WO1995001008A1 - Bit error counting method and counter - Google Patents
Bit error counting method and counter Download PDFInfo
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- WO1995001008A1 WO1995001008A1 PCT/JP1993/000830 JP9300830W WO9501008A1 WO 1995001008 A1 WO1995001008 A1 WO 1995001008A1 JP 9300830 W JP9300830 W JP 9300830W WO 9501008 A1 WO9501008 A1 WO 9501008A1
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- signal
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- error detection
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
- H04L1/208—Arrangements for detecting or preventing errors in the information received using signal quality detector involving signal re-encoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/3961—Arrangements of methods for branch or transition metric calculation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
Definitions
- the present invention relates to a method and apparatus for counting signal errors in a digital communication system, and more particularly, to a method and apparatus for counting signal errors in bit units in a system in which error correction is performed using a viterbi decoding process.
- Background technology a method and apparatus for counting signal errors in bit units in a system in which error correction is performed using a viterbi decoding process.
- the received signal is sent via a communication line or the like.
- This received signal has already undergone coding processing.
- the received signal described above is branched into two, one of which is the Viterbi decoder 901 , and the other is input to the delay unit 902 .
- the Viterbi decoding unit 901 performs a generally known Viterbi decoding process on the received signal.
- This Viterbi decoding is a process of restoring a signal before encoding from a received signal subjected to trellis encoding. This Viterbi decoding will be explained in detail later.
- the signal restored to the state before encoding by the Viterbi decoding unit 901 (hereinafter referred to as the decoded signal) is output as it is and also sent to the convolutional encoding unit 903 .
- the same processing as that for generating the received signal described above is performed. Therefore, the output of this convolutional encoder 903 (hereinafter referred to as re-encoded signal) is considered to be the same as the received signal. .
- the delay unit 902 delays the received signal by a fixed time and outputs it. This delay matches the output timings of the re-encoded signal and the received signal. For this reason, the delay time of delay section 902 should be substantially equal to the total processing time of Viterbi decoding section 901 and convolutional coding section 903, which will be described later. This delay section 902 does not change the signal in any way other than the time delay as described above.
- This re-encoded signal and the delayed received signal are input to the comparing section 904 .
- the input timings of both are aligned by the effect of the delay section 902 as already described.
- the comparator 904 compares these input signals. Originally, both signals should match, but if a transmission error occurs in the received signal, they will not match at the point where the error occurred.
- the comparison unit outputs an error count according to this non-matching portion.
- circuit provided with a memory for storing received signals instead of the delay unit 902 .
- the received signal stored in the memory is read out in synchronism with the output of the re-encoded signal.
- the comparison unit similarly compares the received signal and the re-encoded signal to detect errors. Disclosure of Invention Technical Problem
- the receiving side must have a reencoding circuit that performs reencoding processing and a comparison processing circuit that compares the reencoded signal with the received signal. Furthermore, the time required for decoding and re-encoding necessitates the delay unit 902 and memory as described above. For this reason, it is inevitable that the scale of the circuit will increase.
- the number of execution steps is large.
- the receiving side will repeat the same encoding or decoding process as the transmitting side. Therefore, re-encoding processing, comparison processing, etc. are required on the receiving side.
- imperfect error correction affects counting. The above technique assumes that the Viterbi-decoded signal at the receiving end is a correct signal. However, there is no means for determining whether or not the Viterbi-decoded signal itself contains an error.
- the present invention extracts the path metric value from the metric memory normally provided in the Virbi decoding unit, selects the minimum value from this path metric value, and counts the number of errors from this minimum value. It is designed to
- the path metric value in a system that transmits a binary code is expressed as the sum of the Hamming distances of paths seen in a trellis diagram, which will be described later.
- the Hamming distance here is defined as follows. That is; the two code sequences U and V are
- V (vl, v2, v3, ⁇ ,vn)
- This Hamming distance is equal to the number of different codes between the two codes when both code sequences are binary signals. Therefore, in general, the greater the number of codes forming a code sequence and the longer the distance between codes, the lower the probability of error occurrence.
- Another representation of the Hamming distance of this code sequence is the path metric value. That is, the Hamming distance between the signal sequence input to the encoder and the decoded signal sequence is equal to the pathmetric value in this system.
- the combination of signals with the smallest Hamming distance is considered to be the closest to the signal before encoding, and the code corresponding to this combination is used as the decoded signal.
- This is the power', Viterbi decoding. Therefore, the Hamming distance of the code sequence increases by 1 each time a 1-bit error occurs in the decoded signal. For this reason, it can be said that the increment of the Hamming distance directly indicates the number of error bits. So this By storing the Hamming distance, it is possible to determine the number of errors. use. Specifically, it is as follows.
- an ACS calculation section when executing Viterbi decoding, an ACS calculation section, a metric memory, a path memory, and a control section for controlling these are used. Therefore, the path metric is calculated from the Hamming distance in the ACS calculation unit, and the path metric is stored in the metric memory, and the path itself giving this path metric is stored in the path memory. Then, the path that minimizes the path metric is selected, and the corresponding signal is adopted as the decoded signal.
- the value of the path metric is extracted and adopted as the number of errors.
- a device for performing such a decoding process is provided both for decoding the audio signal and for decoding the well-known control signal called the FACCH signal. Both of these devices receive the received signal and perform decoding processes suitable for speech and FACCH signals, respectively. By comparing the number of errors obtained from each device as a result of this decoding process, it is possible to identify whether the received signal was a voice signal or a FACCH signal, and to correctly decode the received signal. output stuff.
- beneficial effect Advantageous effects associated with the present invention include: first, hardware simplification by omitting the re-encoding unit, comparison processing unit, delay unit, etc.; The number of steps is reduced, and thirdly, error count accuracy is improved by correcting the number of errors when Viterbi decoding is incorrect.
- the received signal is a voice signal or a FACCH signal can be identified from the received signal itself at the same time as the decoding process.
- FIG. 1 is a flow chart showing the outline of the processing procedure of the embodiment.
- FIG. 2 is a block diagram showing the configuration of a decoding unit
- FIG. 3 is a block diagram showing the configuration of an encoder with a constraint length of 3;
- FIG. 4 is an explanatory diagram showing a trellis figure.
- FIG. 5 is an explanatory diagram showing a partially enlarged trellis figure.
- FIG. 6 is an explanatory diagram showing the calculation of the path metric.
- FIG. 7 is a flow chart showing the procedure of Viterbi decoding.
- FIG. 8 is a flow chart showing a path metric calculation procedure.
- FIG. 9 is a block diagram showing the configuration of a conventional error counting device.
- FIG. 10 is a flow chart showing the signal identification procedure.
- FIG. 11 is a block diagram showing the configuration of a signal identification device.
- BEST MODE FOR CARRYING OUT THE INVENTION The best mode for carrying out the invention, which the applicant considers best, will be described below with appropriate reference to the drawings.
- Decoding is a method of signal transformation that is used in conjunction with encoding.
- encoding refers to a method of converting a digital code or the like to be transmitted based on a specific rule at a transmitting terminal in a system for transmitting digital code or the like.
- Decoding refers to the method of obtaining digital codes prior to encoding based on signals that have been encoded and transmitted from the terminal on the sending side.
- Viterbi decoding is used in combination with trellis coding.
- the purpose of such coding and decoding before and after transmission is to obtain coding gain.
- the coding gain is defined by the difference between the theoretical CN ratio without coding to obtain a constant error rate and the CN ratio after error correction decoding.
- the CN ratio is the ratio between the carrier power of the operating signal and the noise power.
- a convolutional code is generated by mod 2 addition of an input bit with a fixed number of bits preceding it. For this reason, the encoder is formed by a shift register and an exclusive OR circuit as shown in Fig. 3 o
- FIG. 3 shows the configuration of an encoder with a coding rate of 1/2 and a constraint length of 3.
- the coding rate indicates the ratio of the number of input bits to the number of output bits
- the constraint length indicates the number of information bits that affect the output of the encoder.
- 31 is a three stage shift register consisting of (j), (a) and (b). This shift register 31 can be input bit by bit.
- EXOR-1 and EXOR-2 are exclusive OR circuits. Mod 2 addition is performed in each of the exclusive OR circuits EXOR-1 and EXOR-2.
- the outputs X1 and X2 of the exclusive OR circuits EXOR-1 and EXOR-2 are the outputs of the encoder as they are. This output is called the encoded output.
- This encoded output is taken out every time sl bits are input to the shift register 31 . Therefore, for every 1 bit of input data, 1 bit each is obtained from XI and X2, for a total of 2 bits of output.
- FIG. 4 shows this trellis diagram created based on the configuration of the encoder shown in FIG. 3 above.
- the aligned circles show the possible states of the shift register 31, ie the possible states of registers (a) and (b), except for one bit of the latest input of the encoder.
- the shift register of the encoder consists of (k-1) stages, so 2 ⁇ (k-1) states can be taken.
- Fig. 3 there are four possibilities: ' ⁇ , 0', '0, ⁇ , '1, 0', and '1, 1'.
- a circle indicating the state of such a shift register is generally called a node.
- the nodes are arranged in four columns in FIG. These four columns represent four stages of state transitions.
- the output of the encoder is initially indicated by one of the four nodes in the leftmost column. From this state, each time there is a 1-bit input to the encoder, the transition is made to one of the nodes belonging to the next column on the right. In the rightmost state, if there is a 1-bit input to the encoder, a transition to the right also occurs, although not shown.
- This two-digit value indicates the output values (X1, X2) obtained by executing the exclusive OR operations EXOR-1 and EXOR-2 on the data stored in the shift register 31 of the encoder.
- the output XI is the exclusive OR of the 3 bits 1, 0, 1. So it will be 0.
- the output ⁇ 2 is 0 because it is the OR of two bits 1 and 1. For this reason, (00) is assigned to the branch connecting the state "0, 0" in Fig. 4 and the next state "1, 0".
- the encoding process is represented by tracing the transition branches on the trellis diagram.
- the continuation of this branch makes it possible to show the process of transition continuously.
- This continuous process of transition is called a path.
- decoding. process A typical example of this decoding process is the Viterbi decoding process mentioned above. Details of the Viterbi decoding concept and processing procedures are described below.
- Viterbi decoding is a procedure particularly called maximum likelihood decoding among decoding processes. Based on the coded signal, several candidates for the input signal are assumed, and the candidate with the highest probability of being the correct input signal is adopted as the original input signal. be. The procedure is characterized in that decoding is performed based only on the encoded signal and without using other signals. Ru o
- FIG. 2 shows an overview of the decoding apparatus used to implement the present invention.
- the decoding device is composed of an ACS calculator 201, a metric memory 202, a path memory 203, an error calculator 204, and a controller 205 for controlling them.
- Each part except the error calculation part constitutes the Viterbi decoding part.
- This Viterbi decoding unit executes all Viterbi decoding processing.
- FIG. 1 shows the implementation procedure of the present invention.
- the decoding device receives an encoded signal.
- This coded signal is stored in the memory provided in the ACS calculator 201 .
- the stored encoded signal is then retrieved and subjected to Viterbi decoding.
- no. smetric is calculated.
- This path metric is stored in a memory (not shown) in the ACS calculator 201 .
- the path metric is then retrieved and checked to see if it exceeds a predetermined value. If the path metric does not exceed the specified value, the path metric is the number of errors. On the other hand, if the path metric exceeds a predetermined value, another predetermined value is the error count.
- the number of errors, an error correction signal indicating whether or not the path metric is directly used as the number of errors, and a decoded signal obtained as a result of Viterbi decoding are output from the decoding device.
- the ACS calculator 201 receives an encoded signal consisting of the two-system outputs al' and a2' of the encoder shown in FIG.
- the ACS calculator 201 estimates the path described above based on the received encoded signal, and performs processing to restore the signal input to the encoder from this path. The procedure for this processing is described below.
- the received coded signal is simply referred to as the received signal.
- the state of the encoder shift register in response to this received signal is the fourth Any one of the four states of the trellis diagram shown in the figure applies. By the time this state is reached, state transitions must have taken place from one of the initial states at the left end of the trellis diagram along one of the branches shown in Fig. 4.
- each branch has a corresponding branch metric.
- This metric is obtained using the Hamming distance between codewords. That is, the metric for each branch is obtained by comparing the received signal and the metric for each branch using the Hamming distance.
- the path metric is obtained by totaling the metrics of all branches belonging to the path reaching that node.
- FIG. 5 shows an enlarged part of the trellis diagram in FIG.
- Bit strings (a0(m), al(m)) and (b0(m), bl(m)) are assigned to these two branches, respectively.
- Each assigned bit string indicates the encoded output output from the encoder when the state of the encoder transitions through the branches shown in FIG. That is, if the state of the encoder transitioned from state kO to state m, the coded output (a0(m), al(m)) should have been output along with this transition. Similarly, if the encoder state transitioned from state kl to state m, the coded output (b0(m), bl(m)) should have been output along with this transition o
- bit string actually received by the Viterbi decoding unit 901 be (r0(t), rl(t)).
- This bit string may differ from the actual encoded output due to transmission errors.
- a transmission error refers to a signal error that occurs between the output of the encoder and the input to the Viterbi decoder 901. vinegar.
- the Hamming distance between the state transition corresponding to an arbitrary branch and the actually received signal is obtained.
- EXOR laO(m), rO(t)i indicates taking the exclusive OR of a0(m) and r0(t). The same is true for other terms in the above formula.
- the Hamming distance between the received signal and the branch can be obtained by obtaining the exclusive OR of the received signal and the branch for each n bits of the received signal. This Hamming distance is then accumulated over a path consisting of a series of state transitions. The sum of these Hamming distances is the path metric for the entire path. This operation is shown in the following formula.
- s(k0,tl) is the path metric of state k0 at time (t-1) Rick
- s(kl,tl) is the path metric of state kl at time (t-1).
- i) gives a smaller path metric. Based on this result, i) is adopted as the survival path.
- the force s always has four surviving paths. Finally, one must be selected from these four paths. One way to do this is to compare the metrics of the four paths and select the path that gives the smallest path metric. 1) Bits are added and encoded so that one path can be selected.
- FIG. 7 shows the processing performed by the ACS calculation unit 201 and the control unit 205. As shown in FIG. Here, we first calculate the path metric in steps 701 and 702. and select a survival path. This processing procedure is shown in FIG.
- step 801 initial values are set.
- i is the bit number of the received signal encoded by the human input
- t is the number of state transitions in the branch to be operated on
- s2(m) is the number of times the branch reached state m.
- j is the number of bits in the decoded signal.
- step 803 a pair of received signals a'l(i) and a'2(i) are input. This is a signal obtained by adding an error to the signal output from the encoder corresponding to the i-th bit of the signal input to the encoder, each of which occupies one bit. Then, in step 804, branch metrics are calculated. No.
- bl(m, kO), b2(k0), bl(m, kl), and b2(m, kl) shown in Fig. 8 are all obtained by a calculation known to those skilled in the art called a generator polynomial. Desired. These values are either 1 or 0. Branch metrics X and y A set of is obtained, where kO and kl are both values indicating nodes, as in FIG.
- step 805 the determined branch metric is added to the path metric corresponding to the surviving paths to the node in question.
- two types of path metric forces up to branches corresponding to the input received signals a'l(i) and a'2(i) are obtained.
- the surviving path here is selected from all paths consisting of branches corresponding to the (i-1)th state transition in the procedure described below. A specific path.
- step 806 the two path metrics are compared. As a result of this comparison, the path with the smaller path metric is taken as the surviving path.
- the path metric adopted at step 806 is substituted for the variable s2(m) representing the path metric of the surviving path.
- step 809 or step 812 the variable PM(m, t) stored in the path memory is substituted with the value kO indicating the node through which the surviving path passes.
- this Viterbi decoding process may not be able to completely correct errors contained in the received signal.
- it is determined whether or not the already obtained path metric is becoming larger than the set value.
- the path metric is larger than the set value, there are many errors in the decoded signal. In this case, it is the most suitable surviving path in the decoding process described above. It is questionable whether or not he could choose the right path.
- the path metric value stored in the metric memory is read.
- the value of the metric memory corresponds to the maximum likelihood path described above.
- a decoded signal can be obtained by taking this maximum likelihood path. From this, it can be said that the value of the path metric stored in the metric memory corresponds to the decoded signal. Also, no. Since the value of the smetric is the sum of the branch metrics, and the branch metric is determined by the Hamming distance between the branch and the received signal, the maximum likelihood path is the input signal before encoding. Assuming true reproduction, the value of the path metric is found to be equal to the number of erroneous bits in the received signal.
- the path metric value is directly output as the number of errors.
- the average of the number of errors Nov of the latest j errors exceeding the set threshold Ner ( ⁇ Nov) Zj
- correction processing is performed as the number of errors.
- Ner is output from the control unit instead of the path metric value, and the path metric value is invalidated as the output of the number of errors. This correction processing will be described subsequently.
- the number of errors obtained by the method described above can be used to identify the signal. This processing will be described below.
- FIG. 14 is a block diagram showing the outline of the configuration of the signal identification device of the present invention.
- the signal identification device shown in FIG. 14 consists of three main parts. The first is the audio signal decoding unit 111, the second is the FACCH signal decoding unit 112, and the third is the signal identification unit 113. The subsequent processing will be described while referring to the front chart shown in FIG. 10 and the block diagram shown in FIG. 11 in parallel.
- An audio signal or a FACCH signal is input to the signal identification device described above. All of these signals are assumed to be coded. Also, when encoding these signals, the encoding rate, constraint length, generator polynomial, etc. are assumed to be different between the two signals. However, it is not necessary that all these conditions be different. These conditions are fundamentally determined by the audio signal or FACCH signal standards, and more specifically by the encoding procedure. Also, from the point of view of the present invention, it does not matter if the conditions are different enough to cause a difference in the number of errors that occur when the same signal is input.
- voice signal decoding section 111 and FACCH signal decoding section 112 are simultaneously input to the ACS calculation units provided in the audio signal decoding unit 111 and the FACCH signal decoding unit 112, respectively.
- survival path selection is performed according to the method already described. Which path is selected is recorded in the path memory 203 according to this selection. Substantially simultaneously with this, no. The value of the metric is recorded in metric memory 202 . The signal is decoded from this path memory record. On the other hand, from the records in the metric memory 202, the number of errors is calculated using the method described above.
- the surviving path is independently determined using the method described above, and the Hamming distance between this surviving path and the received signal is calculated. to determine the path metric.
- the two types of path metrics obtained in this manner are output as the number of errors, together with the independently determined decoded signal.
- the number of errors differs between speech signal decoding section 111 and FACCH signal decoding section 112 even for the same signal input. This is because the speech signal and the FACCH signal should be decoded based on procedures with different conditions such as coding rate, constraint length, and generator polynomial.
- Decoding is then performed according to the selected survivor path. Also, the number of errors is obtained according to the value of the path metric. Details of the processing will be described below with reference to the flow chart shown in FIG.
- step 1001 the number of errors, correct/incorrect signals, and decoded signals are input in two types, #1 and #2, respectively. These signals are decoded by separate decoding units.
- the number of errors is the value obtained according to the value of the path metric
- the correct/incorrect signal is the
- the signal indicating whether or not the result of error detection is correct, and the decoded signal are the received signals input to the ACS calculator that have undergone Viterbi decoding processing.
- # 1 is the audio signal decoding unit
- Let #2 correspond to the FACCH signal decoder.
- step 1002 it is checked whether the correct/wrong signal #1 is positive. This is the process of determining whether or not the audio signal decoding unit has performed correct decoding. As this signal, an error detection code specified by TIA may be used. As a result, if the correct/wrong signal is positive, it is determined that the decoding has been performed correctly. In this case, it is assumed that the input signal is probably an audio signal.
- step 1003 it is checked whether the number of errors #1 exceeds the set threshold #la. Here, if the number of errors #1 is equal to or less than the set threshold value #la, it can be safely concluded that the input signal is an audio signal.
- step 1004 the identification signal is #1, and the decoded signal #1 and the error number #1 are used as the decoded signal and the error number, respectively.
- the correct/wrong signal #1 is incorrect in step 1002, or if the number of errors #1 exceeds the set threshold value #la in step 1003, the input signal decryption was not performed correctly.
- the input signal was the FACCH signal. If the input signal is a FACCH signal, the input signal should have been correctly decoded in the FACCH signal decoding section.
- step 1005 it is checked in step 1005 whether the number of errors #1 exceeds the set threshold value #lb.
- the value of the set threshold #lb referred to here may be larger or smaller than the set threshold #la.
- the identification signal is #1 in the step, and the decoded signal and the number of errors are the decoded signal Take # 1 and number of errors # 1.
- step 1006 it is checked whether the correct/wrong signal #2 is positive.
- step 1003 When the number of errors #1 exceeds the set threshold value #la, it is similarly checked whether the correct/wrong signal #2 is positive. As a result, if true/false signal #2 is positive, then the human input signal is probably the FACCH signal.
- step 1010 it is determined whether the number of errors #2 exceeds the set threshold #2a. Here, if the number of errors #1 is equal to or less than the set threshold #2a, it can be safely concluded that the input signal is the FACCH signal.
- #2 is used as the identification signal
- decoded signal #2 and error number #2 are used as the decoded signal and error number, respectively.
- step 1006 if the correct/wrong signal #2 is false in step 1006, it is checked in step 1007 if the number of errors #2 is greater than or equal to the set threshold value #2b. As a result, if the number of errors #2 is less than the set threshold value #2b, then in step 1009, the identification signal #2 is set as the decoded signal and the number of errors in the same way as when the correct/wrong signal #2 is positive. Take signal #2 and error number #2.
- the FACCH signal decoding unit It is possible that the signal was not decoded correctly.
- step 1008 error number #1 and error number #2 are compared.
- step 1004 or step 1009 the identification signal, decoded signal, and number of errors with the smaller number of errors are adopted. After that, output these processing results.
- This invention is suitable for various types of communication equipment that transmit digital signals via wireless or wired transmission lines. Suitable for communication equipment that transmits by encoding or decoding,
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Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP93913548A EP0748057B1 (en) | 1993-06-21 | 1993-06-21 | Bit error counting method and counter |
| DE69328636T DE69328636T2 (de) | 1993-06-21 | 1993-06-21 | Bitfehler zählverfahren und zähler |
| PCT/JP1993/000830 WO1995001008A1 (en) | 1993-06-21 | 1993-06-21 | Bit error counting method and counter |
| JP7502637A JP2917177B2 (ja) | 1993-06-21 | 1993-06-21 | 誤り検出方法、装置ならびに識別方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP1993/000830 WO1995001008A1 (en) | 1993-06-21 | 1993-06-21 | Bit error counting method and counter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO1995001008A1 true WO1995001008A1 (en) | 1995-01-05 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP1993/000830 Ceased WO1995001008A1 (en) | 1993-06-21 | 1993-06-21 | Bit error counting method and counter |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0748057B1 (ja) |
| JP (1) | JP2917177B2 (ja) |
| DE (1) | DE69328636T2 (ja) |
| WO (1) | WO1995001008A1 (ja) |
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| JP2006262394A (ja) * | 2005-03-18 | 2006-09-28 | Nec Corp | 復号回路及び復号方法 |
| JP2011517255A (ja) | 2008-04-15 | 2011-05-26 | クゥアルコム・インコーポレイテッド | チャネルデコーディングに基づいたエラー検出 |
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| DE19647314A1 (de) * | 1996-11-13 | 1998-05-14 | Siemens Ag | Verfahren zum Erkennen von Fehlern bei der Datenübertragung |
| FI102335B1 (fi) | 1997-02-28 | 1998-11-13 | Nokia Telecommunications Oy | Vastaanottomenetelmä ja vastaanotin |
| US6553065B1 (en) * | 1999-02-04 | 2003-04-22 | Nokia Corporation | Mobile station employing CRC verification using decoding reliability and methods therefor |
| US6668298B1 (en) * | 1999-12-29 | 2003-12-23 | Intel Corporation | Shifting an input signal from a high-speed domain to a lower-speed domain |
| US7010731B2 (en) * | 2002-08-14 | 2006-03-07 | Intel Corporation | Method and apparatus of generating a quality indicator |
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| JPS61338U (ja) * | 1984-06-06 | 1986-01-06 | クラリオン株式会社 | 復号装置 |
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| GB8327084D0 (en) * | 1983-10-11 | 1983-11-09 | Gordon J | Error correction decoder apparatus |
| CA1260143A (en) * | 1986-02-24 | 1989-09-26 | Atsushi Yamashita | Path trace viterbi decoder |
| US4823346A (en) * | 1986-04-16 | 1989-04-18 | Hitachi, Ltd. | Maximum likelihood decoder |
| US5050191A (en) * | 1989-10-24 | 1991-09-17 | Hughes Aircraft Company | Synchronization detector using path metric and branch metric values of a Viterbi decoder |
| EP0426894A1 (de) * | 1989-11-08 | 1991-05-15 | Siemens Aktiengesellschaft | Verfahren zur schnellen Empfängersynchronisation unter Ausnutzung einer fehlerkorrigierenden Codierung |
| JP2594683B2 (ja) * | 1990-05-18 | 1997-03-26 | 三菱電機株式会社 | ヴィタビ・デコーダ |
| FR2664111A1 (fr) * | 1990-06-28 | 1992-01-03 | Alcatel Transmission | Circuit de decodage de codes convolutionnels pour l'execution de l'etape de stockage et d'exploration inverse des chemins survivants d'un algorithme de viterbi. |
| JP3120511B2 (ja) * | 1991-11-21 | 2000-12-25 | ソニー株式会社 | ビタビ復号装置 |
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1993
- 1993-06-21 DE DE69328636T patent/DE69328636T2/de not_active Expired - Lifetime
- 1993-06-21 WO PCT/JP1993/000830 patent/WO1995001008A1/ja not_active Ceased
- 1993-06-21 EP EP93913548A patent/EP0748057B1/en not_active Expired - Lifetime
- 1993-06-21 JP JP7502637A patent/JP2917177B2/ja not_active Expired - Fee Related
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| JPS636173B2 (ja) * | 1980-06-03 | 1988-02-08 | Japan Broadcasting Corp | |
| JPS61338U (ja) * | 1984-06-06 | 1986-01-06 | クラリオン株式会社 | 復号装置 |
| JPS62159519A (ja) * | 1986-01-08 | 1987-07-15 | Hitachi Ltd | 誤り訂正方法及びその装置 |
| JPH01235073A (ja) * | 1988-03-14 | 1989-09-20 | Sony Corp | データ種別検出装置 |
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|---|
| HIROSHI MIYAGAWA, YOSHIHIRO IWATARE, HIDEKI IMAI, "Code Theory", 25 October 1974, SHOKODO K.K. (Tokyo), p. 370, 373, 375. * |
| See also references of EP0748057A4 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006262394A (ja) * | 2005-03-18 | 2006-09-28 | Nec Corp | 復号回路及び復号方法 |
| JP2011517255A (ja) | 2008-04-15 | 2011-05-26 | クゥアルコム・インコーポレイテッド | チャネルデコーディングに基づいたエラー検出 |
| US8879643B2 (en) | 2008-04-15 | 2014-11-04 | Qualcomm Incorporated | Data substitution scheme for oversampled data |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0748057A4 (en) | 1997-07-30 |
| DE69328636T2 (de) | 2001-01-25 |
| DE69328636D1 (de) | 2000-06-15 |
| EP0748057B1 (en) | 2000-05-10 |
| JP2917177B2 (ja) | 1999-07-12 |
| EP0748057A1 (en) | 1996-12-11 |
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