WO1995012164A3 - Frame buffer system designed for windowing operations - Google Patents

Frame buffer system designed for windowing operations Download PDF

Info

Publication number
WO1995012164A3
WO1995012164A3 PCT/US1994/012307 US9412307W WO9512164A3 WO 1995012164 A3 WO1995012164 A3 WO 1995012164A3 US 9412307 W US9412307 W US 9412307W WO 9512164 A3 WO9512164 A3 WO 9512164A3
Authority
WO
WIPO (PCT)
Prior art keywords
array
frame buffer
groups
columns
adjacent columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1994/012307
Other languages
French (fr)
Other versions
WO1995012164A2 (en
Inventor
Curtis Priem
Shuen Chin Chang
Hai Duy Ho
Szu Cheng Sun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Semiconductor Inc
Sun Microsystems Inc
Original Assignee
Samsung Semiconductor Inc
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Semiconductor Inc, Sun Microsystems Inc filed Critical Samsung Semiconductor Inc
Priority to DE69432512T priority Critical patent/DE69432512T2/en
Priority to EP94932066A priority patent/EP0677190B1/en
Priority to KR1019950702526A priority patent/KR100335474B1/en
Priority to JP7512813A priority patent/JPH08505255A/en
Publication of WO1995012164A2 publication Critical patent/WO1995012164A2/en
Publication of WO1995012164A3 publication Critical patent/WO1995012164A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/024—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using colour registers, e.g. to control background, foreground, surface filling
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/02—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed
    • G09G5/022—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the way in which colour is displayed using memory planes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Memory System (AREA)
  • Digital Computer Display Output (AREA)

Abstract

A frame buffer (17) designed to be coupled to a data bus (12) and to an output display (18) in a computer system (Figure 1), the frame buffer (Frame 3) including an array of memory cells (52) for storing data indicating pixels to be displayed on the output display, address decoding apparatus (54 and 56) for controlling access to the array, the address decoding apparatus including column address decoding apparatus (56) for selecting groups of adjacent columns of the array, a plurality of apparatus for selectively writing to each of the columns of any of said groups of adjacent columns, a plurality of color value registers (C0 and C1), latching apparatus (57) for storing pixel data equivalent to a row of pixel data to be displayed on the output display, apparatus for writing pixel data from selected groups of adjacent columns of the array to the latching apparatus, and apparatus (58) for connecting either selected ones of the color value registers, the latches, or the data bus to the apparatus for selectively writing to each of the columns of any of said groups of adjacent columns.
PCT/US1994/012307 1993-10-29 1994-10-27 Frame buffer system designed for windowing operations Ceased WO1995012164A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE69432512T DE69432512T2 (en) 1993-10-29 1994-10-27 GRID BUFFER SYSTEM DESIGNED FOR WINDOW ENVIRONMENTAL OPERATIONS
EP94932066A EP0677190B1 (en) 1993-10-29 1994-10-27 Frame buffer system designed for windowing operations
KR1019950702526A KR100335474B1 (en) 1993-10-29 1994-10-27 Frame Buffer System Designed by Window Influence
JP7512813A JPH08505255A (en) 1993-10-29 1994-10-27 Frame buffer system for window operation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14533593A 1993-10-29 1993-10-29
US08/145,335 1993-10-29

Publications (2)

Publication Number Publication Date
WO1995012164A2 WO1995012164A2 (en) 1995-05-04
WO1995012164A3 true WO1995012164A3 (en) 1995-05-26

Family

ID=22512623

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1994/012307 Ceased WO1995012164A2 (en) 1993-10-29 1994-10-27 Frame buffer system designed for windowing operations

Country Status (6)

Country Link
US (1) US5528751A (en)
EP (1) EP0677190B1 (en)
JP (1) JPH08505255A (en)
KR (1) KR100335474B1 (en)
DE (1) DE69432512T2 (en)
WO (1) WO1995012164A2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5539430A (en) * 1993-10-29 1996-07-23 Sun Microsystems, Inc. Pipelined read write operations in a high speed frame buffer system
EP0677200B1 (en) * 1993-10-29 2002-04-03 Sun Microsystems, Inc. Method for increasing the rate of scrolling in a frame buffer
US5764963A (en) * 1995-07-07 1998-06-09 Rambus, Inc. Method and apparatus for performing maskable multiple color block writes
US6104658A (en) * 1996-08-08 2000-08-15 Neomagic Corporation Distributed DRAM refreshing
US6230235B1 (en) 1996-08-08 2001-05-08 Apache Systems, Inc. Address lookup DRAM aging
US5781200A (en) * 1996-08-08 1998-07-14 Ulsi Systems Tile memory mapping for increased throughput in a dual bank access DRAM
KR100300972B1 (en) * 1997-09-19 2001-09-03 윤종용 Texture mapping system and texture cache access method
US6542796B1 (en) * 2000-11-18 2003-04-01 Honeywell International Inc. Methods and apparatus for integrating, organizing, and accessing flight planning and other data on multifunction cockpit displays
TW514863B (en) * 2001-12-14 2002-12-21 Chi Mei Electronics Corp Overdrive system and method of liquid crystal display
CN100350448C (en) * 2001-12-27 2007-11-21 奇美电子股份有限公司 Liquid crystal display overload driving system and method
US7313764B1 (en) * 2003-03-06 2007-12-25 Apple Inc. Method and apparatus to accelerate scrolling for buffered windows
US8159440B2 (en) 2003-06-30 2012-04-17 Advanced Micro Devices, Inc. Controller driver and display apparatus using the same
US7573491B2 (en) * 2004-04-02 2009-08-11 David Hartkop Method for formatting images for angle-specific viewing in a scanning aperture display device
EP1622111A1 (en) * 2004-07-28 2006-02-01 Deutsche Thomson-Brandt Gmbh Line driver circuit for active matrix display device
JP4404116B2 (en) * 2007-08-14 2010-01-27 セイコーエプソン株式会社 Image processing circuit, display device and printing device
JP4488042B2 (en) * 2007-08-14 2010-06-23 セイコーエプソン株式会社 Image processing circuit, display device and printing device
TWI416500B (en) * 2009-12-28 2013-11-21 Inventec Besta Co Ltd Display system and speeding method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4648077A (en) * 1985-01-22 1987-03-03 Texas Instruments Incorporated Video serial accessed memory with midline load
US4823302A (en) * 1987-01-30 1989-04-18 Rca Licensing Corporation Block oriented random access memory able to perform a data read, a data write and a data refresh operation in one block-access time
US5046023A (en) * 1987-10-06 1991-09-03 Hitachi, Ltd. Graphic processing system having bus connection control capable of high-speed parallel drawing processing in a frame buffer and a system memory

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4769637A (en) * 1985-11-26 1988-09-06 Digital Equipment Corporation Video display control circuit arrangement
US5170157A (en) * 1986-05-20 1992-12-08 Takatoshi Ishii Memory device for an image display apparatus having a serial port and independently operable data registers
JPS63204595A (en) * 1987-02-20 1988-08-24 Fujitsu Ltd Multi-plane video ram constituting system
US4807189A (en) * 1987-08-05 1989-02-21 Texas Instruments Incorporated Read/write memory having a multiple column select mode
US5305078A (en) * 1992-01-21 1994-04-19 Exfo Electro-Optical Engineering Inc. Measurement of attenuation of optical fibers using transmitted wavelength and power information
US5282177A (en) * 1992-04-08 1994-01-25 Micron Technology, Inc. Multiple register block write method and circuit for video DRAMs

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4648077A (en) * 1985-01-22 1987-03-03 Texas Instruments Incorporated Video serial accessed memory with midline load
US4823302A (en) * 1987-01-30 1989-04-18 Rca Licensing Corporation Block oriented random access memory able to perform a data read, a data write and a data refresh operation in one block-access time
US5046023A (en) * 1987-10-06 1991-09-03 Hitachi, Ltd. Graphic processing system having bus connection control capable of high-speed parallel drawing processing in a frame buffer and a system memory

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0677190A4 *

Also Published As

Publication number Publication date
EP0677190A1 (en) 1995-10-18
EP0677190B1 (en) 2003-04-16
KR100335474B1 (en) 2002-09-26
EP0677190A4 (en) 1996-07-24
WO1995012164A2 (en) 1995-05-04
KR950704741A (en) 1995-11-20
JPH08505255A (en) 1996-06-04
DE69432512D1 (en) 2003-05-22
US5528751A (en) 1996-06-18
DE69432512T2 (en) 2004-04-22

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