WO1996026604A3 - Device for deriving a clock signal from a synchronizing signal and a video recorder provided with the device - Google Patents

Device for deriving a clock signal from a synchronizing signal and a video recorder provided with the device Download PDF

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Publication number
WO1996026604A3
WO1996026604A3 PCT/IB1996/000078 IB9600078W WO9626604A3 WO 1996026604 A3 WO1996026604 A3 WO 1996026604A3 IB 9600078 W IB9600078 W IB 9600078W WO 9626604 A3 WO9626604 A3 WO 9626604A3
Authority
WO
WIPO (PCT)
Prior art keywords
input
output
control signal
preset control
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB1996/000078
Other languages
French (fr)
Other versions
WO1996026604A2 (en
Inventor
Jurgen Holger Titus Geerlings
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Philips Norden AB
Original Assignee
Philips Electronics NV
Philips Norden AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV, Philips Norden AB filed Critical Philips Electronics NV
Priority to EP96900415A priority Critical patent/EP0756799B1/en
Priority to DE69613282T priority patent/DE69613282T2/en
Priority to AT96900415T priority patent/ATE202253T1/en
Priority to JP8525520A priority patent/JPH09512415A/en
Publication of WO1996026604A2 publication Critical patent/WO1996026604A2/en
Publication of WO1996026604A3 publication Critical patent/WO1996026604A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/93—Regeneration of the television signal or of selected parts thereof
    • H04N5/95—Time-base error compensation
    • H04N5/956—Time-base error compensation by using a digital memory with independent write-in and read-out clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
    • H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/91—Television signal processing therefor
    • H04N5/93—Regeneration of the television signal or of selected parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Television Signal Processing For Recording (AREA)
  • Synchronizing For Television (AREA)

Abstract

A device for deriving a clock signal having a specific frequency (fcl) from a synchronizing signal (Hsync) derived from an electrical signal, for example a video signal, comprises: an input terminal (1) for receiving the synchronizing signal; a phase comparator (5) having a first input coupled to the input terminal, a second input and an output; a voltage controlled oscillator (15) having an input coupled to the output of the phase comparator and an output; counter means (23) having a first input coupled to the output of the voltage controlled oscillator, a second input for receiving a preset control signal and an output coupled to the second input of the phase comparator; preset control signal generator means (30) having an input coupled to the input terminal and an output coupled to the second input of the counter means, the counter means being adapted to set its count value to a preset value in response to the preset control signal applied to its preset control signal input. The preset control signal generator means comprises: window signal generator means (48) for determining a window signal in response to a specified count value of the counter means; detector means (34, 36) for detecting whether at least one edge in the synchronizing signal falls outside a time interval defined by the window signal and for generating said preset control signal in response to said detection, said detector means having an input coupled to the input of the preset control signal generator means and an output coupled to the output of said preset control signal generator means.
PCT/IB1996/000078 1995-02-20 1996-01-29 Device for deriving a clock signal from a synchronizing signal and a video recorder provided with the device Ceased WO1996026604A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP96900415A EP0756799B1 (en) 1995-02-20 1996-01-29 Device for deriving a clock signal from a synchronizing signal and a video recorder provided with the device
DE69613282T DE69613282T2 (en) 1995-02-20 1996-01-29 DEVICE FOR DERIVING A CLOCK SIGNAL FROM A SYNCHRONOUS SIGNAL AND VIDEO RECORDING DEVICE EQUIPPED WITH SUCH A CIRCUIT ARRANGEMENT
AT96900415T ATE202253T1 (en) 1995-02-20 1996-01-29 DEVICE FOR DERIVING A CLOCK SIGNAL FROM A SYNCHRONOUS SIGNAL AND VIDEO RECORDING DEVICE EQUIPPED WITH THE DEVICE
JP8525520A JPH09512415A (en) 1995-02-20 1996-01-29 Device for obtaining clock signal from synchronization signal and video recorder provided with this device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP95200403.4 1995-02-20
EP95200403 1995-02-20

Publications (2)

Publication Number Publication Date
WO1996026604A2 WO1996026604A2 (en) 1996-08-29
WO1996026604A3 true WO1996026604A3 (en) 1996-10-31

Family

ID=8220032

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1996/000078 Ceased WO1996026604A2 (en) 1995-02-20 1996-01-29 Device for deriving a clock signal from a synchronizing signal and a video recorder provided with the device

Country Status (6)

Country Link
US (1) US5877640A (en)
EP (1) EP0756799B1 (en)
JP (1) JPH09512415A (en)
AT (1) ATE202253T1 (en)
DE (1) DE69613282T2 (en)
WO (1) WO1996026604A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19737326A1 (en) * 1997-08-27 1999-03-04 Thomson Brandt Gmbh Method for obtaining line synchronization information from a video signal and device for carrying out the method
WO1999013582A1 (en) * 1997-09-09 1999-03-18 Advanced Fibre Communications, Inc. Perturbation tolerant digital phase-locked loop employing phase-frequency detector
US6556249B1 (en) * 1999-09-07 2003-04-29 Fairchild Semiconductors, Inc. Jitter cancellation technique for video clock recovery circuitry
US6741289B1 (en) * 2000-10-31 2004-05-25 Fairchild Semiconductors, Inc. Technique to stabilize the chrominance subcarrier generation in a line-locked digital video system
US6472913B2 (en) * 2001-01-26 2002-10-29 Oki Electric Industry Co., Ltd Method and apparatus for data sampling
FR2831756B1 (en) * 2001-10-26 2004-01-30 St Microelectronics Sa METHOD AND DEVICE FOR SYNCHRONIZING A REFERENCE SIGNAL ON A VIDEO SIGNAL
FR2868891B1 (en) * 2004-04-08 2006-07-07 Eads Telecom Soc Par Actions S HALF LOADED PHASE STACK LOOP
DE102018100692B4 (en) * 2018-01-12 2019-08-22 Infineon Technologies Ag Method for monitoring a battery, monitoring system and monitoring circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043966A (en) * 1988-05-25 1991-08-27 U.S. Philips Corporation Device for deriving a sampling rate
EP0555569A1 (en) * 1992-02-11 1993-08-18 International Business Machines Corporation Signal processing apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573634A (en) * 1968-09-04 1971-04-06 Bell Telephone Labor Inc Timing of regenerator and receiver apparatus for an unrestricted digital communication signal
US3701953A (en) * 1970-11-16 1972-10-31 Telecommunications Technology Digital phase lock loop circuit employing oscillator triggered at zero voltage crossing of input signal
JPH0292021A (en) * 1988-09-29 1990-03-30 Mitsubishi Rayon Co Ltd Digital PLL circuit
JPH071423B2 (en) * 1988-12-20 1995-01-11 株式会社山下電子設計 Pulse generator
JPH0799446A (en) * 1993-03-02 1995-04-11 Mitsubishi Electric Corp PLL circuit
US5457428A (en) * 1993-12-09 1995-10-10 At&T Corp. Method and apparatus for the reduction of time interval error in a phase locked loop circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043966A (en) * 1988-05-25 1991-08-27 U.S. Philips Corporation Device for deriving a sampling rate
EP0555569A1 (en) * 1992-02-11 1993-08-18 International Business Machines Corporation Signal processing apparatus

Also Published As

Publication number Publication date
WO1996026604A2 (en) 1996-08-29
ATE202253T1 (en) 2001-06-15
JPH09512415A (en) 1997-12-09
EP0756799A1 (en) 1997-02-05
DE69613282D1 (en) 2001-07-19
EP0756799B1 (en) 2001-06-13
DE69613282T2 (en) 2002-05-02
US5877640A (en) 1999-03-02

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