WO1997048048A1 - Word width selection for sram cache - Google Patents

Word width selection for sram cache Download PDF

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Publication number
WO1997048048A1
WO1997048048A1 PCT/US1997/010184 US9710184W WO9748048A1 WO 1997048048 A1 WO1997048048 A1 WO 1997048048A1 US 9710184 W US9710184 W US 9710184W WO 9748048 A1 WO9748048 A1 WO 9748048A1
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Prior art keywords
data
bit
bus
logic
cache memory
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PCT/US1997/010184
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French (fr)
Inventor
Joseph Thomas Pawlowski
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Micron Technology Inc
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Micron Technology Inc
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Priority to AU33896/97A priority Critical patent/AU3389697A/en
Priority to EP97929956A priority patent/EP0978041A1/en
Priority to JP50182798A priority patent/JP3569735B2/en
Priority to KR1019980710264A priority patent/KR100322366B1/en
Publication of WO1997048048A1 publication Critical patent/WO1997048048A1/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1064—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in cache or content addressable memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access

Definitions

  • the present invention relates to digital computers in general, and to computer memory in particular. More particular still, this invention relates to logic implementation of cache memory.
  • a memory hierarchy comprises a number of different memory levels, sizes and speeds.
  • the memory located near or inside the processor is usually the smallest and fastest and is commonly referred to as cache memory.
  • Cache memory needs to be fast to accommodate the demand of the processor therefore it is usually constructed from static-type memory or static random access memory (SRAM).
  • Cache memory plays an important role in the computer memory hierarchy. Computer instructions and data which are most likely to be reused are stored temporarily in the cache memory because the processor can access these instructions or data much faster than accessing them from the slower computer main memory.
  • a processor-cache interface uses a 64-bit bus data an additional bus for tag.
  • the tag bus width varies, but has nominally been 16 bits for a total of 80 bits wide for tag plus data. If the cache block (or cache line) size is four times the data bus width, then no useful information appears on the tag bus for three out of every four bus cycles therefore the bus is not utilized efficiently.
  • This logic could implement a 64-bit data bus plus a 16-bit or more tag bus but the same logic is also usable to implement a 96-bit bus.
  • the present invention describes a selection logic which enables the implementation of an 80-bit wide or a 96-bit wide SRAM in a computer system comprising a microprocessor and a cache memory.
  • the logic enables the implementation of an 80-bit or a 96-bit wide cache SRAM.
  • This logic could also be used to implement two SRAMs having half the width, that is two 40-bit or 48-bit cache SRAMs.
  • the present invention permits higher useful data throughput on an 80 or a 96-bit bus than what has been previously achieved with an 80-bit bus.
  • This logic implementation is accomplished by merging tag, error checking and correction (ECC), and data into an ordered block of information to maximize bus utilization.
  • ECC error checking and correction
  • This logic implementation utilizes useful information on every bus cycle for an 80-bit bus case and it reduces the number of bus cycles from four to three in the case of a 96-bit bus.
  • Figure 1 is a block diagram of a simplified computer system comprising a microprocessor and an 80-bit or a 96-bit cache SRAM.
  • Figure 2 is a block diagram of the 80-/96-bit cache SRAM of Figure 1.
  • Figure 3 is a block diagram of available routes for data transfer from the memory array to the output blocks for the case of a 96-bit implementation.
  • Figures 4A-4D are possible output block selection combinations when the initial address is 00, 01, 10, and 1 1 respectively for the case of a 96-bit implementation.
  • Figures 5A-5E are the combinations of the logic for the case of a 96-bit implementation according to the present invention.
  • Figure 6 is a block diagram of available routes for data transfer from the memory array to the output blocks for the case of an 80-bit implementation.
  • Figures 7A-7D are possible output block selection combinations for the case of an 80-bit implementation.
  • Figures 8A-8E are the combinations of the logic for the case of an 80-bit implementation according to the present invention.
  • Figures 9A-9E are the combinations of the logic for both cases of an 80-bit and a 96-bit implementation according to the present invention.
  • FIG. 1 illustrates a simplified computer system comprising a microprocessor 150 connected to an 80-/96-bit cache SRAM 100 through a processor-cache interface 160.
  • Processor-cache interface 160 comprises a system clock (CLK), an address data strobe (ADS#), a read or write request (RW#), an address bus, a tag bus and an data bus.
  • FIG. 2 is block diagram of the 80-/96-bit cache SRAM 100 of Figure 1.
  • Cache SRAM 100 can support an 80 to 96 bit data bus.
  • the 80-bit or 96-bit operations are accomplished by a data ordering scheme and logic selections of input select logic 106 and output select logic 108.
  • Input and output logic 106 and 108 are logically identical.
  • Data are transferred to and from a data and tag memory array 1 10 in three bus cycles in the case of an 96-bit and in four bus cycles in the case of a 80-bit system.
  • the sequence of the bus cycles is monitored by a bus cycle counter 102.
  • Cycle counter 102 begins when ADS# is low and resets to zero and holds after three counts (cycle 1, cycle2 then cycle3 for a 96-bit system), or after four counts (cyclel, cycle2, cycle3 then cycle4 for an 80-bit system). Data is written to or is read from memory array 1 10 by a write operation or read operation respectively. In the diagram, RW# indicates whether a read or write operation is requested, the sign # indicating that it writes if the signal is low. Address represents the sough memory location in memory array 110. Data represents a composite collection of data and tag bits.
  • Figure 3 is a block diagram of available routes for data to be transferred from the memory array to the output blocks for the case of a 96-bit implementation.
  • This embodiment shows a portion of memory array 210 which comprises four 64-bit longwords A, B, C and D and two tag words totaling up to 32 bits and are indicated as tag.1 and tag.2.
  • Tag in this and in other embodiments represents additional information such as status, ECC, tag, etc.
  • Each of the four 64-bit longwords is divided into four 16-bit words.
  • Longword A has four 16-bit words indicated as 1.1, 1.2, 1.3 and 1.4.
  • Longword B has four 16-bit words indicated as 2.1, 2.2, 2.3 and 2.4.
  • Longword C has four 16-bit words indicated as 3.1, 3.2, 3.3 and 3.4 and longword D has four 16-bit words indicated as 4.1, 4.2, 4.3 and 4.4.
  • Words A, B, C and D in that order, represent the order of data criticality to the processor.
  • the actual physical address which is considered critically ordered differs from processor to processor in existing implementations and may entail a modula-4 linear burst, a modula-4 interleaved order, etc.
  • the optimal order is modula-4 linear burst. This ordering is shown in Table A. Any other ordering for this type of processor will prevent maximization of performance for a processor designed to utilize the 96-bit operation.
  • Table A Linear Burst Data Ordering in a Four Entry Cache Line Initial address A B C D xOO xOO xOl xl O xl l xOl xOl xlO xl l xOO xlO xl O xl l xOO xOl xl l xl l xOO xOl xlO
  • Table B Interleaved Burst Data Ordering in a Four Entry Cache Line Initial address A B C D xOO xOO xOl xlO xl l xOl xOl xOO xl l xl O xl O xl O xl O xl l xOO xOl xl l xl l xlO xOl xOO
  • the order in which the cache line data words are transferred is programmable. Such a device would permit, for example, both interleaved and linear burst data ordering with the same cache device. In another embodiment, data ordering could be changed to reflect characteristics of the programs or programs being executed (e.g. a program operating at particular stride through memory).
  • data are transferred from memory array 210 to output blocks 230 by a logic selection from a plurality of pathways 220.
  • Pathways 220 comprises thirty-four routes in which six routes 221 through 226 are connected to the output blocks 230 at each 16-bit output blocks 231 through 236 indicated respectively as OBI to OB6.
  • An output block is comprised of output buffers and optionally data registers or latches. The logic which enables six of these thirty-four available routes will be described below.
  • Figures 4A-4D are possible output block selection combinations when the initial address is 00, 01, 10, and 1 1 respectively for the case of a 96-bit implementation. These Figures clearly shows that a 96-bit bus can be implemented using only three bus cycles. Tag only appears in the first bus cycle (cycle 1), freeing the input/output lines for data transfer during cycle two (cycle2) and cycle three (cycle3). This ordering simplies the logic needed to transfer the cache line data words and reduces the number of paths that must be available. The logic which enables these possible output block selection combinations is described in Figures 5A-5E.
  • Figures 5A-5E are the combinations of the logic for the case of a 96-bit implementation.
  • the logic comprises a combination of input 410, logic gates 420 and a plurality of outputs 430.
  • Logic gates 420 comprises a plurality of logic AND and logic OR gates.
  • Input 410 driving the logic comprises cycle 1, cycle2, cycle3, A0 and Al .
  • A0 and Al represent the two least significant bits of the initial address.
  • Cyclel , cycle2 or cycle3 is the current bus cycle determined by bus cycle counter 102.
  • Outputs 430 from this logic enables the data to be transferred to the appropriate blocks OBI through OB6 of output blocks 230.
  • Table 1 Detailed combinations of the logic enabling at output 430 are described in Table 1.
  • OB represents output block
  • IA represents the least two significant bits of the initial address
  • tag.l and tag.2 represent the miscellaneous additional information such as status, ECC, tag, etc.
  • 1.1 represents datum 1 : word 1 in the current cache line
  • 1.2 represents datum 1 ; word 2, etc.
  • Table 1 Logic for a 96-bit Linear Burst Data Ordering Implementation
  • a 96-bit bus implementation could also be used to implement a 96-bit wide device using two 48-bit wide devices.
  • the 96-bit implementation for the two 48- bit wide devices would be implemented as such: all the even words are in one device, and all the odd words are in the other device.
  • words 1.4. 2.4, 3,4 , 4.4, 1.2, 2.2, 3.2, 4.2 (x.4, x.2), OB6, OB4, OB2 are in one device, and x.3, x.l, OB5, OB3, OBI are in the other device.
  • the described logic operates exactly as explained and the devices operate together seamlessly, and only one design is necessary; two identical devices are used in the implementation.
  • Figure 6 is a block diagram of available routes for data to be transferred from the memory array to the output blocks for the case of an 80-bit implementation.
  • longwords A, B, C and D are arranged in the same structure in the portion of memory array 510 as in Figure 3 for the case of 96-bit implementation however, up to four tag words indicated as tag.1, tag.2, tag.3 and tag.4 can be utilized.
  • the output blocks 530 in this embodiment comprises five 16-bit output block 531, 533, 534, 535 and 536 which are indicated respectively as OBI, OB3, OB4, OB5 and OB6. Data are transferred from the memory array 510 to output blocks 530 by a logic selection from a plurality of pathways 520.
  • Pathways 520 comprises up to twenty routes in which five routes 521, 523, 524, 525 and 526 are connected to output blocks 530.
  • Figures 7A-7D are possible output block selection combinations when the initial address is 00, 01, 10, and 1 1 respectively for the case of an 80-bit implementation. These Figures shows that four bus cycles are needed for data transfer. In this case, tag or useful information appears on every bus cycles (cyclel through cycle4) therefore it is an efficient utilization of bus. In this 80- bit implementation, to maximize performance, the tag limit is 16 bits. If more tag bits are need, the 80-bits would be expanded within reason to accommodate the additional necessary bits. For example, if a 20-bit tag is essential, this would entail an 84-bit bus. 11 bits of ECC is sufficient regardless of tag size, within reason. The logic which enables these possible output block selection combinations is described in Figures 8A-8E.
  • Figures 8A-8E are the combinations of the logic for the case of an 80-bit implementation.
  • the logic comprises a combination of input 710, logic gates 720 and a plurality of outputs 730.
  • Logic gates 720 comprises logic a plurality of logic AND and logic OR gates.
  • Input 710 driving the logic comprises cyclel , cycle2, cycle3, cycle4, AO and Al.
  • AO and Al represent the two least significant bits of the initial address.
  • Cyclel, cycle2 or cycle3 is the current bus cycle determined by bus cycle counter 102.
  • Outputs 730 from this logic enables the data to be transferred to the appropriate blocks of output blocks 530.
  • OB represents output block
  • IA represents the least two significant bits of the initial address
  • tag.l and tag.2 represent the miscellaneous additional information such as status, ECC, tag, etc.
  • 1.1 represents datum 1 : word 1 in the current cache line
  • 1.2 represents datum 1 ; word 2, etc.
  • Table 2 Logic for an 80-bit Linear Burst Data Ordering Implementation
  • the implementation for a 80-bit wide device described above could also be used to implement an 80-bit bus wide in a memory device using more than one device.
  • OBI would have to be split into two 8-bit halves so that two such identical devices would comprise the 80-bit bus device.
  • the tag and OB 1 is split evenly among four devices.
  • Figures 9A-9E From the illustrations and descriptions of Figure 3 through Figure 8E, it is apparent that there are commonality in the available pathways and in the logic selections between the 80-bit and 96 bit implementations. Further examining of Figure 3 (available routes for a 96-bit implementation) and Figure 6 (available routes for an 80-bit implementation), a conclusion can be drawn that Figure 6 is a subset of Figure 3. Further examining of Figures 5A-5E (logic for a 96-bit implementation) and Figures 8A-8E (logic for an 80-bit implementation) and also Table 1 and Table 2, a modification could be made to the logic so that it can implement both 80-bit and 96-bit implementation from the same memory array. Thus the block diagram of the routes in Figure 3 can be used for both cases of an 80-bit and 96-bit implementation, and the modified logic to implement both cases is illustrated in Figures 9A-9E.
  • Figures 9A-9E are the combinations of the logic for both cases of an 80- bit and a 96-bit implementation according to the present invention. This embodiment shows the logical differences between the 80-bit and the 96-bit implementation and identifies the logic that is common and specific to each implementation.
  • the common logic in each Figure is the entire logic excluding optional logic indicated at 96 and optional logic indicated at 80.
  • the common logic and optional logic 96 are active only in the case of a 96-bit implementation.
  • the common logic and optional logic 80 are active only in the case of an 80-bit implementation.
  • an 80-bit implementation is carried out by four bus cycles and useful information is on every cycle therefore the bus utilization is more efficient.
  • a 96-bit implementation requires only three instead of four cycles thus speeding up the data transaction process.
  • the block selections described in these embodiments are in terms of output but it is also understood that the input ordering is identical and follows the same logic. Furthermore it is clear that implementation of an 80-bit and a 96-bit device using the same memory array can be obtained by the logic described in the present invention.

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Abstract

A logic which enables implementation of an 80-bit wide or a 96-bit wide cache SRAM using the same memory array. The logic implementation is accomplished by merging tag, and data into an order block of information to maximize bus utilization. The logic reduces the bus cycles from four cycles for an 80-bit to three cycles for a 96-bit implementation.

Description

WORD WIDTH SELECTION FOR SRAM CACHE
Field of the Invention
The present invention relates to digital computers in general, and to computer memory in particular. More particular still, this invention relates to logic implementation of cache memory.
Background of the Invention The performance of computer systems, especially personal computers, has improved dramatically due to the rapid growth in computer architecture design and in particular to the performance of computer memory.
Computer processors and memories however have not pursued the same pace of development through the years. Memories are not able to deliver enough response speed to processors. To reduce the gap in speed between the processors and memories, the concept of memory hierarchy was introduced. A memory hierarchy comprises a number of different memory levels, sizes and speeds. The memory located near or inside the processor is usually the smallest and fastest and is commonly referred to as cache memory. Cache memory needs to be fast to accommodate the demand of the processor therefore it is usually constructed from static-type memory or static random access memory (SRAM).
Cache memory plays an important role in the computer memory hierarchy. Computer instructions and data which are most likely to be reused are stored temporarily in the cache memory because the processor can access these instructions or data much faster than accessing them from the slower computer main memory.
Almost all of cache memories are managed by hardware meaning that the cache operation is physically controlled by logic circuits. Implementation of cache memory is not the same in different type of processors since the logic control circuits are different. In some implementations, a processor-cache interface uses a 64-bit bus data an additional bus for tag. The tag bus width varies, but has nominally been 16 bits for a total of 80 bits wide for tag plus data. If the cache block (or cache line) size is four times the data bus width, then no useful information appears on the tag bus for three out of every four bus cycles therefore the bus is not utilized efficiently.
There is a need for a logic to implement a cache SRAM so that the utilization of data and tag bus can be more efficient. This logic could implement a 64-bit data bus plus a 16-bit or more tag bus but the same logic is also usable to implement a 96-bit bus.
Summary of the Invention The present invention describes a selection logic which enables the implementation of an 80-bit wide or a 96-bit wide SRAM in a computer system comprising a microprocessor and a cache memory. In one embodiment, the logic enables the implementation of an 80-bit or a 96-bit wide cache SRAM. This logic could also be used to implement two SRAMs having half the width, that is two 40-bit or 48-bit cache SRAMs. The present invention permits higher useful data throughput on an 80 or a 96-bit bus than what has been previously achieved with an 80-bit bus. This logic implementation is accomplished by merging tag, error checking and correction (ECC), and data into an ordered block of information to maximize bus utilization.
The important advantages of this logic implementation is that it utilizes useful information on every bus cycle for an 80-bit bus case and it reduces the number of bus cycles from four to three in the case of a 96-bit bus.
Brief Description of the Drawings Figure 1 is a block diagram of a simplified computer system comprising a microprocessor and an 80-bit or a 96-bit cache SRAM. Figure 2 is a block diagram of the 80-/96-bit cache SRAM of Figure 1.
Figure 3 is a block diagram of available routes for data transfer from the memory array to the output blocks for the case of a 96-bit implementation.
Figures 4A-4D are possible output block selection combinations when the initial address is 00, 01, 10, and 1 1 respectively for the case of a 96-bit implementation. Figures 5A-5E are the combinations of the logic for the case of a 96-bit implementation according to the present invention.
Figure 6 is a block diagram of available routes for data transfer from the memory array to the output blocks for the case of an 80-bit implementation. Figures 7A-7D are possible output block selection combinations for the case of an 80-bit implementation.
Figures 8A-8E are the combinations of the logic for the case of an 80-bit implementation according to the present invention.
Figures 9A-9E are the combinations of the logic for both cases of an 80-bit and a 96-bit implementation according to the present invention.
Description of the Preferred Embodiment In the following detailed description of the preferred embodiment, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in limiting sense, and the scope of the invention is defined by the appended claims. Figure 1 illustrates a simplified computer system comprising a microprocessor 150 connected to an 80-/96-bit cache SRAM 100 through a processor-cache interface 160. Processor-cache interface 160 comprises a system clock (CLK), an address data strobe (ADS#), a read or write request (RW#), an address bus, a tag bus and an data bus.
Figure 2 is block diagram of the 80-/96-bit cache SRAM 100 of Figure 1. Cache SRAM 100 can support an 80 to 96 bit data bus. The 80-bit or 96-bit operations are accomplished by a data ordering scheme and logic selections of input select logic 106 and output select logic 108. Input and output logic 106 and 108 are logically identical. Data are transferred to and from a data and tag memory array 1 10 in three bus cycles in the case of an 96-bit and in four bus cycles in the case of a 80-bit system. The sequence of the bus cycles is monitored by a bus cycle counter 102. Cycle counter 102 begins when ADS# is low and resets to zero and holds after three counts (cycle 1, cycle2 then cycle3 for a 96-bit system), or after four counts (cyclel, cycle2, cycle3 then cycle4 for an 80-bit system). Data is written to or is read from memory array 1 10 by a write operation or read operation respectively. In the diagram, RW# indicates whether a read or write operation is requested, the sign # indicating that it writes if the signal is low. Address represents the sough memory location in memory array 110. Data represents a composite collection of data and tag bits. Figure 3 is a block diagram of available routes for data to be transferred from the memory array to the output blocks for the case of a 96-bit implementation. This embodiment shows a portion of memory array 210 which comprises four 64-bit longwords A, B, C and D and two tag words totaling up to 32 bits and are indicated as tag.1 and tag.2. Tag in this and in other embodiments represents additional information such as status, ECC, tag, etc. Each of the four 64-bit longwords is divided into four 16-bit words. Longword A has four 16-bit words indicated as 1.1, 1.2, 1.3 and 1.4. Longword B has four 16-bit words indicated as 2.1, 2.2, 2.3 and 2.4. Longword C has four 16-bit words indicated as 3.1, 3.2, 3.3 and 3.4 and longword D has four 16-bit words indicated as 4.1, 4.2, 4.3 and 4.4. In this embodiments, 1.1 represents datum 1 ; word 1, 1.2 represents datum 1 word 2 , 1.3 represents datum 1 ; word 3, and etc. Words A, B, C and D, in that order, represent the order of data criticality to the processor. The actual physical address which is considered critically ordered differs from processor to processor in existing implementations and may entail a modula-4 linear burst, a modula-4 interleaved order, etc. For the typical line addressing microprocessor (e.g. PowerPC or Cyrix Ml), the optimal order is modula-4 linear burst. This ordering is shown in Table A. Any other ordering for this type of processor will prevent maximization of performance for a processor designed to utilize the 96-bit operation. The reason for this is that, in the course of operating on a whole block of data, the highest probability of utilizing data in the block is 100% for the initial address, and less for each subsequent address. The probability is much lower for the previous address. Therefore, if the initial address is 01 , the address before it, namely 00, is probably the least necessary to have and should therefore have less priority. Hence, A, D, C, and D would show the following sequence represented in binary form in which x stands for "any":
Table A: Linear Burst Data Ordering in a Four Entry Cache Line Initial address A B C D xOO xOO xOl xl O xl l xOl xOl xlO xl l xOO xlO xl O xl l xOO xOl xl l xl l xOO xOl xlO
For processors which required interleaved burst order (e.g. Intel Pentium). a modula-4 interleaved burst order could be used. This ordering is shown in Table B.
Table B: Interleaved Burst Data Ordering in a Four Entry Cache Line Initial address A B C D xOO xOO xOl xlO xl l xOl xOl xOO xl l xl O xl O xl O xl l xOO xOl xl l xl l xlO xOl xOO
In one embodiment, the order in which the cache line data words are transferred is programmable. Such a device would permit, for example, both interleaved and linear burst data ordering with the same cache device. In another embodiment, data ordering could be changed to reflect characteristics of the programs or programs being executed (e.g. a program operating at particular stride through memory). Referring again to Figure 3, data are transferred from memory array 210 to output blocks 230 by a logic selection from a plurality of pathways 220. Pathways 220 comprises thirty-four routes in which six routes 221 through 226 are connected to the output blocks 230 at each 16-bit output blocks 231 through 236 indicated respectively as OBI to OB6. An output block is comprised of output buffers and optionally data registers or latches. The logic which enables six of these thirty-four available routes will be described below.
Figures 4A-4D are possible output block selection combinations when the initial address is 00, 01, 10, and 1 1 respectively for the case of a 96-bit implementation. These Figures clearly shows that a 96-bit bus can be implemented using only three bus cycles. Tag only appears in the first bus cycle (cycle 1), freeing the input/output lines for data transfer during cycle two (cycle2) and cycle three (cycle3). This ordering simplies the logic needed to transfer the cache line data words and reduces the number of paths that must be available. The logic which enables these possible output block selection combinations is described in Figures 5A-5E.
Figures 5A-5E are the combinations of the logic for the case of a 96-bit implementation. For this 96-bit case, only three bus cycles are needed and the order of data transaction is cycle 1 , then cycle2, and finally cycle3. In this embodiment, the logic comprises a combination of input 410, logic gates 420 and a plurality of outputs 430. Logic gates 420 comprises a plurality of logic AND and logic OR gates. Input 410 driving the logic comprises cycle 1, cycle2, cycle3, A0 and Al . A0 and Al represent the two least significant bits of the initial address. Cyclel , cycle2 or cycle3 is the current bus cycle determined by bus cycle counter 102. Outputs 430 from this logic enables the data to be transferred to the appropriate blocks OBI through OB6 of output blocks 230. Detailed combinations of the logic enabling at output 430 are described in Table 1. In this table, OB represents output block, IA represents the least two significant bits of the initial address, tag.l and tag.2 represent the miscellaneous additional information such as status, ECC, tag, etc. and 1.1 represents datum 1 : word 1 in the current cache line , 1.2 represents datum 1 ; word 2, etc. Table 1 : Logic for a 96-bit Linear Burst Data Ordering Implementation
Enable tag.l to OBI = Cyclel Enable tag.2 to OB2 = Cyclel Enable 1.1 to OB3 = Cyclel AND (IA=00) OR Cycle2 AND (I A= 1 1 ) OR Cycle3
AND (IA=10) Enable 1.2 to OB4 - Cyclel AND (IA=00) OR Cycle2 AND (IA=1 1) OR Cycle3
AND (I A= 10) Enable 1.3 to OB5 = Cyclel AND (IA=00) OR Cycle2 AND (IA=1 1 ) OR Cycle3 AND (I A= 10)
Enable 1.4 to OB6 = Cyclel AND (IA=00) OR Cyclc2 AND (IA=11) OR Cycle3
AND (I A= 10) Enable 1.1 to OBI = Cycle2 AND (IA=01) Enable 1.2 to OB2 = Cycle2 AND (IA=01) Enable 1.3 to OB 1 = Cycle3 AND (I A=01 ) Enable 1.4 to OB2 = Cycle3 AND (IA=01) Enable 2.1 to OB3 = Cyclel AND (IA=01) OR Cycle2 AND (IA=00) OR Cycle3
AND (IA=1 1) Enable 2.2 to OB4 = Cyclel AND (IA=01) OR Cycle2 AND (IA=00) OR Cycle3 AND (IA=1 1)
Enable 2.3 to OB5 = Cyclel AND (IA=01 ) OR Cycle2 AND (IA=00) OR Cycle3
AND (IA=1 1) Enable 2.4 to OB6 = Cyclel AND (IA=01) OR Cycle2 AND (IA=00) OR Cycle3 AND (IA=11) Enable 2.1 to OBI = Cycle2 AND (IA=10) Enable 2.2 to OB2 = Cycle2 AND (IA=10) Enable 2.3 to OBI = Cycle3 AND (IA=10) Enable 2.4 to OB2 = Cycle3 AND (IA=10)
Enable 3.1 to OB3 = Cyclel AND (IA=10) OR Cycle2 AND (IA=01) OR Cycle3 AND (IA=00) Enable 3.2 to OB4 = Cyclel AND (IA=10) OR Cycle2 AND (IA=01) OR Cycle3
AND (IA=00) Enable 3.3 to OB5 = Cyclel AND (1A=10) OR Cycle2 AND (IA=01) OR Cycle3
AND (IA=00) Enable 3.4 to OB6 = Cyclel AND (IA=10) OR Cycle2 AND (IA=01 ) OR Cycle3
AND (IA=00)
Enable 3.1 to OBI = Cycle2 AND (IA=11)
Enable 3.2 to OB2 = Cycle2 AND (IA=1 1)
Enable 3.3 to OBI = Cycle3 AND (IA=1 1) Enable 3.4 to OB2 = Cycle3 AND (I A= 1 1 )
Enable 4.1 to OB3 = Cyclel AND (IA=1 1) OR Cycle2 AND (IA=10) OR Cycle3
AND (IA=01) Enable 4.2 to OB4 = Cyclel AND (IA=11) OR Cycle2 AND (IA=10) OR Cycle3
AND (IA=01) Enable 4.3 to OB5 = Cyclel AND (IA=1 1) OR Cycle2 AND (IA=10) OR Cycle3
AND (IA=01) Enable 4.4 to OB6 = Cyclel AND (1A=1 1 ) OR Cycle2 AND (IA=10) OR Cycle3
AND (IA=01)
Enable 4.1 to OBI = Cycle2 AND (IA=00) Enable 4.2 to OB2 = Cycle2 AND (IA=00)
Enable 4.3 to OBI = Cycle3 AND (IA=00)
Enable 4.4 to OB2 = Cycle3 AND (IA=00)
Those skilled in the art will readily recognize that the above description for a 96-bit bus implementation could also be used to implement a 96-bit wide device using two 48-bit wide devices. The 96-bit implementation for the two 48- bit wide devices would be implemented as such: all the even words are in one device, and all the odd words are in the other device. For example, words 1.4. 2.4, 3,4 , 4.4, 1.2, 2.2, 3.2, 4.2 (x.4, x.2), OB6, OB4, OB2 are in one device, and x.3, x.l, OB5, OB3, OBI are in the other device. The described logic operates exactly as explained and the devices operate together seamlessly, and only one design is necessary; two identical devices are used in the implementation.
Figure 6 is a block diagram of available routes for data to be transferred from the memory array to the output blocks for the case of an 80-bit implementation. In this embodiment, longwords A, B, C and D are arranged in the same structure in the portion of memory array 510 as in Figure 3 for the case of 96-bit implementation however, up to four tag words indicated as tag.1, tag.2, tag.3 and tag.4 can be utilized. The output blocks 530 in this embodiment comprises five 16-bit output block 531, 533, 534, 535 and 536 which are indicated respectively as OBI, OB3, OB4, OB5 and OB6. Data are transferred from the memory array 510 to output blocks 530 by a logic selection from a plurality of pathways 520. Pathways 520 comprises up to twenty routes in which five routes 521, 523, 524, 525 and 526 are connected to output blocks 530. Figures 7A-7D are possible output block selection combinations when the initial address is 00, 01, 10, and 1 1 respectively for the case of an 80-bit implementation. These Figures shows that four bus cycles are needed for data transfer. In this case, tag or useful information appears on every bus cycles (cyclel through cycle4) therefore it is an efficient utilization of bus. In this 80- bit implementation, to maximize performance, the tag limit is 16 bits. If more tag bits are need, the 80-bits would be expanded within reason to accommodate the additional necessary bits. For example, if a 20-bit tag is essential, this would entail an 84-bit bus. 11 bits of ECC is sufficient regardless of tag size, within reason. The logic which enables these possible output block selection combinations is described in Figures 8A-8E.
Figures 8A-8E are the combinations of the logic for the case of an 80-bit implementation. For this 80-bit case, four bus cycles are needed and the order of data transaction is cyclel , then cycle2, then cycle3, and finally cycle4. In this embodiment, the logic comprises a combination of input 710, logic gates 720 and a plurality of outputs 730. Logic gates 720 comprises logic a plurality of logic AND and logic OR gates. Input 710 driving the logic comprises cyclel , cycle2, cycle3, cycle4, AO and Al. AO and Al represent the two least significant bits of the initial address. Cyclel, cycle2 or cycle3 is the current bus cycle determined by bus cycle counter 102. Outputs 730 from this logic enables the data to be transferred to the appropriate blocks of output blocks 530. Detailed combinations of the logic enabling at output 730 are described in Table 2. In this table, OB represents output block, IA represents the least two significant bits of the initial address, tag.l and tag.2 represent the miscellaneous additional information such as status, ECC, tag, etc. and 1.1 represents datum 1 : word 1 in the current cache line , 1.2 represents datum 1 ; word 2, etc.
Table 2: Logic for an 80-bit Linear Burst Data Ordering Implementation
Enable tag.l to OBI = Cyclel Enable tag.2 to OBI = Cycle2 Enable tag.3 to OB 1 = Cycle3 Enable tag.4 to OBI = Cycle4 Enable 1.1 to OB3 = Cyclel AND (IA=00) OR Cycle2 AND (IA=1 1) OR Cycle3
AND (IA=10) OR Cycle4 AND (IA=01) Enable 1.2 to OB4 = Cyclel AND (IA=00) OR Cycle2 AND (IA=1 1) OR Cycle3 AND (IA=10) OR Cycle4 AND (IA=01 )
Enable 1.3 to OB5 = Cyclel AND (IA=00) OR Cycle2 AND (IA=1 1) OR Cycle3
AND (IA=10) OR Cycle4 AND (IA=01) Enable 1.4 to OB6 = Cyclel AND (IA=00) OR Cycle2 AND (IA=1 1) OR Cycle3
AND (IA=10) OR Cycle4 AND (IA=01 ) Enable 2.1 to OB3 = Cyclel AND (IA=01) OR Cycle2 AND (IA=00) OR Cycle3
AND (IA=1 1) OR Cycle4 AND (IA=10) Enable 2.2 to OB4 = Cyclel AND (IA=01) OR Cycle2 AND (IA=00) OR Cycle3
AND (1A=11) OR Cycle4 AND (IA=10) Enable 2.3 to OB5 = Cyclel AND (IA=01 ) OR Cycle2 AND (IA=00) OR Cycle3 AND (IA=l l) OR Cycle4. ΛND (1A=10) Enable 2.4 to OB6 = Cyclel AND (IA=01) OR Cycle2 AND (IA=00) OR Cycle3
AND (IA=1 1) OR Cycle4 AND (IA=10) Enable 3.1 to OB3 = Cyclel AND (IA=10) OR Cycle2 AND (IA=01) OR Cycle3
AND (IA=00) OR Cycle4 AND (IA=1 1) Enable 3.2 to OB4 = Cyclel AND (I A= 10) OR Cycle2 AND (I A=01 ) OR Cycle3
AND (IA=00) OR Cycle4 AND (IA=1 1) Enable 3.3 to OB5 = Cyclel AND (IA=10) OR Cycle2 AND (IA=01) OR Cycle3
AND (IA=00) OR Cycle4 AND (IA=1 1 ) Enable 3.4 to OB6 = Cyclel AND (IA=10) OR Cycle2 AND (IA=01) OR Cycle3 AND (IA=00) OR Cycle4 AND (IA=1 1 )
Enable 4.1 to OB3 = Cyclel AND (1A=11) OR Cycle2 AND (IA=10) OR Cycle3
AND (IA=01) OR Cycle4 AND (IA=00) Enable 4.2 to OB4 = Cyclel AND (IA=11) OR Cycle2 AND (IA=10) OR Cycle3
AND (IA=01) OR Cycle4 AND (IA=00) Enable 4.3 to OB5 = Cyclel AND (IA=11) OR Cycle2 AND (IA=10) OR Cycle3
AND (IA=01) OR Cycle4 AND (IA=00) Enable 4.4 to OB6 = Cyclel AND (IA=11) OR Cycle2 AND (IA=10) OR Cycle3
AND (IA=01) OR Cycle4 AND (IA=00)
Those skilled in the art will readily recognize that the implementation for a 80-bit wide device described above could also be used to implement an 80-bit bus wide in a memory device using more than one device. For example, if the 80-bit bus is split across two devices, OBI would have to be split into two 8-bit halves so that two such identical devices would comprise the 80-bit bus device. As such only one device type is needed, and that device is used twice. The same principle applied in a four device implementation. In this case, the tag and OB 1 is split evenly among four devices.
From the illustrations and descriptions of Figure 3 through Figure 8E, it is apparent that there are commonality in the available pathways and in the logic selections between the 80-bit and 96 bit implementations. Further examining of Figure 3 (available routes for a 96-bit implementation) and Figure 6 (available routes for an 80-bit implementation), a conclusion can be drawn that Figure 6 is a subset of Figure 3. Further examining of Figures 5A-5E (logic for a 96-bit implementation) and Figures 8A-8E (logic for an 80-bit implementation) and also Table 1 and Table 2, a modification could be made to the logic so that it can implement both 80-bit and 96-bit implementation from the same memory array. Thus the block diagram of the routes in Figure 3 can be used for both cases of an 80-bit and 96-bit implementation, and the modified logic to implement both cases is illustrated in Figures 9A-9E.
Figures 9A-9E are the combinations of the logic for both cases of an 80- bit and a 96-bit implementation according to the present invention. This embodiment shows the logical differences between the 80-bit and the 96-bit implementation and identifies the logic that is common and specific to each implementation. In Figures 9A-9E, the common logic in each Figure is the entire logic excluding optional logic indicated at 96 and optional logic indicated at 80. The common logic and optional logic 96 are active only in the case of a 96-bit implementation. The common logic and optional logic 80 are active only in the case of an 80-bit implementation.
From the detailed description of the invention, an 80-bit implementation is carried out by four bus cycles and useful information is on every cycle therefore the bus utilization is more efficient. A 96-bit implementation requires only three instead of four cycles thus speeding up the data transaction process. The block selections described in these embodiments are in terms of output but it is also understood that the input ordering is identical and follows the same logic. Furthermore it is clear that implementation of an 80-bit and a 96-bit device using the same memory array can be obtained by the logic described in the present invention.

Claims

What is claimed is:
1. A computer system comprising: a processor; a cache memory having a plurality of cache lines and tag lines; and a reconfigurable processor-cache interface including an N-bit data bus wherein the range of N is 64 to 96.
2. The computer system according to claim 1 wherein the N-bit data bus is configurable as 96-bit wide data bus, the width of the cache lines is four times the width of the data bus and a data transaction between the processor and the cache memory is completed in three bus cycles.
3. The computer system according to claim 1 wherein the N-bit data bus is configurable as 80-bit wide data bus, the width of the cache lines is four times the width of the data bus and a data transaction between the processor and the cache memory is completed in four bus cycles.
4. The computer system according to claim 2 wherein the cache lines comprises a plurality of longwords, the tag lines comprises a plurality of tag words, wherein each of the longwords comprises a plurality of words which together with the tag words are merged into an ordered block of information by an ordering scheme to allow the optimal use of the N-bit bus.
5. The computer system according to claim 4 wherein the cache memory further comprises a plurality of data routing pathways which enables the words and tag words to be merged into the ordered block.
6. The computer system according to claim 5 wherein the cache memory further comprises an input selection logic and an output selection logic, which provide logical control to the routing of data on the data routing pathways such that the words and tag words are properly transferred to the ordered block according to the data ordering scheme.
7. The computer system according to claim 6 wherein the input selection logic and the output selection logic are logically the same.
8. The computer system according to claim 3 wherein the cache lines comprises a plurality of longwords, the tag lines comprises a plurality of tag words, wherein each longword comprises a plurality of words which together with the tag words are merged into an ordered block of information by an ordering scheme to allow the optimal use of the N-bit bus.
9. The computer system according to claim 3 wherein the cache memory further comprises a plurality of data routing pathways which enables the words and tag words to be merged into the ordered block.
10. The computer system according to claim 3 wherein the cache memory further comprises an input selection logic and an output selection logic, which provide logical control to the routing of data on the data routing pathways such that the words and tag words are properly transferred to the ordered block according to the data ordering scheme.
1 1. The computer system according to claim 3 wherein the input selection logic and the output selection logic are logically the same.
12. A cache memory, comprising: a memory array having a plurality tag words, and a plurality of longwords including first, second, third and fourth longwords, and wherein each longword comprises a plurality of words; a plurality of output blocks connected to the memory array for holding data; a plurality of data routing pathways comprising thirty-four pathways connected to the output blocks for data transfer between the memory array and the output blocks; a cache interface having an N-bit wide data bus connected to the output blocks; an input select logic having a plurality of common logics, and a plurality of optional logics including first and second optional logics, and a plurality of inputs and outputs; an output select logic having a plurality of common logics, and a plurality of optional logics including first and second optional logics, and a plurality of inputs and outputs; a bus cycles counter producing a plurality of sequential count cycles to keep track of the count cycles of the N-bit wide data bus.
13. The cache memory according to claim 12 wherein the input select logic and the output select logic are logically the same.
14. The cache memory according to claim 13 wherein the input and the output select output logic operate in a way such that the common logics are always operative, the first optional logics are operative only when N is 80, and the second optional logics are operative only when n is 96.
15. The cache memory according to claim 14 wherein the inputs and the outputs of the input and output select logic comprises sequential count cycles of the cycle counter and two least significant digits of the initial address of the longwords.
16. The cache memory according to claim 15 wherein the bus cycle counter resets to zero after counting the first, the second and the third count cycle when the N-bit data bus is a 96-bit wide data bus, and the cycle counter resets to zero after counting the first, the second, the third and the fourth count cycle when the N-bit data bus is a 80-bit wide data bus.
17. The cache memory according to claim 16 wherein all the tag words are transferred on the first bus cycle when the N-bit data bus is a 96-bit wide data bus, and the tag words are present in every bus cycle when the N-bit data bus is an 80-bit wide data bus.
18. The cache memory according to claim 17 wherein the input and output select logic enable up to six of the thirty-four data routing pathways to transfer data from the memory array to the associated output blocks.
19. The cache memory according to claim 18 wherein the input select logic and the output select logic is configured the same.
20. A method of operating a cache memory in a computer system, comprising the steps of: configuring a processor-cache interface as an N-bit data bus where N is between 64 and 96; configuring a cache memory to have a plurality of longwords; ordering the data in the cache memory by priority according to an order critical to the processor to produce a critical order; retrieving the data in the order according to the critical order; logically selecting the data in the order according to the critical order; and outputting the data in the order according the critical order.
21. The method of claim 20 wherein the priority depends on the initial address of the longwords such that the priority is a first priority for an initial address a second priority for each subsequent address and a third priority for the previous address.
22. The method of claim 20 wherein the retrieving of the data is achieved in three bus cycle when the N-data bus is configured as a 96-bit wide data bus.
23. The method of claim 20 wherein the retrieving of the data is achieved in four bus cycles when the N-data bus is configured as a 80-bit wide or more data bus.
24. The method of claim 20 wherein the logical selection of the data to and from the memory array are the same.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998029812A1 (en) * 1997-01-03 1998-07-09 Micron Technology, Inc. Selectable bit width cache memory system and method
US5960453A (en) * 1996-06-13 1999-09-28 Micron Technology, Inc. Word selection logic to implement an 80 or 96-bit cache SRAM
JP2001195603A (en) * 1999-10-28 2001-07-19 Nintendo Co Ltd Vertex cache for three-dimensional graphics

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6385687B2 (en) * 1999-05-14 2002-05-07 Micron Technology, Inc. Method and apparatus for simultaneously accessing the tag and data arrays of a memory device
US6446169B1 (en) 1999-08-31 2002-09-03 Micron Technology, Inc. SRAM with tag and data arrays for private external microprocessor bus
JP2004240713A (en) * 2003-02-06 2004-08-26 Matsushita Electric Ind Co Ltd Data transfer method and data transfer device
US7844767B2 (en) * 2004-05-21 2010-11-30 Intel Corporation Method for identifying bad lanes and exchanging width capabilities of two CSI agents connected across a link
US7123521B1 (en) 2005-04-27 2006-10-17 Micron Technology, Inc. Random cache read
US7444579B2 (en) 2005-04-28 2008-10-28 Micron Technology, Inc. Non-systematic coded error correction
US7653785B2 (en) * 2005-06-22 2010-01-26 Lexmark International, Inc. Reconfigurable cache controller utilizing multiple ASIC SRAMS
US7457901B2 (en) * 2005-07-05 2008-11-25 Via Technologies, Inc. Microprocessor apparatus and method for enabling variable width data transfers
US7502880B2 (en) 2005-07-11 2009-03-10 Via Technologies, Inc. Apparatus and method for quad-pumped address bus
US7441064B2 (en) * 2005-07-11 2008-10-21 Via Technologies, Inc. Flexible width data protocol
US7590787B2 (en) * 2005-07-19 2009-09-15 Via Technologies, Inc. Apparatus and method for ordering transaction beats in a data transfer
US7444472B2 (en) * 2005-07-19 2008-10-28 Via Technologies, Inc. Apparatus and method for writing a sparsely populated cache line to memory
US20070061669A1 (en) * 2005-08-30 2007-03-15 Major Karl L Method, device and system for detecting error correction defects
US7453723B2 (en) 2006-03-01 2008-11-18 Micron Technology, Inc. Memory with weighted multi-page read
US7810017B2 (en) 2006-03-20 2010-10-05 Micron Technology, Inc. Variable sector-count ECC
US7369434B2 (en) * 2006-08-14 2008-05-06 Micron Technology, Inc. Flash memory with multi-bit read
KR100881196B1 (en) 2007-05-29 2009-02-05 삼성전자주식회사 Memory device having a selectable two bit structure and a system having the same
KR102865309B1 (en) * 2020-09-03 2025-09-30 삼성전자주식회사 Semiconductor memory device and operation method thereof

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280598A (en) * 1990-07-26 1994-01-18 Mitsubishi Denki Kabushiki Kaisha Cache memory and bus width control circuit for selectively coupling peripheral devices
US5406525A (en) * 1994-06-06 1995-04-11 Motorola, Inc. Configurable SRAM and method for providing the same

Family Cites Families (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3848234A (en) * 1973-04-04 1974-11-12 Sperry Rand Corp Multi-processor system with multiple cache memories
US4084234A (en) * 1977-02-17 1978-04-11 Honeywell Information Systems Inc. Cache write capacity
JPS5918745B2 (en) 1978-02-15 1984-04-28 富士通株式会社 Memory shared access method
US4386402A (en) * 1980-09-25 1983-05-31 Bell Telephone Laboratories, Incorporated Computer with dual vat buffers for accessing a common memory shared by a cache and a processor interrupt stack
US4953073A (en) 1986-02-06 1990-08-28 Mips Computer Systems, Inc. Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories
US4885680A (en) * 1986-07-25 1989-12-05 International Business Machines Corporation Method and apparatus for efficiently handling temporarily cacheable data
US5091846A (en) * 1986-10-03 1992-02-25 Intergraph Corporation Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5053951A (en) * 1986-12-23 1991-10-01 Bull Hn Information Systems Inc. Segment descriptor unit for performing static and dynamic address translation operations
US5091850A (en) * 1987-09-28 1992-02-25 Compaq Computer Corporation System for fast selection of non-cacheable address ranges using programmed array logic
US5184320A (en) * 1988-02-12 1993-02-02 Texas Instruments Incorporated Cached random access memory device and system
US5255378A (en) * 1989-04-05 1993-10-19 Intel Corporation Method of transferring burst data in a microprocessor
US5155824A (en) 1989-05-15 1992-10-13 Motorola, Inc. System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address
US5015883A (en) * 1989-10-10 1991-05-14 Micron Technology, Inc. Compact multifunction logic circuit
US5164944A (en) * 1990-06-08 1992-11-17 Unisys Corporation Method and apparatus for effecting multiple error correction in a computer memory
JP2646854B2 (en) * 1990-12-18 1997-08-27 三菱電機株式会社 Microprocessor
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
US5228134A (en) * 1991-06-04 1993-07-13 Intel Corporation Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus
JP2836321B2 (en) * 1991-11-05 1998-12-14 三菱電機株式会社 Data processing device
US5469555A (en) * 1991-12-19 1995-11-21 Opti, Inc. Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system
AU3330793A (en) * 1991-12-23 1993-07-28 Intel Corporation Interleaved cache for multiple accesses per clock in a microprocessor
US5586303A (en) * 1992-02-12 1996-12-17 Integrated Device Technology, Inc. Structure and method for providing a cache memory of selectable sizes
US5423016A (en) * 1992-02-24 1995-06-06 Unisys Corporation Block buffer for instruction/operand caches
US5235221A (en) * 1992-04-08 1993-08-10 Micron Technology, Inc. Field programmable logic array with speed optimized architecture
EP0567707A1 (en) * 1992-04-30 1993-11-03 International Business Machines Corporation Implementation of column redundancy in a cache memory architecture
US5220215A (en) * 1992-05-15 1993-06-15 Micron Technology, Inc. Field programmable logic array with two or planes
US5300830A (en) * 1992-05-15 1994-04-05 Micron Semiconductor, Inc. Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control
US5287017A (en) * 1992-05-15 1994-02-15 Micron Technology, Inc. Programmable logic device macrocell with two OR array inputs
US5298803A (en) * 1992-07-15 1994-03-29 Micron Semiconductor, Inc. Programmable logic device having low power microcells with selectable registered and combinatorial output signals
US5361238A (en) * 1993-05-12 1994-11-01 Hughes Aircraft Company Optical cache memory for magnetic and optical disk storage
US5553263A (en) * 1993-07-16 1996-09-03 Unisys Corporation Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory
US5553259A (en) * 1993-07-16 1996-09-03 Unisys Corporation Apparatus and method for synchronizing the simultaneous loading of cache program word addresses in dual slice registers
US5581734A (en) * 1993-08-02 1996-12-03 International Business Machines Corporation Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
US5432804A (en) * 1993-11-16 1995-07-11 At&T Corp. Digital processor and viterbi decoder having shared memory
US5590352A (en) * 1994-04-26 1996-12-31 Advanced Micro Devices, Inc. Dependency checking and forwarding of variable width operands
US5603041A (en) * 1994-12-13 1997-02-11 International Business Machines Corporation Method and system for reading from a m-byte memory utilizing a processor having a n-byte data bus
US5960453A (en) * 1996-06-13 1999-09-28 Micron Technology, Inc. Word selection logic to implement an 80 or 96-bit cache SRAM

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5280598A (en) * 1990-07-26 1994-01-18 Mitsubishi Denki Kabushiki Kaisha Cache memory and bus width control circuit for selectively coupling peripheral devices
US5406525A (en) * 1994-06-06 1995-04-11 Motorola, Inc. Configurable SRAM and method for providing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"FAST TTL BURST CONTROLLER FOR MICROPROCESSOR", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 8, 1 January 1991 (1991-01-01), pages 118 - 120, XP000107015 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5960453A (en) * 1996-06-13 1999-09-28 Micron Technology, Inc. Word selection logic to implement an 80 or 96-bit cache SRAM
US6223253B1 (en) 1996-06-13 2001-04-24 Micron Technology, Inc. Word selection logic to implement an 80 or 96-bit cache SRAM
US6493799B2 (en) 1996-06-13 2002-12-10 Micron Technology, Inc. Word selection logic to implement an 80 or 96-bit cache SRAM
WO1998029812A1 (en) * 1997-01-03 1998-07-09 Micron Technology, Inc. Selectable bit width cache memory system and method
JP2001195603A (en) * 1999-10-28 2001-07-19 Nintendo Co Ltd Vertex cache for three-dimensional graphics

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