WO1998013961A3 - Architecture for a modular communications switching system - Google Patents

Architecture for a modular communications switching system Download PDF

Info

Publication number
WO1998013961A3
WO1998013961A3 PCT/CA1997/000696 CA9700696W WO9813961A3 WO 1998013961 A3 WO1998013961 A3 WO 1998013961A3 CA 9700696 W CA9700696 W CA 9700696W WO 9813961 A3 WO9813961 A3 WO 9813961A3
Authority
WO
WIPO (PCT)
Prior art keywords
resource
bandwidth
payload data
switch
control module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CA1997/000696
Other languages
French (fr)
Other versions
WO1998013961A2 (en
Inventor
Harold J Snow
Edmund Wong
Anatoly Tarsky
Bruce I Barkhouse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nortel Networks Ltd
Original Assignee
Northern Telecom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Northern Telecom Ltd filed Critical Northern Telecom Ltd
Priority to JP51508598A priority Critical patent/JP2001503934A/en
Priority to CA002266673A priority patent/CA2266673C/en
Priority to EP97918870A priority patent/EP0931432A2/en
Publication of WO1998013961A2 publication Critical patent/WO1998013961A2/en
Publication of WO1998013961A3 publication Critical patent/WO1998013961A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program using multi-processor systems
    • H04Q3/54558—Redundancy, stand-by
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored program using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

An architecture for a modular communications system is disclosed. The modular communications system comprises at least one control module; a plurality of resource modules for receipt of external payload data provided to said system of for manipulation of the payload data; a plurality of resource module links, one link connecting each resource module to the control module and each resource module. The control module comprises a switch for switching payload data between the plurality of resource modules; and a bandwidth allocator comprising a bandwidth selector and a distributor each connected to the switch and to the resource module links. The bandwidth selector allows the selection of the bandwidth of payload data passed from any of the resource modules to the time switch. Similarly, the bandwidth distributor allows for the selection of the bandwidth of payload data switched through the switch and provided to any of the resouce modules from the control module. Preferably, all the resource module links are electrically isolated from each other. The architecture provides for the modular assembly of a telecommunications offering varied capacities, redundancies and services.
PCT/CA1997/000696 1996-09-27 1997-09-24 Architecture for a modular communications switching system Ceased WO1998013961A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP51508598A JP2001503934A (en) 1996-09-27 1997-09-24 Modular communication switching system configuration
CA002266673A CA2266673C (en) 1996-09-27 1997-09-24 Architecture for a modular communications switching system
EP97918870A EP0931432A2 (en) 1996-09-27 1997-09-24 Architecture for a modular communications switching system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/721,095 US6125111A (en) 1996-09-27 1996-09-27 Architecture for a modular communications switching system
US08/721,095 1996-09-27

Publications (2)

Publication Number Publication Date
WO1998013961A2 WO1998013961A2 (en) 1998-04-02
WO1998013961A3 true WO1998013961A3 (en) 1998-06-18

Family

ID=24896513

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CA1997/000696 Ceased WO1998013961A2 (en) 1996-09-27 1997-09-24 Architecture for a modular communications switching system

Country Status (5)

Country Link
US (1) US6125111A (en)
EP (1) EP0931432A2 (en)
JP (1) JP2001503934A (en)
CA (1) CA2266673C (en)
WO (1) WO1998013961A2 (en)

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US7359410B2 (en) * 2003-05-30 2008-04-15 Hubbell Incorporated Apparatus and method for increasing optical density of SONET multiplexer using integral components
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Also Published As

Publication number Publication date
EP0931432A2 (en) 1999-07-28
US6125111A (en) 2000-09-26
CA2266673A1 (en) 1998-04-02
JP2001503934A (en) 2001-03-21
WO1998013961A2 (en) 1998-04-02
CA2266673C (en) 2004-02-24

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