WO1998043148A3 - Novel multiprocessor distributed memory system and board and methods therefor - Google Patents

Novel multiprocessor distributed memory system and board and methods therefor Download PDF

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Publication number
WO1998043148A3
WO1998043148A3 PCT/US1998/005785 US9805785W WO9843148A3 WO 1998043148 A3 WO1998043148 A3 WO 1998043148A3 US 9805785 W US9805785 W US 9805785W WO 9843148 A3 WO9843148 A3 WO 9843148A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
memory
circuit board
printed circuit
processing node
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US1998/005785
Other languages
French (fr)
Other versions
WO1998043148A2 (en
Inventor
John D Acton
Michael D Derbish
Gavin G Gibson
Jack M Hardy Jr
Hugh M Humphreys
Steven P Kent
Steven E Schelong
Ricardo Yong
William B Derolf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to EP98912010A priority Critical patent/EP0970427A4/en
Publication of WO1998043148A2 publication Critical patent/WO1998043148A2/en
Publication of WO1998043148A3 publication Critical patent/WO1998043148A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17381—Two dimensional, e.g. mesh, torus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Information Transfer Systems (AREA)
  • Hardware Redundancy (AREA)

Abstract

A data processing system includes a plurality of nodes (501-504), a serial data bus (50) interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node (501). In one construction, this processing node (501) has a processor (510), a printed circuit board (500), a memory partitioned into first and second sections and a local bus (13) connecting the processor (510), a block sharable memory section of the memory, and the printed circuit board (500). The local bus (13) is used for transferring data in parallel from the processor (510) to a directly sharable memory (518) section of the memory on the printed circuit board. The printed circuit board (500) includes a sensor for sensing when data is transferred into the directly sharable memory (518), a queuing device for queuing the sensed data, a serializer (32) for serializing the queued data, a transmitter for transmitting the serialized data onto the serial data bus to the next sussessive processing node (501), a receiver for receiving serialized data from next preceding processing node (501), and a deserializer (31) for deserializing the received serialized data into parallel data.
PCT/US1998/005785 1997-03-25 1998-03-25 Novel multiprocessor distributed memory system and board and methods therefor Ceased WO1998043148A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP98912010A EP0970427A4 (en) 1997-03-25 1998-03-25 Novel multiprocessor distributed memory system and board and methods therefor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/826,805 1997-03-25
US08/826,805 US6094532A (en) 1997-03-25 1997-03-25 Multiprocessor distributed memory system and board and methods therefor

Publications (2)

Publication Number Publication Date
WO1998043148A2 WO1998043148A2 (en) 1998-10-01
WO1998043148A3 true WO1998043148A3 (en) 1998-12-30

Family

ID=25247582

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/005785 Ceased WO1998043148A2 (en) 1997-03-25 1998-03-25 Novel multiprocessor distributed memory system and board and methods therefor

Country Status (3)

Country Link
US (3) US6094532A (en)
EP (1) EP0970427A4 (en)
WO (1) WO1998043148A2 (en)

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US6442670B2 (en) * 1997-03-25 2002-08-27 Sun Microsystems, Inc. Data processing system including a shared memory resource circuit
GB9709627D0 (en) * 1997-05-13 1997-07-02 Hewlett Packard Co Multimode communications systems
US7373440B2 (en) * 1997-12-17 2008-05-13 Src Computers, Inc. Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format
US20060117274A1 (en) * 1998-08-31 2006-06-01 Tseng Ping-Sheng Behavior processor system and method
US9195784B2 (en) * 1998-08-31 2015-11-24 Cadence Design Systems, Inc. Common shared memory in a verification system
JP3976432B2 (en) * 1998-12-09 2007-09-19 エヌイーシーコンピュータテクノ株式会社 Data processing apparatus and data processing method
KR100362193B1 (en) * 1999-11-26 2002-11-23 주식회사 하이닉스반도체 Data Output Device of DDR SDRAM
US6775274B1 (en) * 2000-01-27 2004-08-10 International Business Machines Corporation Circuit and method for providing secure communication over data communication interconnects
US7333570B2 (en) 2000-03-14 2008-02-19 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US6661355B2 (en) * 2000-12-27 2003-12-09 Apple Computer, Inc. Methods and apparatus for constant-weight encoding & decoding
US20020176138A1 (en) * 2001-05-21 2002-11-28 Schlanger Steven Eric Infrared encoder/decoder having hardware and software data rate selection
US6892337B1 (en) * 2001-08-22 2005-05-10 Cypress Semiconductor Corp. Circuit and method for testing physical layer functions of a communication network
US20030101280A1 (en) * 2001-11-27 2003-05-29 Chiu Kenneth Y. Fast jump address algorithm
WO2003060733A1 (en) * 2002-01-15 2003-07-24 Nano Storage Pte Ltd Bus architecture and communication protocol
DE10231424B4 (en) * 2002-07-11 2006-11-09 Pro Design Electronic & Cad-Layout Gmbh Device and method for data communication
US7206831B1 (en) * 2002-08-26 2007-04-17 Finisar Corporation On card programmable filtering and searching for captured network data
US7636804B2 (en) * 2003-04-28 2009-12-22 Quantum Corporation Data storage and protection apparatus and methods of data storage and protection
US7421559B1 (en) 2003-12-18 2008-09-02 Cypress Semiconductor Corporation Apparatus and method for a synchronous multi-port memory
US7660993B2 (en) * 2004-03-22 2010-02-09 Microsoft Corporation Cryptographic puzzle cancellation service for deterring bulk electronic mail messages
US20060221427A1 (en) * 2005-03-31 2006-10-05 Wu Xin M Impedance matching circuit for optical transmitter
US20070009267A1 (en) * 2005-06-22 2007-01-11 Crews Darren S Driving a laser using an electrical link driver
US7962698B1 (en) 2005-10-03 2011-06-14 Cypress Semiconductor Corporation Deterministic collision detection
US8874477B2 (en) 2005-10-04 2014-10-28 Steven Mark Hoffberg Multifactorial optimization system and method
US7945816B1 (en) * 2005-11-30 2011-05-17 At&T Intellectual Property Ii, L.P. Comprehensive end-to-end storage area network (SAN) application transport service
US7532135B1 (en) * 2007-11-26 2009-05-12 Broadcom Corporation Dual purpose serializer/de-serializer for point-to-point and point-to-multipoint communication
US7554466B1 (en) 2007-12-05 2009-06-30 Broadcom Corporation Multi-speed burst mode serializer/de-serializer
CN107196864A (en) * 2014-08-12 2017-09-22 烽火通信科技股份有限公司 A kind of multichannel FC business long distance transmitters based on FPGA
US11561840B2 (en) 2020-01-30 2023-01-24 Alibaba Group Holding Limited Efficient inter-chip interconnect topology for distributed parallel deep learning
CN115378504A (en) * 2022-07-27 2022-11-22 中国船舶重工集团公司第七二四研究所 PCIE bus memory polling-based multi-path optical fiber data transmission method

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US5327570A (en) * 1991-07-22 1994-07-05 International Business Machines Corporation Multiprocessor system having local write cache within each data processor node
US5617537A (en) * 1993-10-05 1997-04-01 Nippon Telegraph And Telephone Corporation Message passing system for distributed shared memory multiprocessor system and message passing method using the same

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US4633394A (en) * 1984-04-24 1986-12-30 International Business Machines Corp. Distributed arbitration for multiple processors
US5297255A (en) 1987-07-28 1994-03-22 Hitachi, Ltd. Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism
US5710932A (en) * 1987-07-28 1998-01-20 Hitachi, Ltd. Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism
US5131061A (en) 1991-02-13 1992-07-14 International Business Machines Corp. Modular active fiber optic coupler system

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US5327570A (en) * 1991-07-22 1994-07-05 International Business Machines Corporation Multiprocessor system having local write cache within each data processor node
US5617537A (en) * 1993-10-05 1997-04-01 Nippon Telegraph And Telephone Corporation Message passing system for distributed shared memory multiprocessor system and message passing method using the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0970427A4 *

Also Published As

Publication number Publication date
EP0970427A4 (en) 2000-06-28
US6256722B1 (en) 2001-07-03
WO1998043148A2 (en) 1998-10-01
US6094532A (en) 2000-07-25
US6134647A (en) 2000-10-17
EP0970427A2 (en) 2000-01-12

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