WO1999011027A3 - Common architecture for a cross-connecting processor - Google Patents

Common architecture for a cross-connecting processor Download PDF

Info

Publication number
WO1999011027A3
WO1999011027A3 PCT/FI1998/000660 FI9800660W WO9911027A3 WO 1999011027 A3 WO1999011027 A3 WO 1999011027A3 FI 9800660 W FI9800660 W FI 9800660W WO 9911027 A3 WO9911027 A3 WO 9911027A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
cross
data
connecting processor
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FI1998/000660
Other languages
Finnish (fi)
French (fr)
Other versions
WO1999011027A2 (en
Inventor
Jarmo Ylae-Mella
Esa Metsaelae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to AU89808/98A priority Critical patent/AU8980898A/en
Priority to DE69835156T priority patent/DE69835156T2/en
Priority to EP98941437A priority patent/EP1010299B1/en
Publication of WO1999011027A2 publication Critical patent/WO1999011027A2/en
Publication of WO1999011027A3 publication Critical patent/WO1999011027A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

A cross-connecting processor is arranged so as to read instructions according to an instruction architecture from a control memory and, controlled by said instructions, to connect data stored in a data memory to transmitter interfaces. Each instruction comprises at least a first part indicating the type of the instruction and a second part specifying the source of the data to be connected. Each instruction comprises at least one and at most M instruction words, where M is the number of bits in the biggest possible data unit that can be cross-connected at a time. The space reserved in the control memory by each individual instruction is N times the size of the instruction word, where N is the number of bits in the data source the connection of which is controlled by the instruction in question.
PCT/FI1998/000660 1997-08-26 1998-08-26 Common architecture for a cross-connecting processor Ceased WO1999011027A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU89808/98A AU8980898A (en) 1997-08-26 1998-08-26 Common architecture for a cross-connecting processor
DE69835156T DE69835156T2 (en) 1997-08-26 1998-08-26 COMMUNITY ARCHITECTURE FOR A CROSS-LINKING PROCESSOR
EP98941437A EP1010299B1 (en) 1997-08-26 1998-08-26 Common architecture for a cross-connecting processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI973507A FI103449B1 (en) 1997-08-26 1997-08-26 The cross architecture processor architecture
FI973507 1997-08-26

Publications (2)

Publication Number Publication Date
WO1999011027A2 WO1999011027A2 (en) 1999-03-04
WO1999011027A3 true WO1999011027A3 (en) 1999-05-20

Family

ID=8549428

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FI1998/000660 Ceased WO1999011027A2 (en) 1997-08-26 1998-08-26 Common architecture for a cross-connecting processor

Country Status (5)

Country Link
EP (1) EP1010299B1 (en)
AU (1) AU8980898A (en)
DE (1) DE69835156T2 (en)
FI (1) FI103449B1 (en)
WO (1) WO1999011027A2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0150940A2 (en) * 1984-01-26 1985-08-07 Northern Telecom Limited Data Format converter
US4862480A (en) * 1987-04-09 1989-08-29 Integrated Network Corporation Digital data service system
WO1993022859A1 (en) * 1992-04-24 1993-11-11 Nokia Telecommunications Oy Method and device for configuration of a time-space-time cross-connection at occasions when the need of cross-connexion changes and use thereof
WO1994015298A1 (en) * 1992-12-29 1994-07-07 Nokia Telecommunications Oy Disturbance-free connection to time-divided bus
EP0622919A1 (en) * 1993-04-30 1994-11-02 Alcatel N.V. Interface device for format conversion
WO1994028644A1 (en) * 1993-05-25 1994-12-08 Nokia Telecommunications Oy Base station in a cellular radio system and a cellular radio system
US5696788A (en) * 1995-12-26 1997-12-09 Electronics And Telecommunications Research Institute Circuit for searching fault location in a device having a plurality of application specific integrated circuits

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0150940A2 (en) * 1984-01-26 1985-08-07 Northern Telecom Limited Data Format converter
US4862480A (en) * 1987-04-09 1989-08-29 Integrated Network Corporation Digital data service system
WO1993022859A1 (en) * 1992-04-24 1993-11-11 Nokia Telecommunications Oy Method and device for configuration of a time-space-time cross-connection at occasions when the need of cross-connexion changes and use thereof
WO1994015298A1 (en) * 1992-12-29 1994-07-07 Nokia Telecommunications Oy Disturbance-free connection to time-divided bus
EP0622919A1 (en) * 1993-04-30 1994-11-02 Alcatel N.V. Interface device for format conversion
WO1994028644A1 (en) * 1993-05-25 1994-12-08 Nokia Telecommunications Oy Base station in a cellular radio system and a cellular radio system
US5696788A (en) * 1995-12-26 1997-12-09 Electronics And Telecommunications Research Institute Circuit for searching fault location in a device having a plurality of application specific integrated circuits

Also Published As

Publication number Publication date
FI973507A0 (en) 1997-08-26
AU8980898A (en) 1999-03-16
FI973507A7 (en) 1999-02-27
DE69835156D1 (en) 2006-08-17
FI103449B (en) 1999-06-30
DE69835156T2 (en) 2007-07-05
WO1999011027A2 (en) 1999-03-04
EP1010299A2 (en) 2000-06-21
EP1010299B1 (en) 2006-07-05
FI103449B1 (en) 1999-06-30

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