WO2000013227A3 - Method of manufacturing a semiconductor device with a bipolar transistor - Google Patents

Method of manufacturing a semiconductor device with a bipolar transistor Download PDF

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Publication number
WO2000013227A3
WO2000013227A3 PCT/EP1999/005600 EP9905600W WO0013227A3 WO 2000013227 A3 WO2000013227 A3 WO 2000013227A3 EP 9905600 W EP9905600 W EP 9905600W WO 0013227 A3 WO0013227 A3 WO 0013227A3
Authority
WO
WIPO (PCT)
Prior art keywords
base
semiconductor body
layer
monocrystalline
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP1999/005600
Other languages
French (fr)
Other versions
WO2000013227A2 (en
Inventor
Catharina H H Emons
Doede Terpstra
Cornelis E Timmering
Boer Wiebe B De
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP99941512A priority Critical patent/EP1048065A2/en
Priority to JP2000568119A priority patent/JP2002524853A/en
Publication of WO2000013227A2 publication Critical patent/WO2000013227A2/en
Publication of WO2000013227A3 publication Critical patent/WO2000013227A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/12—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a gaseous phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1404—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

The invention relates to a method of manufacturing a discrete or integrated bipolar transistor comprising a base (1A), an emitter (2) and a collector (3). The base (1A) and a connecting region (1B) of the base (1A) are formed by providing a semiconductor body (10) with a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body which forms the collector (3). Outside said base, the layer (1) borders on a non-monocrystalline part (4) of the semiconductor body (10) and forms a non-monocrystalline connecting region (1B) of the base (1A). By means of a mask (5), the doping concentration of the layer (1) outside the mask (5) is selectively increased, resulting in a highly conducting connection region (1B) and a very fast transistor. In the known method, an ion implantation is used for this purpose. In a method in accordance with the invention, this is achieved by bringing the semiconductor body (10) into contact with a gaseous substance (40) comprising a doping element, and heating the semiconductor body (10) in such a manner that the doping elements penetrate into the semiconducting layer (1). The supply of the gaseous substance (40), for example diborane, preferably takes place at a temperature between 800 and 950 °C for one to several minutes. Subsequently, a slightly longer diffusion step can be carried out, for example, at 850 °C.
PCT/EP1999/005600 1998-08-31 1999-08-03 Method of manufacturing a semiconductor device with a bipolar transistor Ceased WO2000013227A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP99941512A EP1048065A2 (en) 1998-08-31 1999-08-03 Method of manufacturing a semiconductor device with a bipolar transistor
JP2000568119A JP2002524853A (en) 1998-08-31 1999-08-03 Method for manufacturing semiconductor device having bipolar transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98202894.6 1998-08-31
EP98202894 1998-08-31

Publications (2)

Publication Number Publication Date
WO2000013227A2 WO2000013227A2 (en) 2000-03-09
WO2000013227A3 true WO2000013227A3 (en) 2000-06-02

Family

ID=8234073

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1999/005600 Ceased WO2000013227A2 (en) 1998-08-31 1999-08-03 Method of manufacturing a semiconductor device with a bipolar transistor

Country Status (4)

Country Link
US (1) US6100152A (en)
EP (1) EP1048065A2 (en)
JP (1) JP2002524853A (en)
WO (1) WO2000013227A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547615B2 (en) 2001-02-12 2009-06-16 Asm America, Inc. Deposition over mixed substrates using trisilane
US8921205B2 (en) 2002-08-14 2014-12-30 Asm America, Inc. Deposition of amorphous silicon-containing films

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2778022B1 (en) * 1998-04-22 2001-07-13 France Telecom VERTICAL BIBOLAR TRANSISTOR, ESPECIALLY BASED ON SIGNAL HETEROJUNCTION, AND MANUFACTURING METHOD
EP1082758A2 (en) * 1998-11-13 2001-03-14 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device comprising a bipolar transistor
US6724066B2 (en) * 2001-04-30 2004-04-20 Texas Instruments Incorporated High breakdown voltage transistor and method
DE10220578A1 (en) * 2002-05-08 2003-11-27 Infineon Technologies Ag Bipolar transistor used as a self-adjusting bipolar transistor comprises an emitter region electrically contacted via an emitter electrode, a base region electrically contacted
KR100486265B1 (en) * 2002-09-19 2005-05-03 삼성전자주식회사 Bipolar transistor and method of manufacturing the same
US6919253B2 (en) * 2003-02-07 2005-07-19 Matsushita Electric Industrial Co., Ltd. Method of forming a semiconductor device including simultaneously forming a single crystalline epitaxial layer and a polycrystalline or amorphous layer
US7566919B2 (en) * 2003-12-12 2009-07-28 Nxp B.V. Method to reduce seedlayer topography in BICMOS process
US6965133B2 (en) * 2004-03-13 2005-11-15 International Business Machines Corporation Method of base formation in a BiCMOS process
US7118995B2 (en) * 2004-05-19 2006-10-10 International Business Machines Corporation Yield improvement in silicon-germanium epitaxial growth
DE102004053394B4 (en) * 2004-11-05 2010-08-19 Atmel Automotive Gmbh Semiconductor arrangement and method for producing a semiconductor device
AU2008332277B2 (en) 2007-12-05 2012-10-25 Toyota Jidosha Kabushiki Kaisha Genes that increase plant oil and method for using the same
CN101599435B (en) * 2009-07-24 2012-05-23 上海宏力半导体制造有限公司 Method for doping single-layer polycrystalline silicon HBT extrinsic base region

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3600651A (en) * 1969-12-08 1971-08-17 Fairchild Camera Instr Co Bipolar and field-effect transistor using polycrystalline epitaxial deposited silicon
US5117271A (en) * 1990-12-07 1992-05-26 International Business Machines Corporation Low capacitance bipolar junction transistor and fabrication process therfor
US5656514A (en) * 1992-07-13 1997-08-12 International Business Machines Corporation Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile
EP0795899A1 (en) * 1996-03-14 1997-09-17 Daimler-Benz Aktiengesellschaft Method for fabricating a heterojunction bipolar transistor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61164262A (en) * 1985-01-17 1986-07-24 Toshiba Corp Semiconductor device
US5073810A (en) * 1989-11-07 1991-12-17 Hitachi, Ltd. Semiconductor integrated circuit device and manufacturing method thereof
JPH05226352A (en) * 1992-02-17 1993-09-03 Mitsubishi Electric Corp Semiconductor device and its manufacture
US5321301A (en) * 1992-04-08 1994-06-14 Nec Corporation Semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3600651A (en) * 1969-12-08 1971-08-17 Fairchild Camera Instr Co Bipolar and field-effect transistor using polycrystalline epitaxial deposited silicon
US5117271A (en) * 1990-12-07 1992-05-26 International Business Machines Corporation Low capacitance bipolar junction transistor and fabrication process therfor
US5656514A (en) * 1992-07-13 1997-08-12 International Business Machines Corporation Method for making heterojunction bipolar transistor with self-aligned retrograde emitter profile
EP0795899A1 (en) * 1996-03-14 1997-09-17 Daimler-Benz Aktiengesellschaft Method for fabricating a heterojunction bipolar transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
YUKIHIRO KIYOTA ET AL: "ULTRA-THIN-BASE SI BIPOLAR TRANSISTOR USING RAPID VAPOR-PHASE DIRECT DOPING (RVD)", IEEE TRANSACTIONS ON ELECTRON DEVICES,US,IEEE INC. NEW YORK, vol. 39, no. 9, 1 September 1992 (1992-09-01), pages 2077 - 2081, XP000293951, ISSN: 0018-9383 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7547615B2 (en) 2001-02-12 2009-06-16 Asm America, Inc. Deposition over mixed substrates using trisilane
US8921205B2 (en) 2002-08-14 2014-12-30 Asm America, Inc. Deposition of amorphous silicon-containing films

Also Published As

Publication number Publication date
US6100152A (en) 2000-08-08
JP2002524853A (en) 2002-08-06
WO2000013227A2 (en) 2000-03-09
EP1048065A2 (en) 2000-11-02

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