WO2000019509A2 - Method of manufacturing a semiconductor device with a field effect transistor - Google Patents

Method of manufacturing a semiconductor device with a field effect transistor Download PDF

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Publication number
WO2000019509A2
WO2000019509A2 PCT/EP1999/006699 EP9906699W WO0019509A2 WO 2000019509 A2 WO2000019509 A2 WO 2000019509A2 EP 9906699 W EP9906699 W EP 9906699W WO 0019509 A2 WO0019509 A2 WO 0019509A2
Authority
WO
WIPO (PCT)
Prior art keywords
layer
poly
gate
sub
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP1999/006699
Other languages
French (fr)
Other versions
WO2000019509A3 (en
Inventor
Jurriaan Schmitz
Pierre H. Woerlee
Andreas H. Montree
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to CA002311967A priority Critical patent/CA2311967A1/en
Priority to JP2000572918A priority patent/JP2002526920A/en
Priority to EP99947310A priority patent/EP1048068A2/en
Priority to KR1020007005689A priority patent/KR100574347B1/en
Publication of WO2000019509A2 publication Critical patent/WO2000019509A2/en
Publication of WO2000019509A3 publication Critical patent/WO2000019509A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01316—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum

Definitions

  • the invention relates to a method of manufacturing a semiconductor device with a field effect transistor, in which method a semiconductor body is provided, at a surface, with a source region and a drain region, while using a doping mask containing a polycrystalline silicon (hereinafter referred to as poly), and in which method subsequently a dielectric layer is provided which is subjected to a material-removing treatment, such as etching or polishing, to remove a part of its thickness, so that the poly-containing doping mask is exposed again, whereafter said poly-containing doping mask is removed by means of a selective etch step and, subsequently, a conductive layer is provided in the resultant recess in the dielectric layer, which conductive layer constitutes the gate of the transistor.
  • a material-removing treatment such as etching or polishing
  • an oxide layer which serves as the dielectric layer is deposited, whereafter the thickness of the dielectric layer is reduced down to the poly by means of chemico-mechanical polishing (hereinafter referred to as CMP).
  • CMP chemico-mechanical polishing
  • the poly of the dummy gate is removed by selective etching.
  • the resultant recess in the oxide layer is filled by a metal gate of Al or W.
  • a method of the type described in the opening paragraph is characterized in accordance with the invention in that the poly- containing doping mask is provided in the form of a double layer comprising a first sub-layer of polysilicon and a second sub-layer, which is provided on the first sub-layer and consists of a material having a greater resistance to the material-removing treatment than polysilicon, and which material can be selectively etched relative to said dielectric layer.
  • the invention is based, inter alia, on the recognition that poly has a fairly low resistance to CMP, which is the reason why the point in time at which CMP is interrupted is so critical.
  • An important embodiment of a method in accordance with the invention is characterized in that the dielectric layer is formed by silicon oxide and the second sub-layer is formed by a layer containing silicon nitride.
  • Figs. 1 through 8 are sectional views of a semiconductor device at various stages in the manufacture of the device by means of a method in accordance with the invention.
  • the device comprises a semiconductor body which, in this case, is made of silicon but which may alternatively be made of another suitable semiconductor material, which semiconductor body has a surface region 1 which borders on a surface and which is of a first conductivity type, in this example the p-type (Fig. 1).
  • a field oxide 2 In the surface region 1, an active region is defined in a customary manner by a field oxide 2.
  • the active region is covered with a thin layer 3 of, for example, silicon oxide which, dependent upon subsequent process steps, may or may not be used as a gate dielectric.
  • a double layer is deposited, which comprises a layer of polycrystalline or amorphous Si or Ge x Si 1-x and, on said poly layer, a second layer, for example a nitride layer such as silicon nitride.
  • the dummy gate 4 covered with the nitride layer 5; is formed from this double layer, whereafter the source/drain extensions 6 are provided by a relatively slight implantation of P or As ions.
  • the sides of the dummy gate 4 are provided, in a manner which is known per se, with spacers 7, for example by deposition and anisotropic backetching of a silicon oxide layer.
  • a relatively thick dielectric layer 10 is deposited from the vapor phase, in this example silicon oxide; of course, also other suitable electrically insulating materials can be used.
  • CMP chemico-mechanical polishing
  • silicon oxide buffered in a solution of ammonium hydroxide.
  • the material-removing treatment is ended when the nitride layer 5 has been reached. Since the poly layer 4 remains covered with the nitride 5 during the CMP step, said poly is not attacked, so that the reproducibility of the process is improved substantially.
  • the silicon nitride layer 5 is selectively removed relative to the silicon oxide, for example by etching in phosphoric acid.
  • the poly of the layer 4 is selectively removed, for example by plasma etching using HBr+Cl 2 , see Fig. 6.
  • a structure which comprises a relatively thick oxide layer 10 with an aperture or recessed portion 13, which is accurately aligned relative to the source and drain regions of the transistor.
  • the oxide layer 3 is removed, whereafter a new gate dielectric 11 is formed by thermal oxidation.
  • a metal layer 12 is applied, in a manner which is known per se, which completely fills the recessed portion 13, see Fig. 7.
  • the metal layer 12 may be made, for example, of Al or W or of another suitable metal or combination of metals.
  • the layer 12 is patterned to obtain the gate 14 of the transistor.
  • Said patterning can be carried out by means of a mask, the metal of the gate extending over the oxide layer 10 beyond the recessed portion 13.
  • no mask is used to remove so much of the metal layer 12 that a gate 14 is formed, as shown in Fig. 8, which is entirely recessed in the oxide layer 10, for example by a CMP treatment.

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

In the known replacement gate process, the relatively high-ohmic poly gate is replaced by a low-ohmic metal gate by depositing a thick oxide layer and subsequently planarizing this layer by CMP until the gate is reached, which gate can be selectively removed and replaced by a metal gate. The process is simplified considerably by providing the gate structure as a stack of a dummy poly gate (4) and a nitride layer (5) on top of the poly gate. When, during the CMP, the nitride layer is reached, the CMP is stopped, thereby precluding an attack on the poly. The nitride and the poly are selectively removed relative to the oxide layer (10).

Description

Method of manufacturing a semiconductor device with a field effect transistor
Description
The invention relates to a method of manufacturing a semiconductor device with a field effect transistor, in which method a semiconductor body is provided, at a surface, with a source region and a drain region, while using a doping mask containing a polycrystalline silicon (hereinafter referred to as poly), and in which method subsequently a dielectric layer is provided which is subjected to a material-removing treatment, such as etching or polishing, to remove a part of its thickness, so that the poly-containing doping mask is exposed again, whereafter said poly-containing doping mask is removed by means of a selective etch step and, subsequently, a conductive layer is provided in the resultant recess in the dielectric layer, which conductive layer constitutes the gate of the transistor. Such a method is known, inter alia, from the article "Sub-100 nm gate length metal gate NMOS transistors fabricated by a replacement gate process" by A. Chatterjee et. al., LEDM 97, pp. 821/824. The "replacement gate process" enables MOS transistors with a metal gate to be manufactured in a self-recording manner, instead of the customary polysilicon gates which have a much higher resistance. In the known process, a dummy gate of polysilicon is formed in the same manner as the poly gate in standard CMOS processes. After the formation of the source and drain regions, an oxide layer which serves as the dielectric layer is deposited, whereafter the thickness of the dielectric layer is reduced down to the poly by means of chemico-mechanical polishing (hereinafter referred to as CMP). Subsequently, the poly of the dummy gate is removed by selective etching. The resultant recess in the oxide layer is filled by a metal gate of Al or W.
In practice it has been found that the reproducibility of this process is limited. In particular the point in time at which the chemico-mechanical polishing operation of the oxide layer is interrupted proved to be very critical. If the CMP is stopped too early, the remaining oxide makes it very difficult to remove the poly. If the CMP process is continued too long, then the height of the gate to be formed eventually proves to be ill-defined.
It is an object of the invention to provide, inter alia, a "replacement gate" process having a better reproducibility. To achieve this, a method of the type described in the opening paragraph is characterized in accordance with the invention in that the poly- containing doping mask is provided in the form of a double layer comprising a first sub-layer of polysilicon and a second sub-layer, which is provided on the first sub-layer and consists of a material having a greater resistance to the material-removing treatment than polysilicon, and which material can be selectively etched relative to said dielectric layer. The invention is based, inter alia, on the recognition that poly has a fairly low resistance to CMP, which is the reason why the point in time at which CMP is interrupted is so critical. By providing, in accordance with the invention, above said poly a layer of another material having a greater etch resistance than poly, the etch rate is reduced substantially when the second sub-layer is reached.
An important embodiment of a method in accordance with the invention is characterized in that the dielectric layer is formed by silicon oxide and the second sub-layer is formed by a layer containing silicon nitride.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
In the drawings:
Figs. 1 through 8 are sectional views of a semiconductor device at various stages in the manufacture of the device by means of a method in accordance with the invention.
Although the invention will hereinafter be explained by means of a single MOS transistor, it will be obvious to those skilled in the art that the process described herein can also be used to manufacture CMOS or BICMOS integrated circuits which are known per se. The device comprises a semiconductor body which, in this case, is made of silicon but which may alternatively be made of another suitable semiconductor material, which semiconductor body has a surface region 1 which borders on a surface and which is of a first conductivity type, in this example the p-type (Fig. 1). In the surface region 1, an active region is defined in a customary manner by a field oxide 2. The active region is covered with a thin layer 3 of, for example, silicon oxide which, dependent upon subsequent process steps, may or may not be used as a gate dielectric. After the formation of the gate oxide 3, a double layer is deposited, which comprises a layer of polycrystalline or amorphous Si or GexSi1-x and, on said poly layer, a second layer, for example a nitride layer such as silicon nitride. In a customary, photolithographic manner, the dummy gate 4, covered with the nitride layer 5; is formed from this double layer, whereafter the source/drain extensions 6 are provided by a relatively slight implantation of P or As ions. Subsequently, the sides of the dummy gate 4 are provided, in a manner which is known per se, with spacers 7, for example by deposition and anisotropic backetching of a silicon oxide layer. Next, the source and drain regions 8 and 9, respectively, are formed, which regions are heavily doped as a result of said implantation with P or S ions. In a next stage, shown in Fig. 3, a relatively thick dielectric layer 10 is deposited from the vapor phase, in this example silicon oxide; of course, also other suitable electrically insulating materials can be used.
Subsequently, a part of the thickness of the layer 10 is removed by means of chemico-mechanical polishing (CMP). For this purpose use can be made, for example, of a slurry of silicon oxide buffered in a solution of ammonium hydroxide. The material-removing treatment is ended when the nitride layer 5 has been reached. Since the poly layer 4 remains covered with the nitride 5 during the CMP step, said poly is not attacked, so that the reproducibility of the process is improved substantially. In a next step, shown in Fig. 5, the silicon nitride layer 5 is selectively removed relative to the silicon oxide, for example by etching in phosphoric acid. Next, the poly of the layer 4 is selectively removed, for example by plasma etching using HBr+Cl2, see Fig. 6. At this stage of the process, a structure has been obtained which comprises a relatively thick oxide layer 10 with an aperture or recessed portion 13, which is accurately aligned relative to the source and drain regions of the transistor. Preferably, the oxide layer 3 is removed, whereafter a new gate dielectric 11 is formed by thermal oxidation. Subsequently, a metal layer 12 is applied, in a manner which is known per se, which completely fills the recessed portion 13, see Fig. 7. The metal layer 12 may be made, for example, of Al or W or of another suitable metal or combination of metals. In a subsequent step, the layer 12 is patterned to obtain the gate 14 of the transistor. Said patterning can be carried out by means of a mask, the metal of the gate extending over the oxide layer 10 beyond the recessed portion 13. Preferably, however, no mask is used to remove so much of the metal layer 12 that a gate 14 is formed, as shown in Fig. 8, which is entirely recessed in the oxide layer 10, for example by a CMP treatment.
It will be obvious that the invention is not limited to the example described herein, and that within the scope of the invention many variations are possible to those skilled in the art. For example, instead of silicon nitride for the layer 5, also other suitable materials or combinations of materials may be used, such as silicon oxynitride.

Claims

CLAIMS:
1. A method of manufacturing a semiconductor device with a field effect transistor, in which method a semiconductor body is provided, at a surface, with a source region and a drain region, while using a doping mask containing a polycrystalline silicon (hereinafter referred to as poly), and in which method subsequently a dielectric layer is provided which is subjected to a material-removing treatment, such as etching or polishing, to remove a part of its thickness, so that the poly-containing doping mask is exposed again, whereafter said poly-containing doping mask is removed by means of a selective etch step and, subsequently, a conductive layer is provided in the resultant recess in the dielectric layer, which conductive layer constitutes the gate of the transistor, characterized in that the poly- containing doping mask is provided in the form of a double layer comprising a first sub-layer of polysilicon and a second sub-layer, which is provided on the first sub-layer and consists of a material having a greater resistance to the material-removing treatment than polysilicon, and which material can be selectively etched relative to said dielectric layer.
2. A method as claimed in claim 1 , characterized in that the dielectric layer is formed by silicon oxide and the second sub-layer is formed by a layer containing silicon nitride.
PCT/EP1999/006699 1998-09-28 1999-09-09 Method of manufacturing a semiconductor device with a field effect transistor Ceased WO2000019509A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CA002311967A CA2311967A1 (en) 1998-09-28 1999-09-09 Method of manufacturing a semiconductor device with a field effect transistor
JP2000572918A JP2002526920A (en) 1998-09-28 1999-09-09 Method of manufacturing semiconductor device having field effect transistor
EP99947310A EP1048068A2 (en) 1998-09-28 1999-09-09 Method of manufacturing a semiconductor device with a field effect transistor
KR1020007005689A KR100574347B1 (en) 1998-09-28 1999-09-09 Method for manufacturing semiconductor device having field effect transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98203246 1998-09-28
EP98203246.8 1998-09-28

Publications (2)

Publication Number Publication Date
WO2000019509A2 true WO2000019509A2 (en) 2000-04-06
WO2000019509A3 WO2000019509A3 (en) 2000-08-03

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US (1) US6177303B1 (en)
EP (1) EP1048068A2 (en)
JP (1) JP2002526920A (en)
KR (1) KR100574347B1 (en)
CN (1) CN1296639A (en)
CA (1) CA2311967A1 (en)
TW (1) TW429447B (en)
WO (1) WO2000019509A2 (en)

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KR100574347B1 (en) 2006-04-27
EP1048068A2 (en) 2000-11-02
CN1296639A (en) 2001-05-23
CA2311967A1 (en) 2000-04-06
JP2002526920A (en) 2002-08-20
WO2000019509A3 (en) 2000-08-03
TW429447B (en) 2001-04-11
US6177303B1 (en) 2001-01-23
KR20010032448A (en) 2001-04-25

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