WO2000033385A1 - Mos-feldeffekttransistor mit hilfselektrode - Google Patents
Mos-feldeffekttransistor mit hilfselektrode Download PDFInfo
- Publication number
- WO2000033385A1 WO2000033385A1 PCT/DE1999/003542 DE9903542W WO0033385A1 WO 2000033385 A1 WO2000033385 A1 WO 2000033385A1 DE 9903542 W DE9903542 W DE 9903542W WO 0033385 A1 WO0033385 A1 WO 0033385A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- effect transistor
- mos field
- field effect
- transistor according
- auxiliary electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
Definitions
- a semiconductor body of one conduction type having a first and a second main surface, at least one first semiconductor zone of the other conduction type of opposite conduction type is embedded,
- a gate electrode at least in the area above the first semiconductor zone between the second semiconductor zone and the semiconductor body
- first electrode contacting the semiconductor body on the second main surface and a second electrode contacting at least the second semiconductor zone.
- This known MOSFET consists of a semiconductor body 1 with an n + -lecting dram contact zone 2, alternating n-conducting and p-conducting semiconductor zones 3 and 4, which are separated from one another by an insulating layer 5 made of, for example, silicon dioxide, p- conductive semiconductor zones ("body" zones) 6 and n-type semiconductor zones 7, which m zones 6 are embedded.
- Silicon is conventionally used for the semiconductor body 1, although other materials can also be used if necessary.
- the specified line types can also be reversed if necessary.
- Gate electrodes 9 made of doped polycrystalline silicon are embedded in an insulating layer 8 made of, for example, silicon dioxide or silicon nitride and provided with a connection G.
- n + -le ⁇ ten- semiconductor layer 2 which is provided with a drain terminal D, there is a drain voltage + U D.
- zones 3 and 4 are mutually cleared out of charge carriers. If these zones 3, 4, which are columnar between the two main surfaces of the semiconductor body 1, the total amount of the n-doping and the p-doping is approximately the same or so small that these zones 3, 4 are completely depleted of charge carriers, Before a breakdown occurs, such a MOSFET can block high voltages and still a low one
- auxiliary electrode provided with an insulating layer, which extends in the direction between the first and the second main surface of the semiconductor body and electrically with the first semiconductor zone connected is.
- the auxiliary electrode is preferably located directly below the first semiconductor zone.
- auxiliary electrodes of this type can be provided below each first semiconductor zone. These auxiliary electrodes can optionally be designed in a "pencil-like" manner.
- the auxiliary electrodes can extend up to a highly doped layer of one conductivity type in the region of the second main surface, that is to say up to the proximity of a dram contact zone.
- the auxiliary electrodes can only extend as far as a weakly doped layer of one conductivity type, which is provided between the semiconductor body and a heavily doped semiconductor layer of one conductivity type contacted with the first electrode.
- the auxiliary electrode itself preferably consists of highly doped polycrystalline silicon, while silicon dioxide is not preferably used for the insulating material.
- the depth of the auxiliary electrodes can be, for example, between 5 and 40 ⁇ m, while their width can be on the order of 1 to 5 ⁇ m.
- the thickness of the insulating layer on the polycrystalline silicon of the auxiliary electrode can be between 0.1 and 1 ⁇ m, this thickness increasing in the direction of the second main surface or towards the center of the auxiliary electrodes between the two main surfaces.
- the MOSFET according to the invention can be produced in a particularly simple manner: trenches are formed in the n-type semiconductor body, for example, by etching. The walls and floors of these trenches are provided with an insulating layer, which can be done by oxidation, so that a silicon dioxide layer is formed as an insulating layer in the semiconductor body consisting of silicon. The trenches are then filled with n + or p " -conducting polycrystalline silicon, which poses no problems.
- a p + doping is preferred for the polycrystalline silicon of the auxiliary electrode: if there is a hole in the insulating layer, a pn junction is created after p-diffusion through the hole in the n-type semiconductor body. In the case of n "doping for the polycrystalline silicon of the auxiliary electrode, on the other hand, such a hole would cause a short circuit to the n-type semiconductor body.
- auxiliary electrodes themselves can be columnar, lattice or strip-shaped or have other designs.
- the n-type semiconductor zones can also be doped the higher the closer the auxiliary electrodes are to one another. However, it must be taken into account here that, in the case of auxiliary electrodes running parallel to one another, the lateral surface charge of the n-conducting semiconductor zones is twice the throughput. fractional dopant quantity must not exceed ⁇ th.
- n + or p + doping in the polycrystalline silicon of the auxiliary electrodes need not be homogeneous. Rather, fluctuations in the doping concentration are permissible without further notice.
- the depth of the auxiliary electrodes or the trench is also not critical: they can reach up to a heavily doped dram contact zone, but do not need to do this.
- n-type semiconductor body instead of an n-type semiconductor body, for example, layers with different doping can also be provided for it.
- FIG. 1 shows a section through a MOSFET according to a first exemplary embodiment of the invention
- FIG. 2 shows a section through a MOSFET according to a second exemplary embodiment of the invention
- FIG. 3 shows a section through a MOSFET according to a third exemplary embodiment of the invention.
- FIG. 4 shows an exemplary embodiment of the MOSFET according to the invention.
- no p-type zones 4 which are surrounded by an insulating layer 5, are provided here.
- auxiliary electrodes 11 are provided in the MOSFET of the exemplary embodiment of FIG. 1, each of which consists of n + or p + -doped polycrystalline silicon 12 and are surrounded by the insulating layer 5.
- the polycrystalline silicon another correspondingly conductive material can optionally be used.
- the insulating layer 5 can also consist of materials other than silicon dioxide, for example silicon nitride, or else of different insulating materials, such as silicon dioxide or silicon nitride.
- auxiliary electrodes have a similar effect to the p-type zones 4 in the conventional MOSFET of FIG. 4: when the drain voltage + U D is applied to the drain terminal D, the n-type zones 3 are cleared of charge carriers. A greater field strength of the electric field occurs on the insulating layer 5 than in the MOSFET with the conventional structure of FIG. 4. However, this has no effect on the intended removal of load carriers.
- trenches 13 m need the semiconductor body 1 approximately up to the layer 2 with a width of approximately 1 to 5 ⁇ m and a depth of approximately 5 to 40 ⁇ m to be etched, the walls of which are then covered by oxidation with the insulating layer 5 made of silicon dioxide and a layer thickness of 0.1 to 1 ⁇ m.
- the thickness of the insulating layer 5 does not play a special role here: it can rather rise in the trench 13 from top to bottom or to the center hm.
- the trenches are then filled with the polycrystalline silicon 12, which can be p + or n + doped. Ap + doping for the auxiliary electrodes 11 is preferred, however, since it gives a greater yield with regard to holes which may be present in the insulating layer 5, as has already been explained above.
- auxiliary electrodes 11 need not correspond to the arrangement of the individual semiconductor cells. Rather, the auxiliary electrodes 11 can be provided in the form of columns, grids or strips or of any other design.
- the n-type zones 3 are preferably doped the higher the closer the auxiliary electrodes 11 are to each other. It is only essential that, in the case of auxiliary electrodes 11 running parallel to one another, the lateral flat charge of the n-conducting zones 3 does not exceed twice the amount of dopant corresponding to the breakdown charge.
- n-type zones 3 or the semiconductor body 1
- several layers with different doping can also be provided.
- the n * -lecting zone 2 can also be replaced by an np + bad sequence or an n ⁇ -p + bad sequence, as is indicated in FIG. 1 by a stitch line 15.
- the doping of the polycrystalline silicon 12 in the auxiliary electrodes 11 need not be homogeneous.
- FIG. 2 shows a further exemplary embodiment of the invention, in which, in contrast to the exemplary embodiment of FIG. 1, two auxiliary electrodes 11 are assigned to each cell.
- two auxiliary electrodes 11 are assigned to each cell.
- the auxiliary electrodes 11 it is also not necessary for the auxiliary electrodes 11 to reach the highly doped n + -type layer 2 on the side of the drain connection D.
- these auxiliary electrodes 11 already end at an n " -type layer 14, which is provided between the ⁇ -type layer 2 and the n-type zones 3.
- the invention thus enables a MOSFET which can be produced in a simple manner and which only requires the usual steps in semiconductor technology when introducing trenches and nevertheless ensures a low on-resistance R on .
- a vertical structure of the MOS field-effect transistor according to the invention is described.
- the invention can, however, also be applied to a lateral structure in which the auxiliary electrodes 11 in the semiconductor body extend in the lateral direction.
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000585937A JP3859969B2 (ja) | 1998-11-27 | 1999-11-04 | 補助電極を有するmos電界効果トランジスタ |
| DE59914942T DE59914942D1 (de) | 1998-11-27 | 1999-11-04 | Mos-feldeffekttransistor mit hilfselektrode |
| EP99963211A EP1051756B1 (de) | 1998-11-27 | 1999-11-04 | Mos-feldeffekttransistor mit hilfselektrode |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19854915A DE19854915C2 (de) | 1998-11-27 | 1998-11-27 | MOS-Feldeffekttransistor mit Hilfselektrode |
| DE19854915.6 | 1998-11-27 | ||
| US09/627,319 US6362505B1 (en) | 1998-11-27 | 2000-07-27 | MOS field-effect transistor with auxiliary electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2000033385A1 true WO2000033385A1 (de) | 2000-06-08 |
Family
ID=26050432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/DE1999/003542 Ceased WO2000033385A1 (de) | 1998-11-27 | 1999-11-04 | Mos-feldeffekttransistor mit hilfselektrode |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6362505B1 (de) |
| EP (1) | EP1051756B1 (de) |
| DE (1) | DE19854915C2 (de) |
| WO (1) | WO2000033385A1 (de) |
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| EP1300886A2 (de) | 2001-09-07 | 2003-04-09 | Power Integrations, Inc. | Hochspannungshalbleiteranordnungen |
| EP1291907A3 (de) * | 2001-09-07 | 2004-02-04 | Power Integrations, Inc. | Verfahren zur Herstellung von Hochspannungshalbleiteranordnungen |
| WO2003098700A3 (en) * | 2002-05-14 | 2004-04-01 | Motorola Inc | Resurf super-junction devices having trenches |
| EP1168455A3 (de) * | 2000-06-30 | 2004-05-12 | Kabushiki Kaisha Toshiba | Leistungshalbleiter-Schaltelement |
| US6768171B2 (en) | 2000-11-27 | 2004-07-27 | Power Integrations, Inc. | High-voltage transistor with JFET conduction channels |
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| US7037742B2 (en) | 2001-07-23 | 2006-05-02 | Cree, Inc. | Methods of fabricating light emitting devices using mesa regions and passivation layers |
| US7115958B2 (en) | 2001-10-29 | 2006-10-03 | Power Integrations, Inc. | Lateral power MOSFET for high switching speeds |
| US7221011B2 (en) | 2001-09-07 | 2007-05-22 | Power Integrations, Inc. | High-voltage vertical transistor with a multi-gradient drain doping profile |
| CN100339959C (zh) * | 2001-10-17 | 2007-09-26 | 费查尔德半导体有限公司 | 具有改善的较小正向电压损耗的半导体器件以及制作方法 |
| US7468536B2 (en) | 2007-02-16 | 2008-12-23 | Power Integrations, Inc. | Gate metal routing for transistor with checkerboarded layout |
| US7557406B2 (en) | 2007-02-16 | 2009-07-07 | Power Integrations, Inc. | Segmented pillar layout for a high-voltage vertical transistor |
| US7595523B2 (en) | 2007-02-16 | 2009-09-29 | Power Integrations, Inc. | Gate pullback at ends of high-voltage vertical transistor structure |
| US9543396B2 (en) | 2013-12-13 | 2017-01-10 | Power Integrations, Inc. | Vertical transistor device structure with cylindrically-shaped regions |
| US10325988B2 (en) | 2013-12-13 | 2019-06-18 | Power Integrations, Inc. | Vertical transistor device structure with cylindrically-shaped field plates |
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| DE10040452B4 (de) * | 2000-08-18 | 2006-05-24 | Infineon Technologies Ag | Durch Feldeffekt steuerbares Halbleiterbauelement |
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| CN102646710B (zh) * | 2012-04-06 | 2014-08-27 | 东南大学 | 一种超结纵向双扩散金属氧化物半导体管 |
| DE102014109859B4 (de) * | 2014-07-14 | 2021-08-26 | Infineon Technologies Austria Ag | Halbleitervorrichtungen mit einer feldelektrode, synchron-gleichrichtungsvorrichtung und energieversorgung |
| CN111033656A (zh) * | 2017-11-30 | 2020-04-17 | 株式会社村田制作所 | 电容器 |
| EP4092752A1 (de) | 2021-05-21 | 2022-11-23 | Infineon Technologies Austria AG | Halbleiterchip mit einer transistorvorrichtung und verfahren zu seiner herstellung |
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| EP1408554B1 (de) * | 1996-02-05 | 2015-03-25 | Infineon Technologies AG | Durch Feldeffekt steuerbares Halbleiterbauelement |
| DE19611045C1 (de) * | 1996-03-20 | 1997-05-22 | Siemens Ag | Durch Feldeffekt steuerbares Halbleiterbauelement |
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| EP1168455A3 (de) * | 2000-06-30 | 2004-05-12 | Kabushiki Kaisha Toshiba | Leistungshalbleiter-Schaltelement |
| US6750508B2 (en) | 2000-06-30 | 2004-06-15 | Kabushiki Kaisha Toshiba | Power semiconductor switching element provided with buried electrode |
| US6768171B2 (en) | 2000-11-27 | 2004-07-27 | Power Integrations, Inc. | High-voltage transistor with JFET conduction channels |
| US7037742B2 (en) | 2001-07-23 | 2006-05-02 | Cree, Inc. | Methods of fabricating light emitting devices using mesa regions and passivation layers |
| US6787847B2 (en) | 2001-09-07 | 2004-09-07 | Power Integrations, Inc. | High-voltage vertical transistor with a multi-layered extended drain structure |
| US7459366B2 (en) | 2001-09-07 | 2008-12-02 | Power Integrations, Inc. | High-voltage vertical transistor with a multi-gradient drain doping profile |
| US8940605B2 (en) | 2001-09-07 | 2015-01-27 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor with an extended drain structure |
| EP1300886A3 (de) * | 2001-09-07 | 2004-02-18 | Power Integrations, Inc. | Hochspannungshalbleiteranordnungen |
| EP1300886A2 (de) | 2001-09-07 | 2003-04-09 | Power Integrations, Inc. | Hochspannungshalbleiteranordnungen |
| US6798020B2 (en) | 2001-09-07 | 2004-09-28 | Power Integrations, Inc. | High-voltage lateral transistor with a multi-layered extended drain structure |
| US6815293B2 (en) | 2001-09-07 | 2004-11-09 | Power Intergrations, Inc. | High-voltage lateral transistor with a multi-layered extended drain structure |
| US6838346B2 (en) | 2001-09-07 | 2005-01-04 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor with a multi-layered extended drain structure |
| EP1521307A2 (de) | 2001-09-07 | 2005-04-06 | Power Integrations, Inc. | Hochspannungshalbleiteranordnungen |
| US6882005B2 (en) | 2001-09-07 | 2005-04-19 | Power Integrations, Inc. | High-voltage vertical transistor with a multi-layered extended drain structure |
| EP1536464A2 (de) | 2001-09-07 | 2005-06-01 | Power Integrations, Inc. | Verfahren zur Herstellung von Hochspannungshalbleiteranordnungen |
| US6987299B2 (en) | 2001-09-07 | 2006-01-17 | Power Integrations, Inc. | High-voltage lateral transistor with a multi-layered extended drain structure |
| EP1291907A3 (de) * | 2001-09-07 | 2004-02-04 | Power Integrations, Inc. | Verfahren zur Herstellung von Hochspannungshalbleiteranordnungen |
| EP2270843A3 (de) * | 2001-09-07 | 2011-01-26 | Power Integrations, Inc. | Verfahren zur Herstellung eines Hochspannungstransistors mit isoliertem Gate |
| US7221011B2 (en) | 2001-09-07 | 2007-05-22 | Power Integrations, Inc. | High-voltage vertical transistor with a multi-gradient drain doping profile |
| US7253042B2 (en) | 2001-09-07 | 2007-08-07 | Power Integrations, Inc. | Method of fabricating a high-voltage transistor with an extended drain structure |
| EP1521307A3 (de) * | 2001-09-07 | 2008-08-06 | Power Integrations, Inc. | Hochspannungshalbleiteranordnungen |
| EP1536464A3 (de) * | 2001-09-07 | 2008-08-06 | Power Integrations, Inc. | Verfahren zur Herstellung von Hochspannungshalbleiteranordnungen |
| CN100339959C (zh) * | 2001-10-17 | 2007-09-26 | 费查尔德半导体有限公司 | 具有改善的较小正向电压损耗的半导体器件以及制作方法 |
| US7115958B2 (en) | 2001-10-29 | 2006-10-03 | Power Integrations, Inc. | Lateral power MOSFET for high switching speeds |
| US6750524B2 (en) | 2002-05-14 | 2004-06-15 | Motorola Freescale Semiconductor | Trench MOS RESURF super-junction devices |
| WO2003098700A3 (en) * | 2002-05-14 | 2004-04-01 | Motorola Inc | Resurf super-junction devices having trenches |
| US7468536B2 (en) | 2007-02-16 | 2008-12-23 | Power Integrations, Inc. | Gate metal routing for transistor with checkerboarded layout |
| US7557406B2 (en) | 2007-02-16 | 2009-07-07 | Power Integrations, Inc. | Segmented pillar layout for a high-voltage vertical transistor |
| US7595523B2 (en) | 2007-02-16 | 2009-09-29 | Power Integrations, Inc. | Gate pullback at ends of high-voltage vertical transistor structure |
| US9601613B2 (en) | 2007-02-16 | 2017-03-21 | Power Integrations, Inc. | Gate pullback at ends of high-voltage vertical transistor structure |
| US9543396B2 (en) | 2013-12-13 | 2017-01-10 | Power Integrations, Inc. | Vertical transistor device structure with cylindrically-shaped regions |
| US10325988B2 (en) | 2013-12-13 | 2019-06-18 | Power Integrations, Inc. | Vertical transistor device structure with cylindrically-shaped field plates |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19854915C2 (de) | 2002-09-05 |
| DE19854915A1 (de) | 2000-06-08 |
| EP1051756A1 (de) | 2000-11-15 |
| EP1051756B1 (de) | 2008-12-31 |
| US6362505B1 (en) | 2002-03-26 |
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