WO2001006648A1 - Integrated circuit - Google Patents

Integrated circuit Download PDF

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Publication number
WO2001006648A1
WO2001006648A1 PCT/EP2000/006344 EP0006344W WO0106648A1 WO 2001006648 A1 WO2001006648 A1 WO 2001006648A1 EP 0006344 W EP0006344 W EP 0006344W WO 0106648 A1 WO0106648 A1 WO 0106648A1
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WO
WIPO (PCT)
Prior art keywords
gyrator
integrated circuit
transistors
mos
series feedback
Prior art date
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Ceased
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PCT/EP2000/006344
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French (fr)
Inventor
Sven Mattisson
Henrik Geis
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Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Priority to MXPA02000394A priority Critical patent/MXPA02000394A/en
Priority to JP2001510984A priority patent/JP2003505907A/en
Priority to IL14751500A priority patent/IL147515A0/en
Priority to DE60009080T priority patent/DE60009080T2/en
Priority to AT00951343T priority patent/ATE262237T1/en
Priority to HK03100485.9A priority patent/HK1048398B/en
Priority to AU64319/00A priority patent/AU6431900A/en
Priority to EP00951343A priority patent/EP1201032B1/en
Publication of WO2001006648A1 publication Critical patent/WO2001006648A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/40—Impedance converters
    • H03H11/42—Gyrators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/02—Multiple-port networks
    • H03H11/04—Frequency selective two-port networks
    • H03H11/08—Frequency selective two-port networks using gyrators

Definitions

  • This invention relates to integrated circuits, and in particular to integrated analog filter circuits.
  • Such devices use transconductance elements such as transistors, in combination with capacitors, which together can form integrators or gyrators, and can emulate the impedance of inductors .
  • the author also proposed a Q-tuning loop, to provide a controllable Q-value for the filter at very high frequencies.
  • the present invention proceeds from the realization that this first order analysis of the prior art structure results in an incomplete understanding of the structure.
  • each MOS transistor adds a delay element due to the actions of charged particles in the channel of the transistor. More specifically, the nonquasi-static behaviour of the channel charge adds a delay, which could be approximated as a parasitic pole, in the frequency characteristic of the transconductance of the device.
  • the channel delays of the transistors can make the gyrator unstable, in particular in the case of higher order filters (which are often required, in order to provide the necessary filter characteristics) , or at higher frequencies (when the channel delay becomes more of a problem) .
  • the channel delay means that the prior art Q-tuning loop does not function as intended.
  • the present invention attempts to overcome the disadvantages of the prior art, by taking the channel delay of the- transistors into consideration.
  • the invention relates in one aspect to the design of an integrated circuit device, in a way which includes consideration of the channel delay of the transistors.
  • the invention relates to an integrated circuit device, in which the channel delay of a transistor is compensated by means of series feedback.
  • FIG. 1 is a block schematic diagram of a gyrator circuit in accordance with the invention.
  • Figure 2 is a circuit diagram of an inverter in the circuit of Figure 1.
  • Figure 3 is a circuit diagram showing a transistor, with a feedback circuit, which can be used in the circuit of Figure 1.
  • Figure 4 is a plot of transfer-admittance magnitude against frequency for devices according to the invention.
  • Figure 5 is a plot of transfer-admittance phase against frequency for devices according to the invention.
  • Figure 6 is a circuit diagram showing a transistor, with a feedback circuit, which can be used in the circuit of Figure 1.
  • Figure 1 shows a gyrator cell 2.
  • the core of the gyrator cell comprises four CMOS inverter circuits 4, 6, 8, 10, which are arranged in a loop, with the output of each inverter being connected to the input of the next.
  • the gyrator has first and second differential inputs i_l, i_2 , and first and second differential outputs o_l, o_2.
  • the cell also includes an input common mode feedback network 12 , comprising inverters 14, 16, 18, 20, and an output common mode feedback network 22, comprising inverters 24, 26, 28, 30.
  • a gyrator In general, a gyrator consists of a positive transconductance and a negative transconductance .
  • the negative transconductance is formed by using differential signals and crossing one pair of wires. It is this crossing of the wires to form a cross-coupled structure which results in stability problems.
  • the present invention applies to any cross-coupled structure.
  • the analysis herein is set out in the context of a gyrator, and hence relates specifically to filters formed from gyrators. However, the same analysis applies also to integrators, and hence also to filters formed from integrators. Thus, the present invention encompasses such devices.
  • CMOS inverters as shown in Figure 2
  • the subsequent description relates primarily to such devices.
  • the analysis applies also to bipolar and BiCMOS devices, and hence also to filters formed from such devices .
  • the present invention encompasses such devices also.
  • the present invention proceeds from the realization that the conventional first order analysis of the properties of the devices, for example, in the case of a MOS transistor, assuming that the MOS transadmittance is purely conductive, is inadequate.
  • MOS transadmittance modelling the channel delay
  • this analysis gives different possible approximations for the effect of the channel delay.
  • a first possibility is to assume a pure delay, using the exponential function. However, the resulting function is difficult to use in analyses.
  • a second possibility is to use the final approximation, which gives a zero in the right-hand half of the complex plane.
  • a third possibility is to use the intermediate approximation, which gives a pole.
  • the second and third possible models give the same phase lag, providing the pole and zero time constants are equal, so this aspect of the stability analysis is satisfactory.
  • the zero in the right-hand half of the complex plane gives the amplitude of the transadmittance a high-pass characteristic, while the intermediate approximation, with the pole, gives the amplitude of the transadmittance a low-pass characteristic. The latter is more realistic, and so that is the model used hereinafter.
  • each MOS transistor in the gyrator core has series feedback added thereto.
  • Figure 3 shows a transistor 42 and feedback circuit 44.
  • the feedback circuit 44 comprises the parallel combination of a feedback resistor Rf (having resistance r f ) and capacitor Cf (having capacitance c f ) , connected to the source terminal of the transistor aud in series with it.
  • Rf having resistance
  • r f a feedback resistor
  • the closed loop transfer- admitt ⁇ nce G T is :
  • G T will approximate l/z f at low frequencies.
  • G T will have a left half- plane zero, resulting in an initial phase advance. Since, without feedback, there is a phase lag, this suggests that a balance condition can be found, in which, at least below a particular frequency, the phase-lag can be minimized.
  • the resulting design can then be used as the basis for an integrated circuit device .
  • the characteristic parameters (such as 9 m ' r f ⁇ gm an ⁇ 3- ⁇ f ) should have a constant relationship in all production devices at different operating temperatures and supply voltages .
  • Figure 6 shows a way of achieving this in an IC.
  • an MOS transistor 50 operating in its triode region, is used as the- feedback impedance.
  • r f l/g d
  • C f C g .
  • the bias voltage connected to the gate of the transistor 50 tracks variations in the supply voltage to the gyrator cell .
  • the supply voltage to the gyrator cell is derived from a tuning circuit, which provides a voltage which is dependent on variations in process, temperature and supply voltage.
  • the bias voltage tracks variations in the gyrator cell tuning voltage, this can ensure that r f « l/g m and ⁇ f « x over normal variations in process, temperature and supply.

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  • Networks Using Active Elements (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Amplifiers (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Nitrogen Condensed Heterocyclic Rings (AREA)

Abstract

The invention relates to an integrated gyrator structure, in which each transistor in the gyrator core (preferably MOS devices) has series feedback associated therewith. This allows for compensation over a large bandwidth of the effects of channel delay in the MOS transistors.

Description

INTEGRATED CIRCUIT TECHNICAL FIELD
This invention relates to integrated circuits, and in particular to integrated analog filter circuits. BACKGROUND OF THE INVENTION
In integrated circuits, it is extremely difficult to realise inductors, except with very low inductances. As a result, it is generally only possible to use RC filters (with resistors and capacitors) , except at very high frequencies.
As an alternative, active filters are often used. Such devices use transconductance elements such as transistors, in combination with capacitors, which together can form integrators or gyrators, and can emulate the impedance of inductors .
An integrated gyrator structure, for use in a very high frequency filter, is proposed in Nauta "A CMOS Transconductance-C Filter Technique for Very High Frequencies", IEEE Journal of Solid State Circuits, Vol. 27,. No. 2, February 1992. The author's first order analysis of the circuit concluded that the proposed gyrator behaves stably.
The author also proposed a Q-tuning loop, to provide a controllable Q-value for the filter at very high frequencies.
SUMMARY OF THE INVENTION
The present invention proceeds from the realization that this first order analysis of the prior art structure results in an incomplete understanding of the structure.
In particular, a more detailed analysis of the MOS transistors reveals that each MOS transistor adds a delay element due to the actions of charged particles in the channel of the transistor. More specifically, the nonquasi-static behaviour of the channel charge adds a delay, which could be approximated as a parasitic pole, in the frequency characteristic of the transconductance of the device. The channel delays of the transistors can make the gyrator unstable, in particular in the case of higher order filters (which are often required, in order to provide the necessary filter characteristics) , or at higher frequencies (when the channel delay becomes more of a problem) .
Moreover, the channel delay means that the prior art Q-tuning loop does not function as intended.
The present invention attempts to overcome the disadvantages of the prior art, by taking the channel delay of the- transistors into consideration.
Specifically, the invention relates in one aspect to the design of an integrated circuit device, in a way which includes consideration of the channel delay of the transistors.
In another aspect, the invention relates to an integrated circuit device, in which the channel delay of a transistor is compensated by means of series feedback.
In another aspect, the invention relates to the design method, which accounts for the channel delay. BRIEF DESCRIPTION OF DRAWINGS Figure 1 is a block schematic diagram of a gyrator circuit in accordance with the invention.
Figure 2 is a circuit diagram of an inverter in the circuit of Figure 1.
Figure 3 is a circuit diagram showing a transistor, with a feedback circuit, which can be used in the circuit of Figure 1.
Figure 4 is a plot of transfer-admittance magnitude against frequency for devices according to the invention. Figure 5 is a plot of transfer-admittance phase against frequency for devices according to the invention.
Figure 6 is a circuit diagram showing a transistor, with a feedback circuit, which can be used in the circuit of Figure 1.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
Figure 1 shows a gyrator cell 2. The core of the gyrator cell comprises four CMOS inverter circuits 4, 6, 8, 10, which are arranged in a loop, with the output of each inverter being connected to the input of the next. The gyrator has first and second differential inputs i_l, i_2 , and first and second differential outputs o_l, o_2. The cell also includes an input common mode feedback network 12 , comprising inverters 14, 16, 18, 20, and an output common mode feedback network 22, comprising inverters 24, 26, 28, 30.
In general, a gyrator consists of a positive transconductance and a negative transconductance . In the cell of Figure 1, the negative transconductance is formed by using differential signals and crossing one pair of wires. It is this crossing of the wires to form a cross-coupled structure which results in stability problems. Thus, the present invention applies to any cross-coupled structure. The analysis herein is set out in the context of a gyrator, and hence relates specifically to filters formed from gyrators. However, the same analysis applies also to integrators, and hence also to filters formed from integrators. Thus, the present invention encompasses such devices.
In devices according to the present invention, conventional CMOS inverters, as shown in Figure 2, may conveniently be used, and the subsequent description relates primarily to such devices. However, the analysis applies also to bipolar and BiCMOS devices, and hence also to filters formed from such devices . Thus, the present invention encompasses such devices also.
The present invention proceeds from the realization that the conventional first order analysis of the properties of the devices, for example, in the case of a MOS transistor, assuming that the MOS transadmittance is purely conductive, is inadequate. An alternative analysis, considering a nonquasi-static channel delay, is therefore proposed.
Thus, the MOS transadmittance, modelling the channel delay, can be approximated as:
s.T-. am
S γm - oσπfe ^ ~ I , ~ o £m - S.C m " *" here conventional notation has been used, that is, gm is the device transconductance, Cgs is the device gate- source capacitance, x = 2/(εωT)ι . = 2Cga/ε, where ωτ is the transit angular frequency, that is, the angular frequency when the current gain is one, and. ε, the Elmore constant of the channel =5.
Thus, this analysis gives different possible approximations for the effect of the channel delay. A first possibility is to assume a pure delay, using the exponential function. However, the resulting function is difficult to use in analyses. A second possibility is to use the final approximation, which gives a zero in the right-hand half of the complex plane. A third possibility is to use the intermediate approximation, which gives a pole. The second and third possible models give the same phase lag, providing the pole and zero time constants are equal, so this aspect of the stability analysis is satisfactory. The zero in the right-hand half of the complex plane gives the amplitude of the transadmittance a high-pass characteristic, while the intermediate approximation, with the pole, gives the amplitude of the transadmittance a low-pass characteristic. The latter is more realistic, and so that is the model used hereinafter.
In one advantageous embodiment of the invention, each MOS transistor in the gyrator core has series feedback added thereto. Figure 3 shows a transistor 42 and feedback circuit 44. Specifically, the feedback circuit 44 comprises the parallel combination of a feedback resistor Rf (having resistance rf) and capacitor Cf (having capacitance cf) , connected to the source terminal of the transistor aud in series with it. Defining the impedance of the feedback circuit as rf || cf = zf, = rf/(l+s.τf), the closed loop transfer- admittεnce GT is :
Figure imgf000006_0001
In the limit, when gm.rf»l, GT will approximate l/zf at low frequencies. Thus, GT will have a left half- plane zero, resulting in an initial phase advance. Since, without feedback, there is a phase lag, this suggests that a balance condition can be found, in which, at least below a particular frequency, the phase-lag can be minimized. Thus, by choosing an appropriate approximation for the channel delay, it is possible to compensate therefor over a large bandwidth. The resulting design can then be used as the basis for an integrated circuit device . Figures 4 and 5 show various plots A-G of the magnitude and phase respectively of the transfer- admittance, for different values of the parameters T and z, where T = gm.rf, and τf = 1/z, and where τ^ = 1. It can thus be seen that a moderate loop gain can result in a substantial widening of the trans dmittance bandwidth, and can also provide some phase lead, which may be de-sirable to compensate for some other parasitic-induced phase lag.
In a practical application of the invention, it is important that the characteristic parameters (such as 9m' r f τ gm an<3- τ f) should have a constant relationship in all production devices at different operating temperatures and supply voltages . Figure 6 shows a way of achieving this in an IC. Specifically, an MOS transistor 50, operating in its triode region, is used as the- feedback impedance. In this case, rf = l/gd and Cf = Cg. Advantageously, the bias voltage connected to the gate of the transistor 50 tracks variations in the supply voltage to the gyrator cell . In the case of the gyrator structure proposed by Nau a in "A CMOS
Transconductance-C Filter Technique for Very High Frequencies", IEEE Journal of Solid State Circuits, Vol. 27, No. 2, February 1992, for example, the supply voltage to the gyrator cell is derived from a tuning circuit, which provides a voltage which is dependent on variations in process, temperature and supply voltage. Thus, if the bias voltage tracks variations in the gyrator cell tuning voltage, this can ensure that rf « l/gm and τf « x over normal variations in process, temperature and supply. There is thus provided a circuit which can compensate for channel delay in a gyrator or other cross-coupled structure. There is further provided a method of designing an integrated circuit to achieve such compensation.

Claims

1. An integrated circuit gyrator, having series feedback associated with at least some of the transistors therein.
2. An integrated circuit gyrator as claimed in claim 1, comprising a plurality of inverters arranged in a loop .
3. An integrated circuit gyrator as claimed in claim 2, having a pair of input terminals and a pair of output terminals.
4. An integrated circuit gyrator as claimed in claim 2, having a cross-coupled structure .
5. An integrated circuit gyrator as claimed in claim 2, wherein the inverters are MOS inverters.
6. An integrated circuit gyrator as claimed in claim 5, having series feedback associated with each MOS device in the MOS integrators.
7. An integrated circuit gyrator as claimed in claim 1, wherein the series feedback is provided by a parallel combination of a resistor and a capacitor, connected in series with the respective transistor.
8. An integrated circuit gyrator as claimed in claim 7, wherein the transistors are MOS devices, and each parallel combination of a resistor and a capacitor is connected to the source terminal of the respective transistor.
9. An integrated circuit gyrator as claimed in claim 1, wherein the transistors are MOS devices, and the series feedback is provided by a further MOS transistor connected to the respective device, each further MOS transistor having a bias voltage applied thereto such that it operates in its triode region.
10. An integrated circuit gyrator as claimed in claim 9, wherein the bias voltage tracks variations in a gyrator supply voltage.
11. A method of designing an integrated circuit analog filter, the filter comprising at least one cross-coupled structure containing a plurality of transistors, the method comprising accounting for the channel delay of at least some of said transistors, and adding series feedback associated with said transistors to compensate therefor over a large bandwidth.
12. A method as claimed in claim 11, further comprising realising an integrated circuit structure in accordance with said method.
13. A cross-coupled integrated circuit transistor structure, having series feedback associated with at least some of the transistors therein.
14. A cross-coupled MOS structure, having series feedback associated with at least some of the transistors therein.
15. A MOS gyrator, having series feedback associated with at least some of the transistors therein.
16. A MOS gyrator, including a gyrator core comprising a plurality of MOS inverters, having series feedback associated with at least some of the transistors in said gyrator core .
17. An integrated circuit analog filter, comprising a plurality of integrators, wherein the integrators have series feedback associated with at least some of the transistors therein.
18. An integrated circuit analog filter, comprising a plurality of gyrators, wherein the gyrators have series feedback associated with at least some of the transistors therein.
PCT/EP2000/006344 1999-07-16 2000-07-05 Integrated circuit Ceased WO2001006648A1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
MXPA02000394A MXPA02000394A (en) 1999-07-16 2000-07-05 Integrated circuit.
JP2001510984A JP2003505907A (en) 1999-07-16 2000-07-05 Integrated circuit
IL14751500A IL147515A0 (en) 1999-07-16 2000-07-05 Integrated circuit
DE60009080T DE60009080T2 (en) 1999-07-16 2000-07-05 INTEGRATED GYRATOR SWITCHING
AT00951343T ATE262237T1 (en) 1999-07-16 2000-07-05 INTEGRATED GYRATOR CIRCUIT
HK03100485.9A HK1048398B (en) 1999-07-16 2000-07-05 Integrated circuit
AU64319/00A AU6431900A (en) 1999-07-16 2000-07-05 Integrated circuit
EP00951343A EP1201032B1 (en) 1999-07-16 2000-07-05 Integrated gyrator circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9916808.0 1999-07-16
GB9916808A GB2352102B (en) 1999-07-16 1999-07-16 Integrated circuit

Publications (1)

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WO2001006648A1 true WO2001006648A1 (en) 2001-01-25

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US (1) US6577212B1 (en)
EP (1) EP1201032B1 (en)
JP (1) JP2003505907A (en)
CN (1) CN100345376C (en)
AT (1) ATE262237T1 (en)
AU (1) AU6431900A (en)
DE (1) DE60009080T2 (en)
GB (1) GB2352102B (en)
HK (1) HK1048398B (en)
IL (1) IL147515A0 (en)
MX (1) MXPA02000394A (en)
MY (1) MY133239A (en)
TR (1) TR200200080T2 (en)
WO (1) WO2001006648A1 (en)

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Publication number Priority date Publication date Assignee Title
US6665403B1 (en) * 1999-05-11 2003-12-16 Agere Systems Inc. Digital gyrator
GB0200094D0 (en) * 2002-01-04 2002-02-20 Koninkl Philips Electronics Nv Balanced gyrator and devices including the balanced gyrator
DE102006043833A1 (en) * 2006-09-19 2008-03-27 Valeo Schalter Und Sensoren Gmbh Circuit arrangement for protection of consumer e.g. on-board electrical system of motor vehicle, has gyrator circuit connected with direct current voltage network at input side and with consumer that is protected at output side
KR100921517B1 (en) * 2006-12-05 2009-10-15 한국전자통신연구원 Navata operational cross-conductance amplifier
US8242863B2 (en) * 2008-08-15 2012-08-14 Infineon Technologies Ag Active inductance for very high frequencies based on CMOS inverters
US8897722B2 (en) * 2009-09-11 2014-11-25 Broadcom Corporation RF front-end with wideband transmitter/receiver isolation
US8723625B2 (en) * 2009-12-18 2014-05-13 Electronics And Telecommunications Research Institute Amplification cell employing linearization method and active inductor using the same
KR101462158B1 (en) * 2009-12-18 2014-12-04 한국전자통신연구원 Amplifying cell applying linearization method and active inductor using the same
US8502626B2 (en) 2009-12-30 2013-08-06 Broadcom Corporation RF front-end with on-chip transmitter/receiver isolation using the hall effect
CN113884204B (en) * 2021-10-22 2024-05-28 合肥艾创微电子科技有限公司 Circuit for converting temperature variation into voltage variation in motor driving system

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EP1201032B1 (en) 2004-03-17
CN1361940A (en) 2002-07-31
CN100345376C (en) 2007-10-24
IL147515A0 (en) 2002-08-14
AU6431900A (en) 2001-02-05
US6577212B1 (en) 2003-06-10
HK1048398A1 (en) 2003-03-28
DE60009080T2 (en) 2005-01-27
HK1048398B (en) 2008-02-15
ATE262237T1 (en) 2004-04-15
DE60009080D1 (en) 2004-04-22
MXPA02000394A (en) 2002-07-02
TR200200080T2 (en) 2002-06-21
JP2003505907A (en) 2003-02-12
GB2352102B (en) 2004-06-16
EP1201032A1 (en) 2002-05-02
GB2352102A (en) 2001-01-17
MY133239A (en) 2007-10-31
GB9916808D0 (en) 1999-09-22

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