WO2001017007A1 - Method of etching and method of plasma treatment - Google Patents
Method of etching and method of plasma treatment Download PDFInfo
- Publication number
- WO2001017007A1 WO2001017007A1 PCT/JP2000/005624 JP0005624W WO0117007A1 WO 2001017007 A1 WO2001017007 A1 WO 2001017007A1 JP 0005624 W JP0005624 W JP 0005624W WO 0117007 A1 WO0117007 A1 WO 0117007A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- gas
- etching
- etching method
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
- H10P50/287—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials by chemical means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
- H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
- H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W20/00—Interconnections in chips, wafers or substrates
- H10W20/01—Manufacture or treatment
- H10W20/071—Manufacture or treatment of dielectric parts thereof
- H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
- H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
- H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
- H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
Definitions
- the present invention relates to an etching method and a plasma processing method.
- BACKGROUND ART With the trend toward ultra-high integration of semiconductor devices, ultra-miniaturization of design rules for metal wiring has recently been cited as one of the technical requirements.
- AI-based wiring such as AI and AI alloys
- the electrical resistance cannot be ignored with the miniaturization of wiring, and wiring delays that lower the operating speed of semiconductor devices tend to occur. Therefore, a technology has recently been proposed that uses Cu, which has a lower electrical resistance than AI, as the wiring material.
- Cu has the property of being more easily oxidized than AI.
- the present invention has been made in view of the above problems of the prior art, and an object of the present invention is to provide a new and improved etching method capable of solving the above problems and other problems. And a plasma treatment method.
- a processing gas introduced into a processing chamber is turned into a plasma, and a Cu layer formed on an object to be processed placed in the processing chamber is formed.
- the processing gas includes a gas composed of C, H, and F, and o 2 . If etching is performed using the gas composed of C, H, and F according to the present invention, the exposed surface of the Cu layer is less likely to be oxidized. Further, the effects, with or without 0 2, is maintained.
- the photo resist layer is etched after the step of etching the SiN x layer using the photo resist layer on which a predetermined pattern is formed, and the etching step.
- a plasma processing method comprising: introducing H 2 into the processing chamber after the assuring step; converting the H 2 into plasma; and performing plasma processing on the exposed Cu layer.
- the exposed surface of the Cu layer may be oxidized during asshing.
- C (carbon atoms) and F (fluorine atoms) may be implanted on the exposed surface of the Cu layer.
- FIG. 1 is a schematic sectional view showing a plasma processing apparatus to which the present invention can be applied.
- FIG. 2 is a schematic cross-sectional view showing a wafer before and after the reprocessing by the etching method of the present invention.
- FIG. 3 is a schematic explanatory diagram for explaining an embodiment of the etching method according to the present invention.
- FIG. 4 is a schematic explanatory diagram for explaining an embodiment of the etching method according to the present invention.
- a plasma processing apparatus 100 to which the etching method according to the present embodiment can be applied will be outlined with reference to FIG.
- the processing chamber 102 is formed in an airtight processing container 104.
- a magnet 106 is arranged around the processing vessel 104, and a rotating magnetic field can be formed in the processing chamber 102.
- a lower electrode 108 on which an object to be processed for example, a semiconductor wafer (hereinafter, referred to as “wafer”) W, can be placed.
- an upper electrode 110 is disposed so as to face the mounting surface of the lower electrode 108.
- a large number of gas discharge holes 110a are formed in the upper electrode 110.
- the first to third on-off valves 1 1 2 and 1 1 The first to third gas supply sources 124, 126, and 128 are respectively connected to the first, second, third, and fourth flow control valves 111, 120, and 122, respectively. It is connected.
- the first to third gas supply source 1 24, 1 26, 1 2 8, CH 2 F 2 constituting such process gas to the embodiment 0 2 and A r are stored respectively. With such a configuration, the inside of the processing chamber 1 02, through the gas discharge holes 1 1 0 a, each process gas consisting of a predetermined flow rate CH 2 F 2 0 2 and A r are introduced. The etching process using the above processing gas will be described later.
- the processing gas introduced into the processing chamber 102 is turned into plasma when high-frequency power output from the high-frequency power supply 130 is applied to the lower electrode 108 through the matching unit 132.
- the gas in the processing chamber 102 is exhausted through a baffle plate 134 provided around the lower electrode 108 and an exhaust pipe 136.
- the plasma processing apparatus 100 is configured to perform not only the etching processing but also the below-described etching processing and the surface processing of the Cu layer 204.
- FIG. 2A is a schematic cross-sectional view showing the wafer W before the SiN x layer 206 is etched.
- FIG. 2B is a schematic cross-sectional view showing the wafer W after the SiN x layer 206 has been etched.
- the first SiO 2 layer 200 is applied to the W via a TaN layer 202 as a barrier metal layer.
- a Cu layer (Cu wiring layer) 204 is formed.
- a SiNx layer 206 to be subjected to etching according to the present embodiment is formed to prevent oxidation of the Cu layer 204. Further, on the S i N x layer 206, and the 2 S i 0 2 layer 208 as an interlayer insulating film, follower Torejisu coat layer 2 1 0 in which a predetermined pattern is formed are sequentially laminated. As shown in Fig. 2 (a), the second etching
- the processing gas introduced into the processing chamber 102 is converted from the processing gas obtained by etching the second SiO 2 layer 208 into CH 2 F 2 , O 2, and A, which are the features of the present embodiment. Switch to process gas consisting of r. At this time, CH
- the flow ratio of 2 F 2 , O 2, and Ar is, for example, “! 0 sccm to 30 sccm mz 10 sccm to 30 sccm / 3000 sccm to 200 sccm.
- the pressure in the processing chamber 102 is set, for example, to 30 mT orr to 100 OmT orr, and then to the lower electrode 108, for example, to 300 W to 1 at 13.56 MHz.
- a high-frequency power of 00 OW is applied, and the processing gas is dissociated to generate a plasma by applying the high-frequency power, and as a result, as shown in FIG.
- FIGS. 3 (a) and 3 (b) and FIGS. 4 (a) and 4 (b) respectively show the depth from the surface of the Cu layer 204 and the element contained in the Cu layer 204 at that depth.
- FIG. 3 is a schematic explanatory diagram showing the relationship with the content.
- the Cu layer 204 was gradually cut by spraying Ar at a predetermined pressure on the exposed surface of the Cu layer 204.
- the etching process is performed on the SiN x layer 206 of the wafer W shown in FIG. 2A using the plasma processing apparatus 100 described above.
- the pressure inside the processing chamber 102 was set to 50 mTorr.
- a 500 W high-frequency power at 13.56 MHz was applied to the lower electrode 108.
- etching was performed using a processing gas consisting of CH 2 F 2 , N 2, and Ar instead of N 2 , the results shown in Fig. 4 (a) were obtained.
- Other processing conditions are the same as above. As shown in FIG.
- Temperature control of I c W is performed by a temperature control mechanism (not shown) incorporated in lower electrode 108.
- a processing gas of, for example, O 2 is introduced into the processing chamber 102 at a flow rate of, for example, 200 sccm.
- a high-frequency power of 100 W is applied to the lower electrode 108 at, for example, 13.5.6 MHz.
- the processing gas is turned into plasma and the photoresist layer 210 of the wafer W shown in FIG. 2B is removed.
- the oxidation of the Cu layer 204 can be suppressed because the assing processing is performed while maintaining the wafer W at a temperature of 100 ° C. or less. You. Therefore, the Cu layer 204 can be maintained in substantially the same state after the etching process as in the etching process.
- the pressure in the processing chamber 102 is set to, for example, 5 OmTorr. Thereafter, the lower electrode "! 08, for example by applying high-frequency power of 1 000W at 1 3. 5 6 MH z, generates and H 2 plasma in the processing chamber 1 02.
- the oxidized Cu in the layer 204 is reduced, and simultaneously, ion bombardment is applied to the Cu layer 204, so that C and F implanted into the Cu layer 204 during the etching process are also removed.
- a Cu layer 204 free of O (oxygen atoms), C, and F can be formed, and the etching method described above is applied to the Cu layer 204 before and after the H 2 plasma treatment.
- the relationship between the depth from the surface of the Cu layer 204 and the contents of O, C, and F contained in the Cu layer 204 at that depth was examined by the measurement method described in the example. from the surface of u layer 204 The ratios of O, C, and F up to 30 A are much lower than before processing and J is much lower after processing. Also, according to the above method, the plasma processing apparatus 100 that performs etching processing and assing processing has C The surface treatment of the u layer 204 can be performed. Therefore, the surface treatment of the Cu layer 204 does not need to be performed by another processing apparatus. As a result, continuous processing in the plasma processing apparatus 100 becomes possible, thereby improving throughput and reducing costs.
- the present invention is not limited to such a configuration, and an inert gas such as He is used instead of Ar.
- the present invention can be practiced without using a gas or adding an inert gas.
- the configuration in which the etching process, the ashing process, and the surface treatment of the Cu layer are performed by the same plasma processing apparatus has been described as an example.
- the present invention is not limited to such a configuration.
- the present invention can also be implemented by performing each processing in another plasma processing apparatus.
- the SiN x layer on the Cu layer can be etched while minimizing the incorporation of other elements into the Cu layer.
- a plasma treatment using H 2 can it to remove other elements present in C u layer.
- the present invention described possibilities or industrial applications are applicable to the manufacturing process of a semiconductor device, in particular subjected to a plasma treatment such as etching with respect to S i N x layer on the C u layer It is preferably applicable.
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Plasma Technology (AREA)
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE60016423T DE60016423T2 (de) | 1999-08-27 | 2000-08-23 | Ätzmethode und plasmabehandlungsmethode |
| EP00954911A EP1207550B1 (en) | 1999-08-27 | 2000-08-23 | Method of etching and method of plasma treatment |
| US10/030,656 US6780342B1 (en) | 1999-08-27 | 2000-08-23 | Method of etching and method of plasma treatment |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24142799A JP4471243B2 (ja) | 1999-08-27 | 1999-08-27 | エッチング方法およびプラズマ処理方法 |
| JP11/241427 | 1999-08-27 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/902,893 Continuation US7211197B2 (en) | 1999-08-27 | 2004-08-02 | Etching method and plasma processing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2001017007A1 true WO2001017007A1 (en) | 2001-03-08 |
Family
ID=17074148
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2000/005624 Ceased WO2001017007A1 (en) | 1999-08-27 | 2000-08-23 | Method of etching and method of plasma treatment |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US6780342B1 (ja) |
| EP (1) | EP1207550B1 (ja) |
| JP (1) | JP4471243B2 (ja) |
| KR (1) | KR100739909B1 (ja) |
| DE (1) | DE60016423T2 (ja) |
| TW (1) | TW457582B (ja) |
| WO (1) | WO2001017007A1 (ja) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003017469A (ja) * | 2001-06-29 | 2003-01-17 | Tokyo Electron Ltd | エッチング兼アッシング装置、アッシング装置、アッシング方法及び処理方法 |
| US7235884B1 (en) * | 2003-04-01 | 2007-06-26 | Altera Corporation | Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable via |
| US7101487B2 (en) * | 2003-05-02 | 2006-09-05 | Ossur Engineering, Inc. | Magnetorheological fluid compositions and prosthetic knees utilizing same |
| JPWO2005076336A1 (ja) * | 2004-02-09 | 2007-08-02 | 忠弘 大見 | 半導体装置の製造方法および絶縁膜のエッチング方法 |
| US20050227382A1 (en) * | 2004-04-02 | 2005-10-13 | Hui Angela T | In-situ surface treatment for memory cell formation |
| JP2008235918A (ja) * | 2008-04-16 | 2008-10-02 | Tokyo Electron Ltd | プラズマ基板処理装置 |
| CN103839604A (zh) * | 2014-02-26 | 2014-06-04 | 京东方科技集团股份有限公司 | 导电膜及其制备方法、阵列基板 |
| JP6385198B2 (ja) * | 2014-08-21 | 2018-09-05 | 日東電工株式会社 | 回路付サスペンション基板の製造方法 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160077A (ja) * | 1991-12-05 | 1993-06-25 | Sharp Corp | プラズマエッチング方法 |
| JPH06204191A (ja) * | 1992-11-10 | 1994-07-22 | Sony Corp | 金属プラグ形成後の表面処理方法 |
| GB2326765A (en) * | 1997-06-27 | 1998-12-30 | Nec Corp | Multilayer wiring |
| GB2333268A (en) * | 1998-01-20 | 1999-07-21 | Nec Corp | Selective anisotropic plasma etching of a silicon nitride film using CO and a CHF gas at reduced substrate temperature |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6162583A (en) * | 1998-03-20 | 2000-12-19 | Industrial Technology Research Institute | Method for making intermetal dielectrics (IMD) on semiconductor integrated circuits using low dielectric constant spin-on polymers |
| US6107208A (en) | 1998-06-04 | 2000-08-22 | Advanced Micro Devices, Inc. | Nitride etch using N2 /Ar/CHF3 chemistry |
| US6380096B2 (en) * | 1998-07-09 | 2002-04-30 | Applied Materials, Inc. | In-situ integrated oxide etch process particularly useful for copper dual damascene |
| JP3180779B2 (ja) | 1998-10-05 | 2001-06-25 | 日本電気株式会社 | 半導体装置の製造方法 |
| US6093632A (en) * | 1998-12-07 | 2000-07-25 | Industrial Technology Research Institute | Modified dual damascene process |
| US6204192B1 (en) * | 1999-03-29 | 2001-03-20 | Lsi Logic Corporation | Plasma cleaning process for openings formed in at least one low dielectric constant insulation layer over copper metallization in integrated circuit structures |
-
1999
- 1999-08-27 JP JP24142799A patent/JP4471243B2/ja not_active Expired - Lifetime
-
2000
- 2000-08-23 KR KR1020027002517A patent/KR100739909B1/ko not_active Expired - Fee Related
- 2000-08-23 WO PCT/JP2000/005624 patent/WO2001017007A1/ja not_active Ceased
- 2000-08-23 DE DE60016423T patent/DE60016423T2/de not_active Expired - Lifetime
- 2000-08-23 US US10/030,656 patent/US6780342B1/en not_active Expired - Lifetime
- 2000-08-23 EP EP00954911A patent/EP1207550B1/en not_active Expired - Lifetime
- 2000-08-25 TW TW089117250A patent/TW457582B/zh not_active IP Right Cessation
-
2004
- 2004-08-02 US US10/902,893 patent/US7211197B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05160077A (ja) * | 1991-12-05 | 1993-06-25 | Sharp Corp | プラズマエッチング方法 |
| JPH06204191A (ja) * | 1992-11-10 | 1994-07-22 | Sony Corp | 金属プラグ形成後の表面処理方法 |
| GB2326765A (en) * | 1997-06-27 | 1998-12-30 | Nec Corp | Multilayer wiring |
| GB2333268A (en) * | 1998-01-20 | 1999-07-21 | Nec Corp | Selective anisotropic plasma etching of a silicon nitride film using CO and a CHF gas at reduced substrate temperature |
Non-Patent Citations (1)
| Title |
|---|
| See also references of EP1207550A4 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20050000939A1 (en) | 2005-01-06 |
| EP1207550B1 (en) | 2004-12-01 |
| US7211197B2 (en) | 2007-05-01 |
| US6780342B1 (en) | 2004-08-24 |
| JP4471243B2 (ja) | 2010-06-02 |
| JP2001068454A (ja) | 2001-03-16 |
| DE60016423T2 (de) | 2005-11-24 |
| EP1207550A1 (en) | 2002-05-22 |
| DE60016423D1 (de) | 2005-01-05 |
| TW457582B (en) | 2001-10-01 |
| EP1207550A4 (en) | 2002-11-06 |
| KR100739909B1 (ko) | 2007-07-16 |
| KR20020027588A (ko) | 2002-04-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5183850B2 (ja) | 有機ケイ酸塩誘電体の層を有する半導体ウエハからフォトレジストを剥離する方法 | |
| EP0416774B1 (en) | A method of treating a sample of aluminium-containing material | |
| US6777344B2 (en) | Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications | |
| US20090075479A1 (en) | Method of manufacturing semiconductor device | |
| KR100414506B1 (ko) | 드라이 에칭 방법 및 반도체 장치의 제조 방법 | |
| WO2003058700A1 (fr) | Procede de traitement au plasma | |
| TW384512B (en) | Manufacturing method for semiconductor devices and manufacturing apparatuses for semiconductors | |
| WO2003077301A1 (en) | Method of etching and etching apparatus | |
| TW200524669A (en) | Method of cleaning semiconductor substrate conductive layer surface | |
| US6566269B1 (en) | Removal of post etch residuals on wafer surface | |
| KR20030020439A (ko) | 반도체 애플리케이션내의 nh3 플라즈마 디스커밍 및레지스트 박리 | |
| US6693040B2 (en) | Method for cleaning the contact area of a metal line | |
| JP4471243B2 (ja) | エッチング方法およびプラズマ処理方法 | |
| JP3862035B2 (ja) | 半導体装置およびその製造方法 | |
| US5827436A (en) | Method for etching aluminum metal films | |
| US6489238B1 (en) | Method to reduce photoresist contamination from silicon carbide films | |
| WO1999062111A1 (en) | Etching method | |
| JPH0774147A (ja) | ドライエッチング方法およびドライエッチング装置 | |
| TW469488B (en) | Etching method | |
| JP4343379B2 (ja) | 基板処理方法および基板処理装置ならびにデバイス製造方法 | |
| JPH08139004A (ja) | プラズマ処理装置およびプラズマ処理方法 | |
| KR20000073004A (ko) | 금속층 식각에 사용된 포토레지스트 마스크 제거 방법 | |
| KR20000071322A (ko) | 반도체 장치 제조 방법 | |
| JP3901949B2 (ja) | 半導体装置およびその製造方法 | |
| JPH05217965A (ja) | 半導体装置の製造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A1 Designated state(s): KR US |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
| DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
| WWE | Wipo information: entry into national phase |
Ref document number: 10030656 Country of ref document: US |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 2000954911 Country of ref document: EP |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 1020027002517 Country of ref document: KR |
|
| WWP | Wipo information: published in national office |
Ref document number: 1020027002517 Country of ref document: KR |
|
| WWP | Wipo information: published in national office |
Ref document number: 2000954911 Country of ref document: EP |
|
| WWG | Wipo information: grant in national office |
Ref document number: 2000954911 Country of ref document: EP |