WO2001050247A3 - Memory shared between processing threads - Google Patents

Memory shared between processing threads Download PDF

Info

Publication number
WO2001050247A3
WO2001050247A3 PCT/US2000/034537 US0034537W WO0150247A3 WO 2001050247 A3 WO2001050247 A3 WO 2001050247A3 US 0034537 W US0034537 W US 0034537W WO 0150247 A3 WO0150247 A3 WO 0150247A3
Authority
WO
WIPO (PCT)
Prior art keywords
processing threads
memory shared
stack
processor
datum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2000/034537
Other languages
French (fr)
Other versions
WO2001050247A2 (en
Inventor
Gilbert Wolrich
Matthew J Adiletta
William Wheeler
Daniel Cutter
Debra Bernstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to AT00986590T priority Critical patent/ATE280972T1/en
Priority to HK02107751.2A priority patent/HK1046180B/en
Priority to EP20000986590 priority patent/EP1247168B1/en
Priority to DE60015395T priority patent/DE60015395T2/en
Priority to AU22801/01A priority patent/AU2280101A/en
Publication of WO2001050247A2 publication Critical patent/WO2001050247A2/en
Publication of WO2001050247A3 publication Critical patent/WO2001050247A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Seal Device For Vehicle (AREA)
  • Glass Compositions (AREA)

Abstract

A method includes pushing a datum onto a stack by a first processor and popping the datum off the stack by a second processor.
PCT/US2000/034537 2000-01-05 2000-12-19 Memory shared between processing threads Ceased WO2001050247A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
AT00986590T ATE280972T1 (en) 2000-01-05 2000-12-19 MEMORY SHARED BETWEEN PROCESSING THREADS
HK02107751.2A HK1046180B (en) 2000-01-05 2000-12-19 Memory shared between processing threads
EP20000986590 EP1247168B1 (en) 2000-01-05 2000-12-19 Memory shared between processing threads
DE60015395T DE60015395T2 (en) 2000-01-05 2000-12-19 MEMORY IS DIVIDED BETWEEN PROCESSING THREADS
AU22801/01A AU2280101A (en) 2000-01-05 2000-12-19 Memory shared between processing threads

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/479,377 2000-01-05
US09/479,377 US6631462B1 (en) 2000-01-05 2000-01-05 Memory shared between processing threads

Publications (2)

Publication Number Publication Date
WO2001050247A2 WO2001050247A2 (en) 2001-07-12
WO2001050247A3 true WO2001050247A3 (en) 2002-01-31

Family

ID=23903749

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/034537 Ceased WO2001050247A2 (en) 2000-01-05 2000-12-19 Memory shared between processing threads

Country Status (10)

Country Link
US (2) US6631462B1 (en)
EP (1) EP1247168B1 (en)
CN (1) CN1253784C (en)
AT (1) ATE280972T1 (en)
AU (1) AU2280101A (en)
DE (1) DE60015395T2 (en)
HK (1) HK1046180B (en)
SG (1) SG149673A1 (en)
TW (1) TWI222011B (en)
WO (1) WO2001050247A2 (en)

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US6876561B2 (en) 1999-12-28 2005-04-05 Intel Corporation Scratchpad memory
US6895457B2 (en) 1999-12-28 2005-05-17 Intel Corporation Bus interface with a first-in-first-out memory
US6934951B2 (en) 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US6976095B1 (en) 1999-12-30 2005-12-13 Intel Corporation Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US7020871B2 (en) 2000-12-21 2006-03-28 Intel Corporation Breakpoint method for parallel hardware threads in multithreaded processor
US7107413B2 (en) 2001-12-17 2006-09-12 Intel Corporation Write queue descriptor count instruction for high speed queuing
US7111296B2 (en) 1999-12-28 2006-09-19 Intel Corporation Thread signaling in multi-threaded processor
US7126952B2 (en) 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US7149226B2 (en) 2002-02-01 2006-12-12 Intel Corporation Processing data packets
US7158964B2 (en) 2001-12-12 2007-01-02 Intel Corporation Queue management
US7181594B2 (en) 2002-01-25 2007-02-20 Intel Corporation Context pipelines
US7181573B2 (en) 2002-01-07 2007-02-20 Intel Corporation Queue array caching in network devices
US7191309B1 (en) 1999-09-01 2007-03-13 Intel Corporation Double shift instruction for micro engine used in multithreaded parallel processor architecture
US7191321B2 (en) 1999-08-31 2007-03-13 Intel Corporation Microengine for parallel processor architecture
US7213099B2 (en) 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7269179B2 (en) 2001-12-18 2007-09-11 Intel Corporation Control mechanisms for enqueue and dequeue operations in a pipelined network processor
US7305500B2 (en) 1999-08-31 2007-12-04 Intel Corporation Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
US7328289B2 (en) 1999-12-30 2008-02-05 Intel Corporation Communication between processors
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7421572B1 (en) 1999-09-01 2008-09-02 Intel Corporation Branch instruction for processor with branching dependent on a specified bit in a register
US7437724B2 (en) 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
USRE41849E1 (en) 1999-12-22 2010-10-19 Intel Corporation Parallel multi-threaded processing
US8031612B2 (en) 2008-09-11 2011-10-04 Intel Corporation Altering operation of a network interface controller based on network traffic

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030095967A1 (en) * 1999-01-25 2003-05-22 Mackay Fabienne BAFF, inhibitors thereof and their use in the modulation of B-cell response and treatment of autoimmune disorders
US6606704B1 (en) * 1999-08-31 2003-08-12 Intel Corporation Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
US6694380B1 (en) 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US6661794B1 (en) 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US7480706B1 (en) 1999-12-30 2009-01-20 Intel Corporation Multi-threaded round-robin receive for fast network port
US6952824B1 (en) 1999-12-30 2005-10-04 Intel Corporation Multi-threaded sequenced receive for fast network port stream of packets
US7681018B2 (en) 2000-08-31 2010-03-16 Intel Corporation Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set
US7299470B2 (en) * 2001-09-13 2007-11-20 International Business Machines Corporation Method and system for regulating communication traffic using a limiter thread
US7895239B2 (en) 2002-01-04 2011-02-22 Intel Corporation Queue arrays in network devices
US7471688B2 (en) 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US7352769B2 (en) 2002-09-12 2008-04-01 Intel Corporation Multiple calendar schedule reservation structure and method
US7275247B2 (en) * 2002-09-19 2007-09-25 International Business Machines Corporation Method and apparatus for handling threads in a data processing system
US7433307B2 (en) 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US7233335B2 (en) * 2003-04-21 2007-06-19 Nividia Corporation System and method for reserving and managing memory spaces in a memory resource
US7443836B2 (en) 2003-06-16 2008-10-28 Intel Corporation Processing a data packet
JP4586526B2 (en) 2004-02-27 2010-11-24 ソニー株式会社 Information processing apparatus, information processing method, information processing system, and information processing program
JP2005276165A (en) * 2004-02-27 2005-10-06 Sony Corp Information processing apparatus, network system status presentation method, and computer program
US7418540B2 (en) * 2004-04-28 2008-08-26 Intel Corporation Memory controller with command queue look-ahead
CN100349142C (en) * 2004-05-25 2007-11-14 中国科学院计算技术研究所 Remote page access method for use in shared virtual memory system and network interface card
US20060067348A1 (en) * 2004-09-30 2006-03-30 Sanjeev Jain System and method for efficient memory access of queue control data structures
US7277990B2 (en) 2004-09-30 2007-10-02 Sanjeev Jain Method and apparatus providing efficient queue descriptor memory access
US7555630B2 (en) 2004-12-21 2009-06-30 Intel Corporation Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit
US7418543B2 (en) 2004-12-21 2008-08-26 Intel Corporation Processor having content addressable memory with command ordering
US20060140203A1 (en) * 2004-12-28 2006-06-29 Sanjeev Jain System and method for packet queuing
US7467256B2 (en) 2004-12-28 2008-12-16 Intel Corporation Processor having content addressable memory for block-based queue structures
DE102005026721A1 (en) * 2005-06-09 2007-01-11 Rohde & Schwarz Gmbh & Co. Kg Method for memory management of digital computing devices
US20070044103A1 (en) * 2005-07-25 2007-02-22 Mark Rosenbluth Inter-thread communication of lock protected data
US7853951B2 (en) * 2005-07-25 2010-12-14 Intel Corporation Lock sequencing to reorder and grant lock requests from multiple program threads
US20070124728A1 (en) * 2005-11-28 2007-05-31 Mark Rosenbluth Passing work between threads
US20070157030A1 (en) * 2005-12-30 2007-07-05 Feghali Wajdi K Cryptographic system component
US8051163B2 (en) * 2006-05-11 2011-11-01 Computer Associates Think, Inc. Synthetic transactions based on system history and load
US8407451B2 (en) * 2007-02-06 2013-03-26 International Business Machines Corporation Method and apparatus for enabling resource allocation identification at the instruction level in a processor system
US8819700B2 (en) * 2010-12-22 2014-08-26 Lsi Corporation System and method for synchronous inter-thread communication
US10725997B1 (en) * 2012-06-18 2020-07-28 EMC IP Holding Company LLC Method and systems for concurrent collection and generation of shared data
US9424027B2 (en) * 2013-07-29 2016-08-23 Ralph Moore Message management system for information transfer within a multitasking system
US9483272B2 (en) 2014-09-30 2016-11-01 Freescale Semiconductor, Inc. Systems and methods for managing return stacks in a multi-threaded data processing system
CN105868014A (en) * 2016-04-08 2016-08-17 京信通信技术(广州)有限公司 Memory optimization queuing method and system
US10901887B2 (en) * 2018-05-17 2021-01-26 International Business Machines Corporation Buffered freepointer management memory system
CN115712902B (en) * 2022-11-28 2026-04-17 国网山东省电力公司信息通信公司 Off-by-one vulnerability detection methods and systems for executable files

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0809180A2 (en) * 1996-05-22 1997-11-26 Seiko Epson Corporation Data processing circuit, microcomputer, and electronic equipment
US5905889A (en) * 1997-03-20 1999-05-18 International Business Machines Corporation Resource management system using next available integer from an integer pool and returning the integer thereto as the next available integer upon completion of use

Family Cites Families (104)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3373408A (en) * 1965-04-16 1968-03-12 Rca Corp Computer capable of switching between programs without storage and retrieval of the contents of operation registers
BE795789A (en) * 1972-03-08 1973-06-18 Burroughs Corp MICROPROGRAM CONTAINING A MICRO-RECOVERY INSTRUCTION
IT986411B (en) * 1973-06-05 1975-01-30 Olivetti E C Spa SYSTEM TO TRANSFER THE CONTROL OF PROCESSING FROM A FIRST PRIORITY LEVEL TO A SECOND PRIORITY LEVEL
US3889243A (en) * 1973-10-18 1975-06-10 Ibm Stack mechanism for a data processor
US4016548A (en) * 1975-04-11 1977-04-05 Sperry Rand Corporation Communication multiplexer module
CH584488A5 (en) * 1975-05-05 1977-01-31 Ibm
US4075691A (en) * 1975-11-06 1978-02-21 Bunker Ramo Corporation Communication control unit
JPS56164464A (en) * 1980-05-21 1981-12-17 Tatsuo Nogi Parallel processing computer
US4831358A (en) * 1982-12-21 1989-05-16 Texas Instruments Incorporated Communications system employing control line minimization
US4745544A (en) * 1985-12-12 1988-05-17 Texas Instruments Incorporated Master/slave sequencing processor with forced I/O
US5115507A (en) * 1987-12-23 1992-05-19 U.S. Philips Corp. System for management of the priorities of access to a memory and its application
FR2625340B1 (en) * 1987-12-23 1990-05-04 Labo Electronique Physique GRAPHIC SYSTEM WITH GRAPHIC CONTROLLER AND DRAM CONTROLLER
US5179702A (en) * 1989-12-29 1993-01-12 Supercomputer Systems Limited Partnership System and method for controlling a highly parallel multiprocessor using an anarchy based scheduler for parallel execution thread scheduling
DE69132495T2 (en) * 1990-03-16 2001-06-13 Texas Instruments Inc., Dallas Distributed processing memory
US5390329A (en) * 1990-06-11 1995-02-14 Cray Research, Inc. Responding to service requests using minimal system-side context in a multiprocessor environment
US5432918A (en) * 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
US5404482A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
KR960001273B1 (en) * 1991-04-30 1996-01-25 가부시키가이샤 도시바 Single chip microcomputer
US5623489A (en) * 1991-09-26 1997-04-22 Ipc Information Systems, Inc. Channel allocation system for distributed digital switching network
US5392412A (en) * 1991-10-03 1995-02-21 Standard Microsystems Corporation Data communication controller for use with a single-port data packet buffer
GB2260429B (en) * 1991-10-11 1995-05-24 Intel Corp Versatile cache memory
US5392391A (en) * 1991-10-18 1995-02-21 Lsi Logic Corporation High performance graphics applications controller
US5442797A (en) * 1991-12-04 1995-08-15 Casavant; Thomas L. Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
JP2823767B2 (en) * 1992-02-03 1998-11-11 松下電器産業株式会社 Register file
US5404484A (en) * 1992-09-16 1995-04-04 Hewlett-Packard Company Cache system for reducing memory latency times
US5617327A (en) * 1993-07-30 1997-04-01 Xilinx, Inc. Method for entering state flow diagrams using schematic editor programs
EP0617361B1 (en) * 1993-03-26 2001-11-28 Cabletron Systems, Inc. Scheduling method and apparatus for a communication network
US6311286B1 (en) * 1993-04-30 2001-10-30 Nec Corporation Symmetric multiprocessing system with unified environment and distributed system functions
CA2122182A1 (en) * 1993-05-20 1994-11-21 Rene Leblanc Method for rapid prototyping of programming problems
JPH0740746A (en) * 1993-07-29 1995-02-10 Aisin Seiki Co Ltd Vehicle sunroof device check mechanism
US5446736A (en) * 1993-10-07 1995-08-29 Ast Research, Inc. Method and apparatus for connecting a node to a wireless network using a standard protocol
US5740402A (en) * 1993-12-15 1998-04-14 Silicon Graphics, Inc. Conflict resolution in interleaved memory systems with multiple parallel accesses
US5490204A (en) * 1994-03-01 1996-02-06 Safco Corporation Automated quality assessment system for cellular networks
JP3547482B2 (en) * 1994-04-15 2004-07-28 株式会社日立製作所 Information processing equipment
US5542088A (en) * 1994-04-29 1996-07-30 Intergraph Corporation Method and apparatus for enabling control of task execution
US5721870A (en) * 1994-05-25 1998-02-24 Nec Corporation Lock control for a shared main storage data processing system
US5781774A (en) * 1994-06-29 1998-07-14 Intel Corporation Processor having operating modes for an upgradeable multiprocessor computer system
JP3810449B2 (en) * 1994-07-20 2006-08-16 富士通株式会社 Queue device
US5625812A (en) * 1994-11-14 1997-04-29 David; Michael M. Method of data structure extraction for computer systems operating under the ANSI-92 SQL2 outer join protocol
JP3169779B2 (en) * 1994-12-19 2001-05-28 日本電気株式会社 Multi-thread processor
US5784712A (en) * 1995-03-01 1998-07-21 Unisys Corporation Method and apparatus for locally generating addressing information for a memory access
US5649157A (en) * 1995-03-30 1997-07-15 Hewlett-Packard Co. Memory controller with priority queues
US5886992A (en) * 1995-04-14 1999-03-23 Valtion Teknillinen Tutkimuskeskus Frame synchronized ring system and method
US5758184A (en) * 1995-04-24 1998-05-26 Microsoft Corporation System for performing asynchronous file operations requested by runnable threads by processing completion messages with different queue thread and checking for completion by runnable threads
US5592622A (en) * 1995-05-10 1997-01-07 3Com Corporation Network intermediate system with message passing architecture
JPH08320797A (en) * 1995-05-24 1996-12-03 Fuji Xerox Co Ltd Program control system
US5613071A (en) * 1995-07-14 1997-03-18 Intel Corporation Method and apparatus for providing remote memory access in a distributed memory multiprocessor system
RU2170494C2 (en) * 1995-12-29 2001-07-10 Тикси. Ком ГмбХ Телекоммьюникейшн Системс Method and microcomputer system for safe and direct automatic data transmission
US6201807B1 (en) * 1996-02-27 2001-03-13 Lucent Technologies Real-time hardware method and apparatus for reducing queue processing
US5761507A (en) * 1996-03-05 1998-06-02 International Business Machines Corporation Client/server architecture supporting concurrent servers within a server with a transaction manager providing server/connection decoupling
US5764915A (en) * 1996-03-08 1998-06-09 International Business Machines Corporation Object-oriented communication interface for network protocol access using the selected newly created protocol interface object and newly created protocol layer objects in the protocol stack
US5784649A (en) * 1996-03-13 1998-07-21 Diamond Multimedia Systems, Inc. Multi-threaded FIFO pool buffer and bus transfer control system
US6199133B1 (en) * 1996-03-29 2001-03-06 Compaq Computer Corporation Management communication bus for networking devices
KR100219597B1 (en) * 1996-03-30 1999-09-01 윤종용 Queuing control method in cd-rom drive
US5946487A (en) * 1996-06-10 1999-08-31 Lsi Logic Corporation Object-oriented multi-media architecture
JP3541335B2 (en) * 1996-06-28 2004-07-07 富士通株式会社 Information processing apparatus and distributed processing control method
US6023742A (en) * 1996-07-18 2000-02-08 University Of Washington Reconfigurable computing architecture for providing pipelined data paths
US5745913A (en) * 1996-08-05 1998-04-28 Exponential Technology, Inc. Multi-processor DRAM controller that prioritizes row-miss requests to stale banks
US5928736A (en) * 1996-09-09 1999-07-27 Raytheon Company Composite structure having integrated aperture and method for its preparation
KR100417398B1 (en) * 1996-09-11 2004-04-03 엘지전자 주식회사 DS instruction block repetition processing
US6072781A (en) * 1996-10-22 2000-06-06 International Business Machines Corporation Multi-tasking adapter for parallel network applications
US5860158A (en) * 1996-11-15 1999-01-12 Samsung Electronics Company, Ltd. Cache control unit with a cache request transaction-oriented protocol
US5905876A (en) * 1996-12-16 1999-05-18 Intel Corporation Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system
US6212542B1 (en) * 1996-12-16 2001-04-03 International Business Machines Corporation Method and system for executing a program within a multiscalar processor by processing linked thread descriptors
US6256115B1 (en) * 1997-02-21 2001-07-03 Worldquest Network, Inc. Facsimile network
US5742587A (en) * 1997-02-28 1998-04-21 Lanart Corporation Load balancing port switching hub
US5898885A (en) * 1997-03-31 1999-04-27 International Business Machines Corporation Method and system for executing a non-native stack-based instruction within a computer system
US5918235A (en) * 1997-04-04 1999-06-29 Hewlett-Packard Company Object surrogate with active computation and probablistic counter
US6535878B1 (en) * 1997-05-02 2003-03-18 Roxio, Inc. Method and system for providing on-line interactivity over a server-client network
US6182177B1 (en) * 1997-06-13 2001-01-30 Intel Corporation Method and apparatus for maintaining one or more queues of elements such as commands using one or more token queues
US6092158A (en) * 1997-06-13 2000-07-18 Intel Corporation Method and apparatus for arbitrating between command streams
US6067585A (en) * 1997-06-23 2000-05-23 Compaq Computer Corporation Adaptive interface controller that can operate with segments of different protocol and transmission rates in a single integrated device
US5887134A (en) * 1997-06-30 1999-03-23 Sun Microsystems System and method for preserving message order while employing both programmed I/O and DMA operations
US6393483B1 (en) * 1997-06-30 2002-05-21 Adaptec, Inc. Method and apparatus for network interface card load balancing and port aggregation
US6247025B1 (en) * 1997-07-17 2001-06-12 International Business Machines Corporation Locking and unlocking mechanism for controlling concurrent access to objects
GB2327784B (en) * 1997-07-28 2002-04-03 Microapl Ltd A method of carrying out computer operations
US6170051B1 (en) * 1997-08-01 2001-01-02 Micron Technology, Inc. Apparatus and method for program level parallelism in a VLIW processor
WO1999009469A1 (en) * 1997-08-18 1999-02-25 Koninklijke Philips Electronics N.V. Stack oriented data processing device
US6014729A (en) * 1997-09-29 2000-01-11 Firstpass, Inc. Shared memory arbitration apparatus and method
US6085294A (en) * 1997-10-24 2000-07-04 Compaq Computer Corporation Distributed data dependency stall mechanism
US6061710A (en) * 1997-10-29 2000-05-09 International Business Machines Corporation Multithreaded processor incorporating a thread latch register for interrupt service new pending threads
US5915123A (en) * 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
EP0918280B1 (en) * 1997-11-19 2004-03-24 IMEC vzw System and method for context switching on predetermined interruption points
US6360262B1 (en) * 1997-11-24 2002-03-19 International Business Machines Corporation Mapping web server objects to TCP/IP ports
JPH11203860A (en) * 1998-01-07 1999-07-30 Nec Corp Semiconductor memory device
US6223238B1 (en) * 1998-03-31 2001-04-24 Micron Electronics, Inc. Method of peer-to-peer mastering over a computer bus
US6079008A (en) * 1998-04-03 2000-06-20 Patton Electronics Co. Multiple thread multiple data predictive coded parallel processing system and method
KR100280460B1 (en) * 1998-04-08 2001-02-01 김영환 Data processing device and its multiple thread processing method
US6092127A (en) * 1998-05-15 2000-07-18 Hewlett-Packard Company Dynamic allocation and reallocation of buffers in links of chained DMA operations by receiving notification of buffer full and maintaining a queue of buffers available
US6373848B1 (en) * 1998-07-28 2002-04-16 International Business Machines Corporation Architecture for a multi-port adapter with a single media access control (MAC)
US6073215A (en) * 1998-08-03 2000-06-06 Motorola, Inc. Data processing system having a data prefetch mechanism and method therefor
US6366998B1 (en) * 1998-10-14 2002-04-02 Conexant Systems, Inc. Reconfigurable functional units for implementing a hybrid VLIW-SIMD programming model
US6347344B1 (en) * 1998-10-14 2002-02-12 Hitachi, Ltd. Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor
US6212611B1 (en) * 1998-11-03 2001-04-03 Intel Corporation Method and apparatus for providing a pipelined memory controller
US6389449B1 (en) * 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US6338078B1 (en) * 1998-12-17 2002-01-08 International Business Machines Corporation System and method for sequencing packets for multiprocessor parallelization in a computer network system
US6356692B1 (en) * 1999-02-04 2002-03-12 Hitachi, Ltd. Optical module, transmitter, receiver, optical switch, optical communication unit, add-and-drop multiplexing unit, and method for manufacturing the optical module
US6529983B1 (en) * 1999-11-03 2003-03-04 Cisco Technology, Inc. Group and virtual locking mechanism for inter processor synchronization
US6532509B1 (en) * 1999-12-22 2003-03-11 Intel Corporation Arbitrating command requests in a parallel multi-threaded processing system
US6694380B1 (en) * 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US6324624B1 (en) * 1999-12-28 2001-11-27 Intel Corporation Read lock miss control and queue management
US6307789B1 (en) * 1999-12-28 2001-10-23 Intel Corporation Scratchpad memory
US6560667B1 (en) * 1999-12-28 2003-05-06 Intel Corporation Handling contiguous memory references in a multi-queue system
US6584522B1 (en) * 1999-12-30 2003-06-24 Intel Corporation Communication between processors

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0809180A2 (en) * 1996-05-22 1997-11-26 Seiko Epson Corporation Data processing circuit, microcomputer, and electronic equipment
US5905889A (en) * 1997-03-20 1999-05-18 International Business Machines Corporation Resource management system using next available integer from an integer pool and returning the integer thereto as the next available integer upon completion of use

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
HYDE R L: "Overview of memory management", BYTE, APRIL 1988, USA, vol. 13, no. 4, pages 219 - 225, XP002162801, ISSN: 0360-5280 *

Cited By (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7424579B2 (en) 1999-08-31 2008-09-09 Intel Corporation Memory controller for processor having multiple multithreaded programmable units
US7305500B2 (en) 1999-08-31 2007-12-04 Intel Corporation Sram controller for parallel processor architecture including a read queue and an order queue for handling requests
US6983350B1 (en) 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US7191321B2 (en) 1999-08-31 2007-03-13 Intel Corporation Microengine for parallel processor architecture
US7191309B1 (en) 1999-09-01 2007-03-13 Intel Corporation Double shift instruction for micro engine used in multithreaded parallel processor architecture
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
US7421572B1 (en) 1999-09-01 2008-09-02 Intel Corporation Branch instruction for processor with branching dependent on a specified bit in a register
USRE41849E1 (en) 1999-12-22 2010-10-19 Intel Corporation Parallel multi-threaded processing
US7111296B2 (en) 1999-12-28 2006-09-19 Intel Corporation Thread signaling in multi-threaded processor
US6876561B2 (en) 1999-12-28 2005-04-05 Intel Corporation Scratchpad memory
US7620702B1 (en) 1999-12-28 2009-11-17 Intel Corporation Providing real-time control data for a network processor
US6895457B2 (en) 1999-12-28 2005-05-17 Intel Corporation Bus interface with a first-in-first-out memory
US6976095B1 (en) 1999-12-30 2005-12-13 Intel Corporation Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch
US7328289B2 (en) 1999-12-30 2008-02-05 Intel Corporation Communication between processors
US7020871B2 (en) 2000-12-21 2006-03-28 Intel Corporation Breakpoint method for parallel hardware threads in multithreaded processor
US6868476B2 (en) 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7487505B2 (en) 2001-08-27 2009-02-03 Intel Corporation Multithreaded microprocessor with register allocation based on number of active threads
US7216204B2 (en) 2001-08-27 2007-05-08 Intel Corporation Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment
US7225281B2 (en) 2001-08-27 2007-05-29 Intel Corporation Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
US7246197B2 (en) 2001-08-27 2007-07-17 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
US7126952B2 (en) 2001-09-28 2006-10-24 Intel Corporation Multiprotocol decapsulation/encapsulation control structure and packet protocol conversion method
US7158964B2 (en) 2001-12-12 2007-01-02 Intel Corporation Queue management
US7107413B2 (en) 2001-12-17 2006-09-12 Intel Corporation Write queue descriptor count instruction for high speed queuing
US7269179B2 (en) 2001-12-18 2007-09-11 Intel Corporation Control mechanisms for enqueue and dequeue operations in a pipelined network processor
US7181573B2 (en) 2002-01-07 2007-02-20 Intel Corporation Queue array caching in network devices
US7302549B2 (en) 2002-01-17 2007-11-27 Intel Corporation Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access
US6934951B2 (en) 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
US7610451B2 (en) 2002-01-25 2009-10-27 Intel Corporation Data transfer mechanism using unidirectional pull bus and push bus
US7181594B2 (en) 2002-01-25 2007-02-20 Intel Corporation Context pipelines
US7149226B2 (en) 2002-02-01 2006-12-12 Intel Corporation Processing data packets
US7437724B2 (en) 2002-04-03 2008-10-14 Intel Corporation Registers for data transfers
US7337275B2 (en) 2002-08-13 2008-02-26 Intel Corporation Free list and ring data structure management
US7418571B2 (en) 2003-01-10 2008-08-26 Intel Corporation Memory interleaving
US6941438B2 (en) 2003-01-10 2005-09-06 Intel Corporation Memory interleaving
US7213099B2 (en) 2003-12-30 2007-05-01 Intel Corporation Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
US8031612B2 (en) 2008-09-11 2011-10-04 Intel Corporation Altering operation of a network interface controller based on network traffic

Also Published As

Publication number Publication date
DE60015395T2 (en) 2005-11-10
ATE280972T1 (en) 2004-11-15
SG149673A1 (en) 2009-02-27
CN1253784C (en) 2006-04-26
US20040039895A1 (en) 2004-02-26
HK1046180B (en) 2005-05-13
EP1247168A2 (en) 2002-10-09
AU2280101A (en) 2001-07-16
CN1451114A (en) 2003-10-22
WO2001050247A2 (en) 2001-07-12
EP1247168B1 (en) 2004-10-27
HK1046180A1 (en) 2002-12-27
DE60015395D1 (en) 2004-12-02
TWI222011B (en) 2004-10-11
US6631462B1 (en) 2003-10-07

Similar Documents

Publication Publication Date Title
WO2001050247A3 (en) Memory shared between processing threads
WO2003073580A3 (en) Processing system for a power distribution system
AUPR174800A0 (en) Semiconductor processing
AU2001229574A1 (en) Split embedded dram processor
AU2003263742A1 (en) Currency processing and strapping systems and methods for using the same
AU2000257476A1 (en) Recipe cascading in a wafer processing system
AU2001283991A1 (en) Data processing system
WO2002071246A3 (en) An apparatus for controlling access in a data processor
AU3678500A (en) Semi-optimal path finding in a wholly unknown environment
AU2001287141A1 (en) Semiconductor device and process for forming the same
AU2001241521A1 (en) Wafer processing system
AU2001229505A1 (en) Establishing thread priority in a processor or the like
AU5021300A (en) Structured finance performance analytics system
AU4330796A (en) Anti-neurodegeneratively active 10-aminoaliphatyl-dibenz(b,f)oxepines
AU2001259184A1 (en) Authenticating and securing data originating from a storage and processing device
AU3241499A (en) Paper stack handler
WO2001075815A3 (en) Card terminal and method for operating a card terminal
AU2001271218A1 (en) Method and arrangement for identifying and processing commands in digital images, where the user marks the command, for example by encircling it
AU1975400A (en) An arrangement and method for the transport, storage and processing of hydrocarbons
AU5308400A (en) System and method for creating, completing, processing and storing surveys and the results thereof over a network
USD417289S (en) Arbor
AU2001246758A1 (en) A magnetic film having a magnetic easy-axis or a multiple easy-axis and a methodof manufacturing the magnetic film
AU1552401A (en) Image processor, image processing method, and storage medium
AU2002212761A1 (en) External storage unit, and information processing unit having the unit
WO2001093313A3 (en) Developing methods for photoresist, apparatuses for coating

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG US UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 2000986590

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 008192847

Country of ref document: CN

WWP Wipo information: published in national office

Ref document number: 2000986590

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: JP

WWG Wipo information: grant in national office

Ref document number: 2000986590

Country of ref document: EP