WO2001052184A3 - Chipkartenanordnung - Google Patents

Chipkartenanordnung Download PDF

Info

Publication number
WO2001052184A3
WO2001052184A3 PCT/DE2000/004634 DE0004634W WO0152184A3 WO 2001052184 A3 WO2001052184 A3 WO 2001052184A3 DE 0004634 W DE0004634 W DE 0004634W WO 0152184 A3 WO0152184 A3 WO 0152184A3
Authority
WO
WIPO (PCT)
Prior art keywords
chipcard
arrangement
electrically conducting
chips
semiconductor chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/DE2000/004634
Other languages
English (en)
French (fr)
Other versions
WO2001052184A2 (de
Inventor
Andreas Kux
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE50005564T priority Critical patent/DE50005564D1/de
Priority to AT00991117T priority patent/ATE261151T1/de
Priority to EP00991117A priority patent/EP1247250B1/de
Publication of WO2001052184A2 publication Critical patent/WO2001052184A2/de
Publication of WO2001052184A3 publication Critical patent/WO2001052184A3/de
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/072—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising a plurality of integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07372—Means for preventing undesired reading or writing from or onto record carriers by detecting tampering with the circuit
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • General Engineering & Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Chipkartenanordnung mit einem kartenförmigen Träger, in dem eine Ausnehmung vorgesehen ist, in der zumindest zwei übereinanderliegende Halbleiterchips (4, 5) angeordnet sind, die miteinander über elektrisch leitende Verbindungen elektrische Signale und/oder Energie austauschen, wobei die zumindest zwei Halbleiterchips (4, 5) zusammen eine Mindestgröße von 20 bis 25 mm aufweisen und die elektrisch leitende Verbindung mittels einer dreidimensionalen Verdrahtung in dem Halbleiterchip realisiert ist.
PCT/DE2000/004634 2000-01-11 2000-12-27 Chipkartenanordnung Ceased WO2001052184A2 (de)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE50005564T DE50005564D1 (de) 2000-01-11 2000-12-27 Chipkartenanordnung
AT00991117T ATE261151T1 (de) 2000-01-11 2000-12-27 Chipkartenanordnung
EP00991117A EP1247250B1 (de) 2000-01-11 2000-12-27 Chipkartenanordnung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP00100507 2000-01-11
EP00100507.3 2000-01-11

Publications (2)

Publication Number Publication Date
WO2001052184A2 WO2001052184A2 (de) 2001-07-19
WO2001052184A3 true WO2001052184A3 (de) 2002-02-07

Family

ID=8167601

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE2000/004634 Ceased WO2001052184A2 (de) 2000-01-11 2000-12-27 Chipkartenanordnung

Country Status (4)

Country Link
EP (1) EP1247250B1 (de)
AT (1) ATE261151T1 (de)
DE (1) DE50005564D1 (de)
WO (1) WO2001052184A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10244446B4 (de) * 2002-09-24 2004-08-19 Infineon Technologies Ag Halbleiterchipstapel
US8232621B2 (en) 2006-07-28 2012-07-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7714535B2 (en) 2006-07-28 2010-05-11 Semiconductor Energy Laboratory Co., Ltd. Power storage device
US7838976B2 (en) 2006-07-28 2010-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having a semiconductor chip enclosed by a body structure and a base
DE102010028926A1 (de) * 2010-05-12 2011-11-17 Bundesdruckerei Gmbh Dokument und Verfahren zur Herstellung eines Dokuments
EP3168787A1 (de) 2015-11-11 2017-05-17 Mastercard International Incorporated Chipkarte
EP3168788A1 (de) 2015-11-11 2017-05-17 Mastercard International Incorporated Chipkarte

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994025982A1 (de) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Kontaktstrukturierung für vertikale chipverbindungen
DE19511775C1 (de) * 1995-03-30 1996-10-17 Siemens Ag Trägermodul, insb. zum Einbau in einen kartenförmigen Datenträger, mit Schutz gegen die Untersuchung geheimer Bestandteile
DE19702121C1 (de) * 1997-01-22 1998-06-18 Siemens Ag Verfahren zur Herstellung von vertikalen Chipverbindungen
DE19735170A1 (de) * 1997-08-13 1998-09-10 Siemens Ag Chipmodul, insbesondere für kontaktbehaftete Chipkarten, mit nebeneinander angeordneten Chips

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994025982A1 (de) * 1993-05-05 1994-11-10 Siemens Aktiengesellschaft Kontaktstrukturierung für vertikale chipverbindungen
DE19511775C1 (de) * 1995-03-30 1996-10-17 Siemens Ag Trägermodul, insb. zum Einbau in einen kartenförmigen Datenträger, mit Schutz gegen die Untersuchung geheimer Bestandteile
DE19702121C1 (de) * 1997-01-22 1998-06-18 Siemens Ag Verfahren zur Herstellung von vertikalen Chipverbindungen
DE19735170A1 (de) * 1997-08-13 1998-09-10 Siemens Ag Chipmodul, insbesondere für kontaktbehaftete Chipkarten, mit nebeneinander angeordneten Chips

Also Published As

Publication number Publication date
DE50005564D1 (de) 2004-04-08
WO2001052184A2 (de) 2001-07-19
EP1247250B1 (de) 2004-03-03
EP1247250A2 (de) 2002-10-09
ATE261151T1 (de) 2004-03-15

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