WO2001084327A3 - Gigabit switch on chip architecture - Google Patents

Gigabit switch on chip architecture Download PDF

Info

Publication number
WO2001084327A3
WO2001084327A3 PCT/US2001/013196 US0113196W WO0184327A3 WO 2001084327 A3 WO2001084327 A3 WO 2001084327A3 US 0113196 W US0113196 W US 0113196W WO 0184327 A3 WO0184327 A3 WO 0184327A3
Authority
WO
WIPO (PCT)
Prior art keywords
data
data port
port interface
interface
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/013196
Other languages
French (fr)
Other versions
WO2001084327A2 (en
Inventor
Govind Malalur
Shiri Kadambi
Shekhar Ambe
Mohan Kalkunte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Priority to DE60120684T priority Critical patent/DE60120684T2/en
Priority to EP01927326A priority patent/EP1279102B1/en
Priority to AU2001253789A priority patent/AU2001253789A1/en
Publication of WO2001084327A2 publication Critical patent/WO2001084327A2/en
Publication of WO2001084327A3 publication Critical patent/WO2001084327A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Electronic Switches (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Optical Communication System (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)

Abstract

A data switch for network communications includes a first data port interface which supports at least one data port which transmits and receives data. A second data port interface is also provided supporting at least one data port transmitting and receiving data. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. A common memory is provided, and communicates with the first data port interface and the second data port interface. A memory management unit is provided, and communicates data from the first data port interface and the second data port interface and a common memory. At least two sets of communication channels are provided, with each of the communication channels communicating data and messaging information between the first data port interface, the second data port interface, and the memory management unit.
PCT/US2001/013196 2000-05-03 2001-04-25 Gigabit switch on chip architecture Ceased WO2001084327A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE60120684T DE60120684T2 (en) 2000-05-03 2001-04-25 Architecture for built-in gigabit switching
EP01927326A EP1279102B1 (en) 2000-05-03 2001-04-25 Gigabit switch on chip architecture
AU2001253789A AU2001253789A1 (en) 2000-05-03 2001-04-25 Gigabit switch on chip architecture

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US20168500P 2000-05-03 2000-05-03
US60/201,685 2000-05-03

Publications (2)

Publication Number Publication Date
WO2001084327A2 WO2001084327A2 (en) 2001-11-08
WO2001084327A3 true WO2001084327A3 (en) 2002-04-25

Family

ID=22746865

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/013196 Ceased WO2001084327A2 (en) 2000-05-03 2001-04-25 Gigabit switch on chip architecture

Country Status (5)

Country Link
EP (1) EP1279102B1 (en)
AT (1) ATE330282T1 (en)
AU (1) AU2001253789A1 (en)
DE (1) DE60120684T2 (en)
WO (1) WO2001084327A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN121051052B (en) * 2025-10-31 2026-01-27 苏州元脑智能科技有限公司 Bus interconnection system, signal processing method and server

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999000936A1 (en) * 1997-06-30 1999-01-07 Sun Microsystems, Inc. A highly integrated multi-layer switch element architecture

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999000936A1 (en) * 1997-06-30 1999-01-07 Sun Microsystems, Inc. A highly integrated multi-layer switch element architecture

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LEVEL ONE: "Level One(TM) IXP1200 Network Processor", ADVANCE DATASHEET, September 1999 (1999-09-01), pages 1 - 52, XP002187948, Retrieved from the Internet <URL:http://www.cs.utah.edu/~cs6935/Previous/s01/netprocs/ixa/ixp1200ad.pdf> [retrieved on 20020121] *

Also Published As

Publication number Publication date
DE60120684T2 (en) 2007-06-14
ATE330282T1 (en) 2006-07-15
WO2001084327A2 (en) 2001-11-08
EP1279102A2 (en) 2003-01-29
AU2001253789A1 (en) 2001-11-12
EP1279102B1 (en) 2006-06-14
DE60120684D1 (en) 2006-07-27

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