WO2001091281A2

WO2001091281A2 - Level shifter for switching power amplifier

Info

Publication number: WO2001091281A2
Application number: PCT/EP2001/004996
Authority: WO
Inventors: Marco Berkhout
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2000-05-25
Filing date: 2001-05-03
Publication date: 2001-11-29
Anticipated expiration: 2002-11-25
Also published as: EP1293035A2; KR20020056878A; KR100762533B1; WO2001091281A3; ES2284656T3; EP1293035B1; US6476672B2; ATE359617T1; DE60127835D1; DE60127835T2; US20020000878A1; JP2003534690A

Abstract

The invention relates to a push-pull amplifier having a level shift circuit to generate different control signals to a driver of a switch. The amplifier has to cope with the voltage limitations of the device. To reduce standby power the level shifter is used. The solution of the invention has as one of the great advantages that only during transitions a current will flow.

Description

Level shifter

The invention relates to a push-pull amplifier as described in the preamble of claim 1. The invention further relates to a level shift circuit for use in such a push-pull amplifier. The invention further relates to a method of level shifting signals.

From the "Proceedings of the IEEE 1995 Custom Integrated Circuits Conference May 1-4, 1995" a push-pull amplifier is known. One of the items of class D amplifier is that the class D amplifier has the cope with the voltage limitations of the device. To reduce standby power dissipation herein a level shifter is proposed.

A disadvantage of this known push-pull amplifier and level shift circuit is that the herein-proposed solution can only be used with complementary power transistors.

It is an object of the invention to propose a push-pull amplifier and a level shift circuit, which not have the disadvantages of the known. To this end a class D amplifier according to the invention comprises the features as claimed in claim 1. One of the great advantages of a push-pull amplifier according to the invention is that this push-pull amplifier has a very low current consumption. This is achieved because only during transitions a current will flow.

Embodiments of the invention are described in the dependent claims.

Herewith a cross-reference is made to the following co-pending applications of the same applicant and of the same date:

"Carrousel handshake" applicant's ref. Nr. ID603908, Application No. 0 201 818.2

"Silent start" applicant's ref. Nr. ID604681, Application No. 0 201 827.3 "PWM limiter" applicant's ref. Nr. ID604682, Application No. 0 201 828.1 "Demodulation filter" applicant's ref. Nr. ID604683, Application No. 0 201 829.9.

These and other aspects of the invention will be apparent from and elucidated with reference to the examples described hereinafter. Herein shows:

Figure 1 schematically an example of a push-pull amplifier, Figure 2 a circuit with pull down and pull up transistors, Figure 3 a three phase level shift circuit, Figure 4 a state transition diagram, Figure 5 a basic four stroke level shift and ledge circuit

Figure 6 a second example of a four-stroke level shift circuit.

Figure 1 shows block-schematic an example of a push-pull amplifier PPA according to the invention. Via an input unit IU the amplifier receives the input signal. The input unit is coupled to a pulse- width modulator PWM, which is coupled with an output to a switching unit SU. The switching unit supplies an output signal via a demodulation filter DF to the output O of the amplifier. The pulse- width modulator is coupled in a feedback loop with a feedback element RF that is coupled with one side to the output of the switching unit SU and with the other side to the input of the pulse- width modulator. The pulse- width modulator further comprises a first integrator Fl and a second integrator SI and a comparator COM, the input of the first integrator is coupled to the output of the input unit IU and the input of the second integrator is coupled to an output of the first integrator Fl and also coupled to an oscillator OSC.

Instead of two integrators it is also possible to use only one integrator. At the inverting input of the comparator for example a saw tooth signal can be supplied.

The switching unit SU comprises a switch control unit SCU and a first and second switch SW1, SW2, respectively. The demodulation filter is in this example shown as an inductance L and a capacitance C can be a second order low-pass demodulation filter, or higher order demodulation filter.

In order to be robust against process and temperature variations it is undesirable to let the timing of the switching be determined by on-chip timeconstants. Therefore, it has been decided to use a handshake procedure to control the switch timing. A circuit is added to both lowside and highside switch that generates a ready signal if the corresponding switch is off. The state of the switch can easily be detected by measuring the gate-source voltage of the DMOS transistor. If it is lower than the threshold voltage the switch is off, if it is higher than the threshold voltage the switch is on. In practice the exact decision level is not very critical. Due to the latch in the driver, the gate-source voltage is either at ON or at 12N while the transitions between these two levels are very fast.

The handshake procedure forces a specific sequence in which the set and reset signals are generated. To illustrate this, consider the situation that the output of the switching unit is in the low position, i.e. the lowside switch is on and the highside switch is off. In this situation the readylow, resetlow and sethigh signals are low while the readyhigh and resethigh signals are high (I). The value of the setlow signal is not important since the lowside switch has already been set so it will be assumed low. In this situation the handshake logic waits for a transition at the input in. Now the following sequence of events will take place. First, the resetlow signal goes high (II) and the resethigh signal goes low (III). These events can also take place at the same time but for safety an overlap of reset signals is preferred. Following the resetlow signal the lowside switch switches off, the highside driver was already reset, removing the resethigh signal does not affect the highside. When the lowside switch is off the readylow signal will go high. As soon as this happens the sethigh signal goes high (IN). Following sethigh the highside switch switches on. When the highside switch is on the readyhigh signal will go low. As soon as this happens the sethigh signal can be made low again (N). Now the output of the switching unit is in the high position. The transition back to the low position is executed in a similar manner.

In general pull-down transistors are capable of pulling down a node on a higher level almost instantaneously. Pulling down the node back up again can only be done fast indirectly with a "pull-up" transistor as illustrated in figure 2.

In both situations a current source is required to recover to the original situation.

Fast recovery requires large currents. The use of the continuous current sources is undesirable since then these (large) currents flow through the pull down and shutter transistors continuously. Switching of the current sources by cross coupling the circuits results in a regenerative loop, which exhibits the undesired delay described earlier. The regenerative loop can easily be broken by adding a third signal. Consider the situation shown in figure 3. Three signals Φ_ls Φ₂ and Φ₃ are sequentially high. If Φi i_s high it pulls down node Ni directly through shutter M₂ and pulls up node N₃ indirectly through pull-up M₉. This switches off pull-up M₆ and leaves N₂ floating (high). Next Φ₂ goes high, pulls down N₂, pulls up Ni and switches off M₉. Next Φ₃ goes high, etc. in this circuit each pull-up transistor is switched off before the corresponding pull-down transistor is switched on and vice versa.

The circuit of figure 3 can also be realized in a four-phase version. Although this seems to be unpractical it starts to make sense when it is considered that the reset signals for the latch are generated by the carrousel described above.

The set and reset signals are generated in a predefined sequence by a state machine. It is easy to decode some additional signals in order to drive a four phase level shift as shown in the, state transition diagram in figure 4.

These additional signals essentially serve to prepare the driver latch for a set or a reset signal. The actual thing can be done with pull-up transistors.

The main problem in implementing the system (push-pull amplifier) described previously is the transfer of signals between the carrousel and the highside driver. The binary signals in the carrousel are between the N_ss and N_stabi rails while the binary signals in the highside driver are between the N_out and N_b00t rails where N_out equals N_ss or N_dd or is in a steep transient between these two levels. Clearly the transfer of the set and reset signals from carrousel to highside driver and ready signal from highside driver to carrousel has to e insensitive to the voltage transient at the output of the switching unit.

The use of continuous current sources is undesirable since then these (large) currents flow through the pulldown and shutter transistors continuously. Switching of the current sources by cross-coupling the circuits results in a regenerative loop which exhibits the undesired delay described earlier. The regenerative loop can easily be broken by adding a third signal. Consider the situation shown in figure 3. Three signals φi, φ₂ and φ₃ are sequentially high. If φt is high it pulls down node Νi directly through shutter M₂ and pulls up node Ν₃ indirectly through pull-up M₉. This switches off pull-up M₆ and leaves N₂ floating (high). Next φ₂ goes high, pulls down N₂, pulls up Ni and switches off M₉. Next φ₃ goes high, etc. In this circuit each pull-up transistor is switched off before the corresponding pull-down transistor is switched on and vice versa. Obviously, the circuit in figure 3 can also be realized in a four-phase version. Although this seems to be unpractical it starts to make sense when it is considered that the set and reset signals for the latch are generated by the carrousel described in the previous section. The set and reset signals are generated by the carrousel described in the previous section. The set and reset signals are generated in a predefined sequence by a state machine. It is very easy to decode some additional signals in order to drive a four-phase level shift as shown in the state transition diagram in Figure 4.

The resulting circuit is shown in figure 5 and is called the four-stroke. The name four-stroke is derived from the superficial similarity with the four phases of operation of a four-stroke combustion engine. If the set signal is high the gate of pull-up transistor M₅ is pulled down and the latch is set. Then the discharge signal goes high and the gate of M₅ is pulled up again indirectly. Next the reset signal goes high and pulls down the gate of M₆, which resets the latch. Finally, the precharge signal pulls up the gate of M₆ again.

In general, if one of the signals driving the four-stroke is high, the corresponding node is pulled down, the adjacent node is pulled up while the two remaining nodes are floating and thus susceptible to capacitive coupling or leakage currents. Although this is generally undesirable it can cause problems in two cases in particular.

First, as long as the switching unit is disabled, both highside and lowside driver remain reset indefinitely. In this case the gate of M₉ is floating and can assume any voltage. Consequently M₉ may be turned on resulting in a resistive channel between N_boot and

V_ss. Second, consider the following situation. The carrousel is in state 110 while the output of the switching unit is on the lowside. When the carrousel progresses to state 111 the resethigh signal goes low while the prechargehigh signal goes high, pulling down the gate of M₉ and thus indirectly pulling up the gate of M₆. Next, after readylow confirmation the carrousel progresses to state 101. Consequently the prechargehigh signal goes low while the sethigh signal goes high pulling down the gates of M₅ and M₈ and indirectly pulling up the gate of M leaving the gate of M₆ floating. Because the latch is now set, the output of the switching unit will make a fast transition to the highside. Because of parasitic capacitance it is now possible that the gate of M₆ is pulled down thus opening M₆ is pulled down thus opening M₆ which counteracts the set effect of M₅. Both problems can be solved by additional pull-up transistors as shown in figure 6. As can be seen in figure both set band reset signals cause all other nodes to be pulled-up. Note that transistors M₁ and Mπ counteract the operation of M and M respectively. In order not to re-create the original problem M₁₄ and Mπ should be made much smaller than M₇ and M₉. Transistors M₁₃ and M₁₂ do not influence the switching speed since they are not used to switch but only to maintain the present state.

Claims

CLAIMS:

1. Push-pull amplifier having an input for receiving an input signal and an output for supplying an output signal, which push-pull amplifier comprises a pulse width modulator comprising at least two integrators, a comparator and a feed back element, switching unit having at least two switches coupled to the output of the pulse width modulator and a demodulator filter coupled to the output of the switching unit characterized in that a switching unit comprises a four phase level shift circuit for generating four different control signals to at least one driver of at least one switch.

2. Push-pull amplifier as claimed in claim 1 characterized in that the push-pull amplifier is class D amplifier.

3. Level shift circuit for use in a push-pull amplifier as claimed in claim 1.

4. Method of level shifting comprising the steps of generating different control signals to a driver of a switch.