WO2001099152A3 - Buried bit line-field plate isolation defined dram cell active areas - Google Patents

Buried bit line-field plate isolation defined dram cell active areas Download PDF

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Publication number
WO2001099152A3
WO2001099152A3 PCT/US2001/019813 US0119813W WO0199152A3 WO 2001099152 A3 WO2001099152 A3 WO 2001099152A3 US 0119813 W US0119813 W US 0119813W WO 0199152 A3 WO0199152 A3 WO 0199152A3
Authority
WO
WIPO (PCT)
Prior art keywords
bit line
semiconductor substrate
buried bit
field plate
active areas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/019813
Other languages
French (fr)
Other versions
WO2001099152A2 (en
Inventor
Michael Stetter
Frank Grellner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Infineon Technologies North America Corp
Original Assignee
International Business Machines Corp
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp, Infineon Technologies North America Corp filed Critical International Business Machines Corp
Priority to EP01946612A priority Critical patent/EP1292967A2/en
Publication of WO2001099152A2 publication Critical patent/WO2001099152A2/en
Publication of WO2001099152A3 publication Critical patent/WO2001099152A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/905—Plural dram cells share common contact or common trench
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/907—Folded bit line dram configuration

Landscapes

  • Semiconductor Memories (AREA)

Abstract

Active areas (24A,24B) of a Dynamic Random Access Memory (DRAM) formed on a semiconductor substrate are defined by buried bit lines (BL1, BL2, BL3) on two sides and by conductors (20) separated from the semiconductor substrate by electrically insulating layers (22) on two other sides. The conductors are electrically biased during operation of the DRAM to cause portions of the semiconductor substrate therebelow to increase in majority carrier concentration and thus to inhibit inversion therof, commonly known as field plate insulation. Each buried bit line is formed in a trench (14) in the semiconductor substrate. Each trench houses a separate bit line and is lined with an electrical insulator (16) and has a conductor (18A) in a bottom portion thereof. Common drain regions (23A) shared by two transistors are coupled to conductors (18A) by means of a conductor (32).
PCT/US2001/019813 2000-06-21 2001-06-21 Buried bit line-field plate isolation defined dram cell active areas Ceased WO2001099152A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP01946612A EP1292967A2 (en) 2000-06-21 2001-06-21 Buried bit line-field plate isolation defined dram cell active areas

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/598,789 2000-06-21
US09/598,789 US6911687B1 (en) 2000-06-21 2000-06-21 Buried bit line-field isolation defined active semiconductor areas

Publications (2)

Publication Number Publication Date
WO2001099152A2 WO2001099152A2 (en) 2001-12-27
WO2001099152A3 true WO2001099152A3 (en) 2002-04-04

Family

ID=24396923

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/019813 Ceased WO2001099152A2 (en) 2000-06-21 2001-06-21 Buried bit line-field plate isolation defined dram cell active areas

Country Status (4)

Country Link
US (1) US6911687B1 (en)
EP (1) EP1292967A2 (en)
TW (1) TW531850B (en)
WO (1) WO2001099152A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10240436C1 (en) * 2002-09-02 2003-12-18 Infineon Technologies Ag Bit line structure comprises a surface bit line, a trenched bit line, a trench isolation layer, a covering isolation layer, covering connecting layers, and self-adjusting connecting layers
DE10321739A1 (en) 2003-05-14 2004-12-09 Infineon Technologies Ag Bit line structure and method for its production
JP2005032991A (en) * 2003-07-14 2005-02-03 Renesas Technology Corp Semiconductor device
US8412706B2 (en) * 2004-09-15 2013-04-02 Within3, Inc. Social network analysis
US8880521B2 (en) * 2004-09-15 2014-11-04 3Degrees Llc Collections of linked databases
US10395326B2 (en) * 2005-11-15 2019-08-27 3Degrees Llc Collections of linked databases
US7485905B2 (en) * 2006-07-25 2009-02-03 Taiwan Semiconductor Manufacturing Co., Ltd. Electrostatic discharge protection device
US20110042722A1 (en) * 2009-08-21 2011-02-24 Nanya Technology Corp. Integrated circuit structure and memory array
TWI691051B (en) * 2019-05-02 2020-04-11 力晶積成電子製造股份有限公司 Memory structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045899A (en) * 1989-12-01 1991-09-03 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory having stacked capacitor structure
EP0444615A1 (en) * 1990-02-26 1991-09-04 Kabushiki Kaisha Toshiba Dynamic random access memory having bit lines buried in semiconductor substrate
JPH07326678A (en) * 1994-05-30 1995-12-12 Nec Corp Semiconductor device having buried wiring and its manufacture
JPH08125144A (en) * 1994-10-21 1996-05-17 Nec Corp Semiconductor memory and fabrication thereof
US5792686A (en) * 1995-08-04 1998-08-11 Mosel Vitelic, Inc. Method of forming a bit-line and a capacitor structure in an integrated circuit
WO1998048460A1 (en) * 1997-04-22 1998-10-29 Micron Technology, Inc. Memory integrated circuitry

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5585285A (en) * 1995-12-06 1996-12-17 Micron Technology, Inc. Method of forming dynamic random access memory circuitry using SOI and isolation trenches
US5793075A (en) * 1996-07-30 1998-08-11 International Business Machines Corporation Deep trench cell capacitor with inverting counter electrode
US5892707A (en) 1997-04-25 1999-04-06 Micron Technology, Inc. Memory array having a digit line buried in an isolation region and method for forming same
US5981332A (en) 1997-09-30 1999-11-09 Siemens Aktiengesellschaft Reduced parasitic leakage in semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5045899A (en) * 1989-12-01 1991-09-03 Mitsubishi Denki Kabushiki Kaisha Dynamic random access memory having stacked capacitor structure
EP0444615A1 (en) * 1990-02-26 1991-09-04 Kabushiki Kaisha Toshiba Dynamic random access memory having bit lines buried in semiconductor substrate
JPH07326678A (en) * 1994-05-30 1995-12-12 Nec Corp Semiconductor device having buried wiring and its manufacture
JPH08125144A (en) * 1994-10-21 1996-05-17 Nec Corp Semiconductor memory and fabrication thereof
US5792686A (en) * 1995-08-04 1998-08-11 Mosel Vitelic, Inc. Method of forming a bit-line and a capacitor structure in an integrated circuit
WO1998048460A1 (en) * 1997-04-22 1998-10-29 Micron Technology, Inc. Memory integrated circuitry

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 04 30 April 1996 (1996-04-30) *
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 09 30 September 1996 (1996-09-30) *

Also Published As

Publication number Publication date
EP1292967A2 (en) 2003-03-19
TW531850B (en) 2003-05-11
US6911687B1 (en) 2005-06-28
WO2001099152A2 (en) 2001-12-27

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