WO2002008964A3 - Integrierter schaltkreis - Google Patents

Integrierter schaltkreis Download PDF

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Publication number
WO2002008964A3
WO2002008964A3 PCT/EP2001/008534 EP0108534W WO0208964A3 WO 2002008964 A3 WO2002008964 A3 WO 2002008964A3 EP 0108534 W EP0108534 W EP 0108534W WO 0208964 A3 WO0208964 A3 WO 0208964A3
Authority
WO
WIPO (PCT)
Prior art keywords
cells
integrated circuit
connections
cell
types
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2001/008534
Other languages
English (en)
French (fr)
Other versions
WO2002008964A2 (de
Inventor
Martin Vorbach
Armin Nueckel
Volker Baumgarte
Gerd Ehlers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pact Informationstechnologie GmbH
Original Assignee
Pact Informationstechnologie GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10036627A external-priority patent/DE10036627A1/de
Priority claimed from PCT/EP2001/006703 external-priority patent/WO2002013000A2/de
Priority to AU2001289737A priority Critical patent/AU2001289737A1/en
Priority to EP01969493A priority patent/EP1377919A2/de
Application filed by Pact Informationstechnologie GmbH filed Critical Pact Informationstechnologie GmbH
Publication of WO2002008964A2 publication Critical patent/WO2002008964A2/de
Priority to US10/469,910 priority patent/US20070299993A1/en
Priority to JP2002570103A priority patent/JP2004535613A/ja
Priority to JP2002570052A priority patent/JP4011488B2/ja
Priority to EP02724198.3A priority patent/EP1386220B1/de
Priority to EP02727358A priority patent/EP1540507B1/de
Priority to PCT/EP2002/002403 priority patent/WO2002071249A2/de
Priority to US10/471,061 priority patent/US7581076B2/en
Priority to AU2002257615A priority patent/AU2002257615A1/en
Priority to EP02712937A priority patent/EP1454258A2/de
Priority to JP2002570104A priority patent/JP2004536373A/ja
Priority to PCT/EP2002/002402 priority patent/WO2002071196A2/de
Priority to AU2002254921A priority patent/AU2002254921A1/en
Priority to PCT/EP2002/002398 priority patent/WO2002071248A2/de
Priority claimed from DE10129237A external-priority patent/DE10129237A1/de
Anticipated expiration legal-status Critical
Publication of WO2002008964A3 publication Critical patent/WO2002008964A3/de
Priority to JP2008249116A priority patent/JP2009043276A/ja
Priority to JP2008249106A priority patent/JP2009054170A/ja
Priority to JP2008249115A priority patent/JP2009043275A/ja
Priority to JP2008249099A priority patent/JP2009032281A/ja
Priority to JP2008249112A priority patent/JP2009020909A/ja
Priority to US12/496,012 priority patent/US20090300262A1/en
Priority to US12/944,068 priority patent/US9037807B2/en
Priority to US13/043,102 priority patent/US20110173389A1/en
Priority to US13/653,639 priority patent/US9075605B2/en
Priority to US14/219,945 priority patent/US9552047B2/en
Priority to US14/231,358 priority patent/US9436631B2/en
Priority to US14/318,211 priority patent/US9250908B2/en
Priority to US14/500,618 priority patent/US9141390B2/en
Priority to US15/225,638 priority patent/US10152320B2/en
Priority to US15/408,358 priority patent/US10331194B2/en
Priority to US16/190,931 priority patent/US20190102173A1/en
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Die Erfindung betrifft einen integrierten Schaltkreis mit mehreren, einander benachbarten Zellen, wobei wenigstens zwei Arten von Zellen vorgesehen sind, welche Anschlüsse aufweisen. Hierbei ist vorgesehen, dass die Zellen eine zur Integration einer Vielzahl logischer Elemente ausreichende Grösse aufweisen, wobei zumindest an einigen der Zellen zumindest ein logisches Element programmierbar ist und die Anschlüsse an zumindest im wesentlichen übereinstimmenden Positionen der Zelle vorgesehen sind, um so eine Zellartendurchmischung bei der benachbarten Anordnung der Zellen zu erlauben.
PCT/EP2001/008534 2000-07-24 2001-07-24 Integrierter schaltkreis Ceased WO2002008964A2 (de)

Priority Applications (31)

Application Number Priority Date Filing Date Title
AU2001289737A AU2001289737A1 (en) 2000-07-24 2001-07-24 Integrated circuit
EP01969493A EP1377919A2 (de) 2000-07-24 2001-07-24 Integrierter schaltkreis
PCT/EP2002/002402 WO2002071196A2 (de) 2001-03-05 2002-03-05 Verfahren und vorrichtung zu datenbe- und/oder verarbeitung
AU2002254921A AU2002254921A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and processing data
PCT/EP2002/002398 WO2002071248A2 (de) 2001-03-05 2002-03-05 Verfahren und vorrichtungen zur datenbe- und/oder verarbeitung
EP02727358A EP1540507B1 (de) 2001-03-05 2002-03-05 Vorrichtung zur datenverarbeitung mit einem feld rekonfigurierbarer elemente
AU2002257615A AU2002257615A1 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
JP2002570052A JP4011488B2 (ja) 2001-03-05 2002-03-05 データ加工および／またはデータ処理方法および装置
EP02724198.3A EP1386220B1 (de) 2001-03-05 2002-03-05 Verfahren und vorrichtung zu datenbe- und/oder verarbeitung
US10/469,910 US20070299993A1 (en) 2001-03-05 2002-03-05 Method and Device for Treating and Processing Data
PCT/EP2002/002403 WO2002071249A2 (de) 2001-03-05 2002-03-05 Verfahren und vorrichtungen zur datenbe- und/oder verarbeitung
US10/471,061 US7581076B2 (en) 2001-03-05 2002-03-05 Methods and devices for treating and/or processing data
JP2002570103A JP2004535613A (ja) 2001-03-05 2002-03-05 データ処理方法およびデータ処理装置
EP02712937A EP1454258A2 (de) 2001-03-05 2002-03-05 Verfahren und vorrichtungen zur datenbe- und/oder verarbeitung
JP2002570104A JP2004536373A (ja) 2001-03-05 2002-03-05 データ処理方法およびデータ処理装置
JP2008249106A JP2009054170A (ja) 2001-03-05 2008-09-26 データ流の管理方法
JP2008249115A JP2009043275A (ja) 2001-03-05 2008-09-26 シーケンスの形成方法
JP2008249116A JP2009043276A (ja) 2001-03-05 2008-09-26 Ｆｉｆｏ記憶方法
JP2008249099A JP2009032281A (ja) 2001-03-05 2008-09-26 データ伝送方法
JP2008249112A JP2009020909A (ja) 2001-03-05 2008-09-26 グラフのパーティショニング方法
US12/496,012 US20090300262A1 (en) 2001-03-05 2009-07-01 Methods and devices for treating and/or processing data
US12/944,068 US9037807B2 (en) 2001-03-05 2010-11-11 Processor arrangement on a chip including data processing, memory, and interface elements
US13/043,102 US20110173389A1 (en) 2001-03-05 2011-03-08 Methods and devices for treating and/or processing data
US13/653,639 US9075605B2 (en) 2001-03-05 2012-10-17 Methods and devices for treating and processing data
US14/219,945 US9552047B2 (en) 2001-03-05 2014-03-19 Multiprocessor having runtime adjustable clock and clock dependent power supply
US14/231,358 US9436631B2 (en) 2001-03-05 2014-03-31 Chip including memory element storing higher level memory data on a page by page basis
US14/318,211 US9250908B2 (en) 2001-03-05 2014-06-27 Multi-processor bus and cache interconnection system
US14/500,618 US9141390B2 (en) 2001-03-05 2014-09-29 Method of processing data with an array of data processors according to application ID
US15/225,638 US10152320B2 (en) 2001-03-05 2016-08-01 Method of transferring data between external devices and an array processor
US15/408,358 US10331194B2 (en) 2001-03-05 2017-01-17 Methods and devices for treating and processing data
US16/190,931 US20190102173A1 (en) 2001-03-05 2018-11-14 Methods and systems for transferring data between a processing device and external devices

Applications Claiming Priority (16)

Application Number Priority Date Filing Date Title
DE10036221.4 2000-07-24
DE10036221 2000-07-24
DE10036627A DE10036627A1 (de) 2000-07-24 2000-07-27 Integrierter Schaltkreis
DE10036627.9 2000-07-27
EPPCT/EP00/10516 2000-10-09
EPPCT/EP00/10516 2000-10-09
EP01102674 2001-02-07
EP01102674.7 2001-02-07
DE10110530 2001-03-05
DE10110530.4 2001-03-05
DE10111014 2001-03-07
DE10111014.6 2001-03-07
PCT/EP2001/006703 WO2002013000A2 (de) 2000-06-13 2001-06-13 Pipeline ct-protokolle und -kommunikation
EPPCT/EP01/06703 2001-06-13
DE10129237.6 2001-06-20
DE10129237A DE10129237A1 (de) 2000-10-09 2002-06-20 Verfahren zur Bearbeitung von Daten

Publications (2)

Publication Number Publication Date
WO2002008964A2 WO2002008964A2 (de) 2002-01-31
WO2002008964A3 true WO2002008964A3 (de) 2003-10-23

Family

ID=56290174

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2001/008534 Ceased WO2002008964A2 (de) 2000-07-24 2001-07-24 Integrierter schaltkreis

Country Status (3)

Country Link
EP (1) EP1377919A2 (de)
AU (1) AU2001289737A1 (de)
WO (1) WO2002008964A2 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003071432A2 (de) 2002-02-18 2003-08-28 Pact Xpp Technologies Ag Bussysteme und rekonfigurationsverfahren
FR2838208B1 (fr) * 2002-04-03 2005-03-11 Centre Nat Rech Scient Architecture de calcul logique comprenant plusieurs modes de configuration

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994014123A1 (en) * 1992-12-11 1994-06-23 National Technology, Inc. Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means
DE19654595A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
EP0858168A1 (de) * 1997-01-29 1998-08-12 Hewlett-Packard Company Feldprogrammierbarer Gatterprozessor
WO1999040522A2 (en) * 1998-02-05 1999-08-12 Sheng, George, S. Digital signal processor using a reconfigurable array of macrocells

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0688659A3 (de) * 1994-06-23 1997-10-08 Illig Maschinenbau Adolf Form- Stanz-Werkzeug zum Herstellen von Behältern aus thermoplastischer Kunststoffolie
US5636368A (en) * 1994-12-23 1997-06-03 Xilinx, Inc. Method for programming complex PLD having more than one function block type
GB9611994D0 (en) * 1996-06-07 1996-08-07 Systolix Ltd A field programmable processor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1994014123A1 (en) * 1992-12-11 1994-06-23 National Technology, Inc. Integrated circuit computing device comprising dynamically configurable gate array having a reconfigurable execution means
DE19654595A1 (de) * 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
DE19654846A1 (de) * 1996-12-27 1998-07-09 Pact Inf Tech Gmbh Verfahren zum selbständigen dynamischen Umladen von Datenflußprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o. dgl.)
EP0858168A1 (de) * 1997-01-29 1998-08-12 Hewlett-Packard Company Feldprogrammierbarer Gatterprozessor
WO1999040522A2 (en) * 1998-02-05 1999-08-12 Sheng, George, S. Digital signal processor using a reconfigurable array of macrocells

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1377919A2 *

Also Published As

Publication number Publication date
EP1377919A2 (de) 2004-01-07
AU2001289737A1 (en) 2002-02-05
WO2002008964A2 (de) 2002-01-31

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