WO2002015266A3 - Direct build-up layer on an encapsulated die package - Google Patents

Direct build-up layer on an encapsulated die package Download PDF

Info

Publication number
WO2002015266A3
WO2002015266A3 PCT/US2001/025060 US0125060W WO0215266A3 WO 2002015266 A3 WO2002015266 A3 WO 2002015266A3 US 0125060 W US0125060 W US 0125060W WO 0215266 A3 WO0215266 A3 WO 0215266A3
Authority
WO
WIPO (PCT)
Prior art keywords
microelectronic die
layer
active surface
die package
encapsulation material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/025060
Other languages
French (fr)
Other versions
WO2002015266A2 (en
Inventor
Xiao-Chun Mu
Qing Ma
Harry Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP01962043A priority Critical patent/EP1354351B1/en
Priority to AU2001283257A priority patent/AU2001283257A1/en
Priority to HK03108126.7A priority patent/HK1055844B/en
Priority to DE60138416T priority patent/DE60138416D1/en
Priority to AT01962043T priority patent/ATE429032T1/en
Publication of WO2002015266A2 publication Critical patent/WO2002015266A2/en
Anticipated expiration legal-status Critical
Publication of WO2002015266A3 publication Critical patent/WO2002015266A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Micromachines (AREA)
  • Air Bags (AREA)
  • Die Bonding (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Chemical Treatment Of Metals (AREA)

Abstract

A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s), wherein the encapsulation material includes at least one surface substantially planar to the microelectronic die active surface. A first dielectric material layer may be disposed on at least a portion of the microelectronic die active surface and the encapsulation material surface. At least one conductive trace is then disposed on the first dielectric material layer. The conductive trace(s) is in electrical contact with the microelectronic die active surface. At least one conductive trace extends adjacent the microelectronic die active surface and adjacent the encapsulation material surface.
PCT/US2001/025060 2000-08-16 2001-08-10 Direct build-up layer on an encapsulated die package Ceased WO2002015266A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP01962043A EP1354351B1 (en) 2000-08-16 2001-08-10 Direct build-up layer on an encapsulated die package
AU2001283257A AU2001283257A1 (en) 2000-08-16 2001-08-10 Direct build-up layer on an encapsulated die package
HK03108126.7A HK1055844B (en) 2000-08-16 2001-08-10 Direct-build-up layer on an encapsulated die package
DE60138416T DE60138416D1 (en) 2000-08-16 2001-08-10 PACK
AT01962043T ATE429032T1 (en) 2000-08-16 2001-08-10 DIRECT BUILD LAYER ON AN ENCAPSULATED CHIP PACKAGING

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US64096100A 2000-08-16 2000-08-16
US09/640,961 2000-08-16

Publications (2)

Publication Number Publication Date
WO2002015266A2 WO2002015266A2 (en) 2002-02-21
WO2002015266A3 true WO2002015266A3 (en) 2003-08-14

Family

ID=24570376

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/025060 Ceased WO2002015266A2 (en) 2000-08-16 2001-08-10 Direct build-up layer on an encapsulated die package

Country Status (7)

Country Link
EP (1) EP1354351B1 (en)
CN (1) CN100426492C (en)
AT (1) ATE429032T1 (en)
AU (1) AU2001283257A1 (en)
DE (1) DE60138416D1 (en)
MY (1) MY141327A (en)
WO (1) WO2002015266A2 (en)

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CN100389494C (en) * 2002-05-23 2008-05-21 威盛电子股份有限公司 Manufacturing process of integrated circuit packaging
DE10320579A1 (en) * 2003-05-07 2004-08-26 Infineon Technologies Ag Semiconductor wafer having an upper side, semiconductor chip positions with integrated circuits for first chips, central and edge regions and an equalizing layer useful in semiconductor technology
FR2857157B1 (en) * 2003-07-01 2005-09-23 3D Plus Sa METHOD FOR INTERCONNECTING ACTIVE AND PASSIVE COMPONENTS AND HETEROGENEOUS COMPONENT WITH LOW THICKNESS THEREFROM
DE10343053A1 (en) * 2003-09-16 2005-04-07 Siemens Ag Electronic component and arrangement with an electronic component
US7338836B2 (en) * 2003-11-05 2008-03-04 California Institute Of Technology Method for integrating pre-fabricated chip structures into functional electronic systems
DE102004022884B4 (en) 2004-05-06 2007-07-19 Infineon Technologies Ag Semiconductor device with a rewiring substrate and method of making the same
JP4343044B2 (en) 2004-06-30 2009-10-14 新光電気工業株式会社 Interposer, manufacturing method thereof, and semiconductor device
CN100578771C (en) * 2006-11-22 2010-01-06 南亚电路板股份有限公司 Embedded chip packaging structure
JP5193898B2 (en) 2009-02-12 2013-05-08 新光電気工業株式会社 Semiconductor device and electronic device
JP5535494B2 (en) 2009-02-23 2014-07-02 新光電気工業株式会社 Semiconductor device
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
FR2943176B1 (en) * 2009-03-10 2011-08-05 3D Plus METHOD FOR POSITIONING CHIPS WHEN MANUFACTURING A RECONSTITUTED PLATE
JP5106460B2 (en) 2009-03-26 2012-12-26 新光電気工業株式会社 Semiconductor device, manufacturing method thereof, and electronic device
JP5330065B2 (en) 2009-04-13 2013-10-30 新光電気工業株式会社 Electronic device and manufacturing method thereof
FR2946795B1 (en) * 2009-06-12 2011-07-22 3D Plus METHOD FOR POSITIONING CHIPS WHEN MANUFACTURING A RECONSTITUTED PLATE
JP5296636B2 (en) * 2009-08-21 2013-09-25 新光電気工業株式会社 Manufacturing method of semiconductor package
JP5541618B2 (en) 2009-09-01 2014-07-09 新光電気工業株式会社 Manufacturing method of semiconductor package
JP5325736B2 (en) 2009-10-06 2013-10-23 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
JP5249173B2 (en) 2009-10-30 2013-07-31 新光電気工業株式会社 Semiconductor device mounting wiring board and method for manufacturing the same
JP5543754B2 (en) 2009-11-04 2014-07-09 新光電気工業株式会社 Semiconductor package and manufacturing method thereof
EP2330618A1 (en) 2009-12-04 2011-06-08 STMicroelectronics (Grenoble 2) SAS Rebuilt wafer assembly
JP5581519B2 (en) 2009-12-04 2014-09-03 新光電気工業株式会社 Semiconductor package and manufacturing method thereof
JP5584011B2 (en) 2010-05-10 2014-09-03 新光電気工業株式会社 Manufacturing method of semiconductor package
JP5826532B2 (en) 2010-07-15 2015-12-02 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US9064883B2 (en) 2011-08-25 2015-06-23 Intel Mobile Communications GmbH Chip with encapsulated sides and exposed surface
US9082825B2 (en) 2011-10-19 2015-07-14 Panasonic Corporation Manufacturing method for semiconductor package, semiconductor package, and semiconductor device
KR101332916B1 (en) 2011-12-29 2013-11-26 주식회사 네패스 Semiconductor package and method of manufacturing the same
US9136236B2 (en) 2012-09-28 2015-09-15 Intel Corporation Localized high density substrate routing
US8912670B2 (en) * 2012-09-28 2014-12-16 Intel Corporation Bumpless build-up layer package including an integrated heat spreader
US9190380B2 (en) 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9159690B2 (en) 2013-09-25 2015-10-13 Intel Corporation Tall solders for through-mold interconnect
US9349703B2 (en) 2013-09-25 2016-05-24 Intel Corporation Method for making high density substrate interconnect using inkjet printing
CN107256848A (en) * 2017-05-25 2017-10-17 日月光封装测试(上海)有限公司 Semiconductor package assembly and a manufacturing method thereof
WO2019103676A1 (en) * 2017-11-24 2019-05-31 Fingerprint Cards Ab Ultra-thin fingerprint sensor component and manufacturing method
CN112582287A (en) * 2019-09-30 2021-03-30 中芯长电半导体（江阴）有限公司 Wafer-level chip packaging structure and packaging method
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Also Published As

Publication number Publication date
AU2001283257A1 (en) 2002-02-25
EP1354351A2 (en) 2003-10-22
MY141327A (en) 2010-04-16
HK1055844A1 (en) 2004-01-21
EP1354351B1 (en) 2009-04-15
CN1535479A (en) 2004-10-06
WO2002015266A2 (en) 2002-02-21
CN100426492C (en) 2008-10-15
DE60138416D1 (en) 2009-05-28
ATE429032T1 (en) 2009-05-15

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