WO2002029972A3 - Buffers with reduced voltage input/output signals - Google Patents

Buffers with reduced voltage input/output signals Download PDF

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Publication number
WO2002029972A3
WO2002029972A3 PCT/US2001/029192 US0129192W WO0229972A3 WO 2002029972 A3 WO2002029972 A3 WO 2002029972A3 US 0129192 W US0129192 W US 0129192W WO 0229972 A3 WO0229972 A3 WO 0229972A3
Authority
WO
WIPO (PCT)
Prior art keywords
reduced voltage
output signals
buffers
voltage range
voltage input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2001/029192
Other languages
French (fr)
Other versions
WO2002029972A2 (en
Inventor
Gerhard Mueller
David R Hanson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Infineon Technologies North America Corp
Original Assignee
International Business Machines Corp
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp, Infineon Technologies North America Corp filed Critical International Business Machines Corp
Priority to DE60137370T priority Critical patent/DE60137370D1/en
Priority to EP01986377A priority patent/EP1360765B1/en
Publication of WO2002029972A2 publication Critical patent/WO2002029972A2/en
Anticipated expiration legal-status Critical
Publication of WO2002029972A3 publication Critical patent/WO2002029972A3/en
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)

Abstract

A buffer circuit that operates with reduced voltage input and output signals is described. The buffer circuit receives an input signal having reduced voltage range and generates an output signal with the reduced voltage range. The reduced voltage range is form 0 volts to VRED, where VRED is less than VCC, the voltage used to operate most of the logic in the integrated circuit. The use of a buffer circuit that receives and generates signals with a reduced voltage range advantageously reduces power consumption.
PCT/US2001/029192 2000-09-29 2001-09-19 Buffers with reduced voltage input/output signals Ceased WO2002029972A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE60137370T DE60137370D1 (en) 2000-09-29 2001-09-19 BUFFERS WITH REDUCED INPUT / OUTPUT VOLTAGES
EP01986377A EP1360765B1 (en) 2000-09-29 2001-09-19 Buffers with reduced voltage input/output signals

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/676,864 2000-09-29
US09/676,864 US6426658B1 (en) 2000-09-29 2000-09-29 Buffers with reduced voltage input/output signals

Publications (2)

Publication Number Publication Date
WO2002029972A2 WO2002029972A2 (en) 2002-04-11
WO2002029972A3 true WO2002029972A3 (en) 2003-07-10

Family

ID=24716342

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/029192 Ceased WO2002029972A2 (en) 2000-09-29 2001-09-19 Buffers with reduced voltage input/output signals

Country Status (4)

Country Link
US (1) US6426658B1 (en)
EP (1) EP1360765B1 (en)
DE (1) DE60137370D1 (en)
WO (1) WO2002029972A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040032284A1 (en) * 2002-06-13 2004-02-19 Stmicroelectronics Pvt. Ltd. Digital electronic circuit for translating high voltage levels to low voltage levels
TW589795B (en) * 2003-07-14 2004-06-01 Realtek Semiconductor Corp High-to-low level shift circuit
JP2005144707A (en) * 2003-11-11 2005-06-09 Brother Ind Ltd Drive circuit and inkjet head drive circuit
KR100541556B1 (en) * 2004-03-29 2006-01-10 삼성전자주식회사 Semiconductor integrated circuit device and its on die termination circuit
US8487695B2 (en) * 2011-09-23 2013-07-16 Tensorcom, Inc. Differential source follower having 6dB gain with applications to WiGig baseband filters
US9304534B1 (en) 2014-09-24 2016-04-05 Freescale Semiconductor, Inc. Low voltage swing buffer
KR102642071B1 (en) 2015-11-17 2024-02-28 텐서컴, 인코퍼레이티드 Highly linear WiGig baseband amplifier with channel selection filter

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920284A (en) * 1987-10-22 1990-04-24 Nec Corporation CMOS level converter circuit with reduced power consumption
US5266848A (en) * 1990-03-28 1993-11-30 Hitachi, Ltd. CMOS circuit with reduced signal swing
US5903142A (en) * 1997-06-27 1999-05-11 Cypress Semiconductor Corp. Low distortion level shifter
US6191636B1 (en) * 1999-09-22 2001-02-20 Cypress Semiconductor Corp. Input buffer/level shifter

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2605565B2 (en) * 1992-11-27 1997-04-30 日本電気株式会社 Semiconductor integrated circuit
US5367205A (en) * 1993-05-13 1994-11-22 Micron Semiconductor, Inc. High speed output buffer with reduced voltage bounce and no cross current
JP3238826B2 (en) * 1994-04-13 2001-12-17 富士通株式会社 Output circuit
JP2964971B2 (en) * 1997-01-24 1999-10-18 日本電気株式会社 Pull-up circuit and pull-down circuit
US6271713B1 (en) * 1999-05-14 2001-08-07 Intel Corporation Dynamic threshold source follower voltage driver circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920284A (en) * 1987-10-22 1990-04-24 Nec Corporation CMOS level converter circuit with reduced power consumption
US5266848A (en) * 1990-03-28 1993-11-30 Hitachi, Ltd. CMOS circuit with reduced signal swing
US5903142A (en) * 1997-06-27 1999-05-11 Cypress Semiconductor Corp. Low distortion level shifter
US6191636B1 (en) * 1999-09-22 2001-02-20 Cypress Semiconductor Corp. Input buffer/level shifter

Also Published As

Publication number Publication date
US6426658B1 (en) 2002-07-30
EP1360765A2 (en) 2003-11-12
DE60137370D1 (en) 2009-02-26
WO2002029972A2 (en) 2002-04-11
EP1360765B1 (en) 2009-01-07

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