WO2002071239A3 - Data processing apparatus and system and method for controlling memory access - Google Patents

Data processing apparatus and system and method for controlling memory access Download PDF

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Publication number
WO2002071239A3
WO2002071239A3 PCT/CA2002/000278 CA0200278W WO02071239A3 WO 2002071239 A3 WO2002071239 A3 WO 2002071239A3 CA 0200278 W CA0200278 W CA 0200278W WO 02071239 A3 WO02071239 A3 WO 02071239A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory access
processing apparatus
data processing
controlling memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CA2002/000278
Other languages
French (fr)
Other versions
WO2002071239A2 (en
Inventor
Eric Giernalczyk
Malcom Stewart
Adrian G Nita
Denny Wong
Andrew Stewart
Tuan Ho
Thinh M Le
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ATSANA SEMICONDUCTOR CORP
Original Assignee
ATSANA SEMICONDUCTOR CORP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATSANA SEMICONDUCTOR CORP filed Critical ATSANA SEMICONDUCTOR CORP
Priority to AU2002238325A priority Critical patent/AU2002238325A1/en
Priority to US10/469,526 priority patent/US20060064553A9/en
Priority to EP02704518A priority patent/EP1381957A2/en
Priority to CA002478570A priority patent/CA2478570A1/en
Publication of WO2002071239A2 publication Critical patent/WO2002071239A2/en
Publication of WO2002071239A3 publication Critical patent/WO2002071239A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • G06F15/8015—One dimensional arrays, e.g. rings, linear arrays, buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3812—Devices capable of handling different types of numbers
    • G06F2207/382—Reconfigurable for different fixed word lengths
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/3808—Details concerning the type of numbers or the way they are handled
    • G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Communication Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Information Transfer Systems (AREA)
  • Selective Calling Equipment (AREA)

Abstract

A data processor comprises a memory having storage elements arranged in columns and a number of column decoders, each having a memory access port. The data processor has a plurality of processing elements, and each of the memory ports is coupleable to at least a respective one of the processor elements, such that each processor element is capable of accessing at least one column of storage elements.
PCT/CA2002/000278 2001-03-02 2002-03-04 Data processing apparatus and system and method for controlling memory access Ceased WO2002071239A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU2002238325A AU2002238325A1 (en) 2001-03-02 2002-03-04 Data processing apparatus and system and method for controlling memory access
US10/469,526 US20060064553A9 (en) 2001-03-02 2002-03-04 Data processing apparatus and system and method for controlling memory access
EP02704518A EP1381957A2 (en) 2001-03-02 2002-03-04 Data processing apparatus and system and method for controlling memory access
CA002478570A CA2478570A1 (en) 2001-03-02 2002-03-04 Data processing apparatus and system and method for controlling memory access

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US27230101P 2001-03-02 2001-03-02
US60/272,301 2001-03-02

Publications (2)

Publication Number Publication Date
WO2002071239A2 WO2002071239A2 (en) 2002-09-12
WO2002071239A3 true WO2002071239A3 (en) 2003-04-10

Family

ID=23039227

Family Applications (3)

Application Number Title Priority Date Filing Date
PCT/CA2002/000278 Ceased WO2002071239A2 (en) 2001-03-02 2002-03-04 Data processing apparatus and system and method for controlling memory access
PCT/CA2002/000279 Ceased WO2002071240A2 (en) 2001-03-02 2002-03-04 Apparatus for variable word length computing in an array processor
PCT/CA2002/000299 Ceased WO2002071246A2 (en) 2001-03-02 2002-03-04 An apparatus for controlling access in a data processor

Family Applications After (2)

Application Number Title Priority Date Filing Date
PCT/CA2002/000279 Ceased WO2002071240A2 (en) 2001-03-02 2002-03-04 Apparatus for variable word length computing in an array processor
PCT/CA2002/000299 Ceased WO2002071246A2 (en) 2001-03-02 2002-03-04 An apparatus for controlling access in a data processor

Country Status (7)

Country Link
US (2) US20040254965A1 (en)
EP (3) EP1381957A2 (en)
AT (1) ATE404923T1 (en)
AU (3) AU2002252863A1 (en)
CA (3) CA2478570A1 (en)
DE (1) DE60228223D1 (en)
WO (3) WO2002071239A2 (en)

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US7461234B2 (en) * 2002-07-01 2008-12-02 Panasonic Corporation Loosely-biased heterogeneous reconfigurable arrays
US20040085910A1 (en) * 2002-11-01 2004-05-06 Zarlink Semiconductor V.N. Inc. Media access control device for high efficiency ethernet backplane
US7421691B1 (en) * 2003-12-23 2008-09-02 Unisys Corporation System and method for scaling performance of a data processing system
US20050273559A1 (en) 2004-05-19 2005-12-08 Aris Aristodemou Microprocessor architecture including unified cache debug unit
US7757048B2 (en) * 2005-04-29 2010-07-13 Mtekvision Co., Ltd. Data processor apparatus and memory interface
US7836284B2 (en) * 2005-06-09 2010-11-16 Qualcomm Incorporated Microprocessor with automatic selection of processing parallelism mode based on width data of instructions
US7694114B2 (en) * 2005-06-09 2010-04-06 Qualcomm Incorporated Software selectable adjustment of SIMD parallelism
WO2007049150A2 (en) 2005-09-28 2007-05-03 Arc International (Uk) Limited Architecture for microprocessor-based systems including simd processing unit and associated systems and methods
US8024394B2 (en) * 2006-02-06 2011-09-20 Via Technologies, Inc. Dual mode floating point multiply accumulate unit
US8656143B2 (en) 2006-03-13 2014-02-18 Laurence H. Cooke Variable clocked heterogeneous serial array processor
US20070226455A1 (en) * 2006-03-13 2007-09-27 Cooke Laurence H Variable clocked heterogeneous serial array processor
US8532288B2 (en) * 2006-12-01 2013-09-10 International Business Machines Corporation Selectively isolating processor elements into subsets of processor elements
WO2011118013A1 (en) * 2010-03-25 2011-09-29 富士通株式会社 Multi-core processor system, memory controller control method and memory controller control program
US10142124B2 (en) * 2012-05-24 2018-11-27 Infineon Technologies Ag System and method to transmit data over a bus system
US9798550B2 (en) * 2013-01-09 2017-10-24 Nxp Usa, Inc. Memory access for a vector processor
JP6308095B2 (en) 2014-10-08 2018-04-11 富士通株式会社 Arithmetic circuit and control method of arithmetic circuit
US9971541B2 (en) 2016-02-17 2018-05-15 Micron Technology, Inc. Apparatuses and methods for data movement
DE102016003362A1 (en) 2016-03-18 2017-09-21 Giesecke+Devrient Currency Technology Gmbh Device and method for evaluating sensor data for a document of value
US10268389B2 (en) 2017-02-22 2019-04-23 Micron Technology, Inc. Apparatuses and methods for in-memory operations
US10318168B2 (en) 2017-06-19 2019-06-11 Micron Technology, Inc. Apparatuses and methods for simultaneous in data path compute operations
US11106268B2 (en) * 2018-07-29 2021-08-31 Redpine Signals, Inc. Method and system for saving power in a real time hardware processing unit
KR102828859B1 (en) * 2020-06-05 2025-07-04 주식회사 퓨리오사에이아이 Neural network processing method and device therefor
US12013809B2 (en) * 2020-09-30 2024-06-18 Beijing Tsingmicro Intelligent Technology Co., Ltd. Computing array and processor having the same
US12394009B2 (en) * 2021-05-28 2025-08-19 MemComputing, Inc. Memory graphics processing unit

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US5325500A (en) * 1990-12-14 1994-06-28 Xerox Corporation Parallel processing units on a substrate, each including a column of memory

Also Published As

Publication number Publication date
CA2478571A1 (en) 2002-09-12
WO2002071240A3 (en) 2003-05-30
US7272691B2 (en) 2007-09-18
AU2002240742A1 (en) 2002-09-19
DE60228223D1 (en) 2008-09-25
WO2002071246A3 (en) 2003-05-15
CA2478570A1 (en) 2002-09-12
CA2478573C (en) 2010-05-25
WO2002071246A2 (en) 2002-09-12
EP1384160A2 (en) 2004-01-28
WO2002071239A2 (en) 2002-09-12
CA2478573A1 (en) 2002-09-12
EP1384158A2 (en) 2004-01-28
US20070118721A1 (en) 2007-05-24
EP1381957A2 (en) 2004-01-21
ATE404923T1 (en) 2008-08-15
AU2002238325A1 (en) 2002-09-19
EP1384158B1 (en) 2008-08-13
AU2002252863A1 (en) 2002-09-19
US20040254965A1 (en) 2004-12-16
WO2002071240A2 (en) 2002-09-12

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