WO2002082653A3 - Integrated circuit - Google Patents

Integrated circuit Download PDF

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Publication number
WO2002082653A3
WO2002082653A3 PCT/GB2002/001407 GB0201407W WO02082653A3 WO 2002082653 A3 WO2002082653 A3 WO 2002082653A3 GB 0201407 W GB0201407 W GB 0201407W WO 02082653 A3 WO02082653 A3 WO 02082653A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
logic area
logic
area
disclosed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB2002/001407
Other languages
French (fr)
Other versions
WO2002082653A2 (en
Inventor
Stephen Maxwell Parkes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Dundee
Original Assignee
University of Dundee
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Dundee filed Critical University of Dundee
Priority to DE60239862T priority Critical patent/DE60239862D1/en
Priority to EP02718307A priority patent/EP1374403B1/en
Priority to AU2002249377A priority patent/AU2002249377A1/en
Priority to AT02718307T priority patent/ATE507615T1/en
Publication of WO2002082653A2 publication Critical patent/WO2002082653A2/en
Publication of WO2002082653A3 publication Critical patent/WO2002082653A3/en
Priority to US10/679,978 priority patent/US7012448B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

There is disclosed an improved integrated circuit (5) and a related system apparatus and method. The integrated circuit (5) comprises: a plurality of logic area of user logic areas (10); and an actively switchable network capable of selectively connecting at least one logic area (10) is with another logic area (10).
PCT/GB2002/001407 2001-04-07 2002-03-27 Integrated circuit Ceased WO2002082653A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE60239862T DE60239862D1 (en) 2001-04-07 2002-03-27 INTEGRATED CIRCUIT
EP02718307A EP1374403B1 (en) 2001-04-07 2002-03-27 Integrated circuit
AU2002249377A AU2002249377A1 (en) 2001-04-07 2002-03-27 Integrated circuit
AT02718307T ATE507615T1 (en) 2001-04-07 2002-03-27 INTEGRATED CIRCUIT
US10/679,978 US7012448B2 (en) 2001-04-07 2003-10-06 Integrated circuit and related improvements

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0108807A GB2374242B (en) 2001-04-07 2001-04-07 Integrated circuit and related improvements
GB0108807.9 2001-04-07

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/679,978 Continuation US7012448B2 (en) 2001-04-07 2003-10-06 Integrated circuit and related improvements

Publications (2)

Publication Number Publication Date
WO2002082653A2 WO2002082653A2 (en) 2002-10-17
WO2002082653A3 true WO2002082653A3 (en) 2002-11-21

Family

ID=9912482

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/001407 Ceased WO2002082653A2 (en) 2001-04-07 2002-03-27 Integrated circuit

Country Status (7)

Country Link
US (1) US7012448B2 (en)
EP (1) EP1374403B1 (en)
AT (1) ATE507615T1 (en)
AU (1) AU2002249377A1 (en)
DE (1) DE60239862D1 (en)
GB (1) GB2374242B (en)
WO (1) WO2002082653A2 (en)

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US10572376B2 (en) 2016-12-30 2020-02-25 Intel Corporation Memory ordering in acceleration hardware
US10416999B2 (en) 2016-12-30 2019-09-17 Intel Corporation Processors, methods, and systems with a configurable spatial accelerator
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US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
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US10445098B2 (en) 2017-09-30 2019-10-15 Intel Corporation Processors and methods for privileged configuration in a spatial array
US10417175B2 (en) 2017-12-30 2019-09-17 Intel Corporation Apparatus, methods, and systems for memory consistency in a configurable spatial accelerator
US10565134B2 (en) * 2017-12-30 2020-02-18 Intel Corporation Apparatus, methods, and systems for multicast in a configurable spatial accelerator
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US10564980B2 (en) 2018-04-03 2020-02-18 Intel Corporation Apparatus, methods, and systems for conditional queues in a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10459866B1 (en) 2018-06-30 2019-10-29 Intel Corporation Apparatuses, methods, and systems for integrated control and data processing in a configurable spatial accelerator
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Also Published As

Publication number Publication date
DE60239862D1 (en) 2011-06-09
GB2374242A (en) 2002-10-09
GB0108807D0 (en) 2001-05-30
ATE507615T1 (en) 2011-05-15
AU2002249377A1 (en) 2002-10-21
WO2002082653A2 (en) 2002-10-17
EP1374403A2 (en) 2004-01-02
EP1374403B1 (en) 2011-04-27
US20040124877A1 (en) 2004-07-01
US7012448B2 (en) 2006-03-14
GB2374242B (en) 2005-03-16

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