WO2002095531A3 - Circuit having a controllable slew rate - Google Patents

Circuit having a controllable slew rate Download PDF

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Publication number
WO2002095531A3
WO2002095531A3 PCT/US2002/015261 US0215261W WO02095531A3 WO 2002095531 A3 WO2002095531 A3 WO 2002095531A3 US 0215261 W US0215261 W US 0215261W WO 02095531 A3 WO02095531 A3 WO 02095531A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
switch
input signal
output
slew rate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2002/015261
Other languages
French (fr)
Other versions
WO2002095531A2 (en
Inventor
Ken S Hunt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to KR1020037015338A priority Critical patent/KR100600918B1/en
Priority to EP02726870A priority patent/EP1405415B1/en
Priority to JP2002591939A priority patent/JP3950058B2/en
Priority to AU2002257274A priority patent/AU2002257274A1/en
Priority to DE60209891T priority patent/DE60209891T2/en
Publication of WO2002095531A2 publication Critical patent/WO2002095531A2/en
Publication of WO2002095531A3 publication Critical patent/WO2002095531A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/296—Time-programme switches providing a choice of time-intervals for executing more than one switching action and automatically terminating their operation after the programme is completed
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163—Soft switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/165—Modifications for eliminating interference voltages or currents in field-effect transistor switches by feedback from the output circuit to the control circuit
    • H03K17/166—Soft switching

Landscapes

  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Dram (AREA)
  • Amplifiers (AREA)
  • Networks Using Active Elements (AREA)
  • Lock And Its Accessories (AREA)

Abstract

A circuit for producing an output signal at an output thereof in response to an input signal at an input thereof is comprised, in one embodiment, of a first switch (50) for connecting the output to a first voltage source and a second switch (54) for connecting the output to a second voltage source. A first control switch (64) is provided for turning off the first switch in response to the logic level of the input signal while a second control switch (66) is provided for turning off the second switch in response to the logic level of the input signal. An integrator (60, 62) is responsive to the input signal for turning on one of the first and second switches depending on the logic level of the input signal. A method of operating such a circuit is also disclosed.
PCT/US2002/015261 2001-05-23 2002-05-14 Circuit having a controllable slew rate Ceased WO2002095531A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020037015338A KR100600918B1 (en) 2001-05-23 2002-05-14 Output circuit and output circuit operation method
EP02726870A EP1405415B1 (en) 2001-05-23 2002-05-14 Circuit having a controllable slew rate
JP2002591939A JP3950058B2 (en) 2001-05-23 2002-05-14 Circuit with controllable slew rate
AU2002257274A AU2002257274A1 (en) 2001-05-23 2002-05-14 Circuit having a controllable slew rate
DE60209891T DE60209891T2 (en) 2001-05-23 2002-05-14 CIRCUIT WITH CONTROLLABLE CHANGE SPEED

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/864,061 2001-05-23
US09/864,061 US6606271B2 (en) 2001-05-23 2001-05-23 Circuit having a controllable slew rate

Publications (2)

Publication Number Publication Date
WO2002095531A2 WO2002095531A2 (en) 2002-11-28
WO2002095531A3 true WO2002095531A3 (en) 2003-02-27

Family

ID=25342440

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/015261 Ceased WO2002095531A2 (en) 2001-05-23 2002-05-14 Circuit having a controllable slew rate

Country Status (9)

Country Link
US (1) US6606271B2 (en)
EP (2) EP1589661A1 (en)
JP (1) JP3950058B2 (en)
KR (2) KR100595080B1 (en)
CN (1) CN100459432C (en)
AT (1) ATE320675T1 (en)
AU (1) AU2002257274A1 (en)
DE (1) DE60209891T2 (en)
WO (1) WO2002095531A2 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030189448A1 (en) * 2002-04-08 2003-10-09 Silicon Video, Inc. MOSFET inverter with controlled slopes and a method of making
TW580787B (en) * 2003-03-14 2004-03-21 Novatek Microelectronics Corp Slew rate enhancement device and slew rate enhancement method
US6977530B1 (en) 2004-02-04 2005-12-20 Sun Microsystems, Inc. Pulse shaper circuit for sense amplifier enable driver
JP4401268B2 (en) * 2004-10-05 2010-01-20 Ｎｅｃエレクトロニクス株式会社 Output buffer circuit and semiconductor device
US7521975B2 (en) * 2005-01-20 2009-04-21 Advanced Micro Devices, Inc. Output buffer with slew rate control utilizing an inverse process dependent current reference
KR100706576B1 (en) * 2005-08-01 2007-04-13 삼성전자주식회사 Output drive circuit with controlled slew rate
US7312626B2 (en) * 2005-08-31 2007-12-25 Micron Technology, Inc. CMOS circuits with reduced crowbar current
JP2007202316A (en) * 2006-01-27 2007-08-09 Rohm Co Ltd Charge pump circuit and electrical equipment with the same
CN100449606C (en) * 2006-09-28 2009-01-07 友达光电股份有限公司 Display capable of adjusting signal slew rate and related driving method
US7786779B2 (en) * 2009-01-06 2010-08-31 Himax Technologies Limited Buffer for driving circuit and method thereof
US7924066B2 (en) * 2009-03-25 2011-04-12 Fairchild Semiconductor Corporation Low speed, load independent, slew rate controlled output buffer with no DC power consumption
KR20110037923A (en) 2009-10-07 2011-04-13 페어차일드 세미컨덕터 코포레이션 Edge rate control
TWI418148B (en) * 2010-06-22 2013-12-01 Univ Nat Chiao Tung A high load driving device
CN102386750B (en) * 2010-08-27 2014-04-09 中芯国际集成电路制造(北京)有限公司 Voltage conversion rate control circuit
KR101638264B1 (en) * 2011-09-29 2016-07-08 인텔 코포레이션 Method and apparatus for improving a load independent buffer
US8742803B2 (en) * 2012-09-26 2014-06-03 Broadcom Corporation Output driver using low voltage transistors
US9473127B1 (en) 2015-07-06 2016-10-18 Qualcomm Incorporated Input/output (I/O) driver
CN106168647B (en) * 2016-05-27 2019-04-02 重庆大学 IGBT aging state detection system
US10484089B1 (en) * 2018-04-27 2019-11-19 Hewlett Packard Enterprise Development Lp Driver assisted by charge sharing
US10491428B2 (en) 2018-04-27 2019-11-26 Hewlett Packard Enterprise Development Lp Current supply for an opto-electronic device
US10756725B2 (en) * 2018-06-21 2020-08-25 Texas Instruments Incorporated Load switch having a controlled slew rate
US12081331B2 (en) 2018-10-12 2024-09-03 Micron Technology, Inc. Adapting channel current
KR102792182B1 (en) * 2020-07-09 2025-04-09 삼성전자주식회사 Interface circuit and interface device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587951A (en) * 1995-08-04 1996-12-24 Atmel Corporation High speed, low voltage non-volatile memory
US5698991A (en) * 1995-02-28 1997-12-16 Nec Corporation Bus driver
US6236239B1 (en) * 1998-07-31 2001-05-22 Fujitsu Limited Output buffer circuit achieving stable operation and cost reduction

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3251661B2 (en) 1991-10-15 2002-01-28 テキサス インスツルメンツ インコーポレイテツド CMOS buffer circuit with controlled slew rate
JPH05206830A (en) * 1992-01-28 1993-08-13 Olympus Optical Co Ltd Output buffer circuit
US5296766A (en) 1992-06-04 1994-03-22 Sharp Microelectronics Technology, Inc. CMOS circuit with crowbar limiting function
JPH06309868A (en) * 1993-04-26 1994-11-04 Hitachi Ltd Semiconductor storage device
US5842155A (en) 1993-05-03 1998-11-24 Fairchild Semiconductor Corp. Method and apparatus for adjusting pin driver charging and discharging current
US5355029A (en) 1993-07-12 1994-10-11 Digital Equipment Corporation Staged CMOS output buffer
US5479132A (en) * 1994-06-06 1995-12-26 Ramtron International Corporation Noise and glitch suppressing filter with feedback
US5808481A (en) * 1996-06-28 1998-09-15 Intel Corporation Output swing clamp for USB differential buffer
US5838191A (en) 1997-02-21 1998-11-17 National Semiconductor Corporation Bias circuit for switched capacitor applications
JP3109458B2 (en) * 1997-08-11 2000-11-13 日本電気株式会社 Malfunction prevention circuit in H-bridge circuit
US5949259A (en) * 1997-11-19 1999-09-07 Atmel Corporation Zero-delay slew-rate controlled output buffer
US5973512A (en) * 1997-12-02 1999-10-26 National Semiconductor Corporation CMOS output buffer having load independent slewing
US6163169A (en) 1998-08-13 2000-12-19 International Business Machines Corporation CMOS tri-state control circuit for a bidirectional I/O with slew rate control
US6172522B1 (en) 1998-08-13 2001-01-09 International Business Machines Corporation Slew rate controlled predriver circuit
US6351138B1 (en) * 2001-03-22 2002-02-26 Pericom Semiconductor Corp. Zero-DC-power active termination with CMOS overshoot and undershoot clamps

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5698991A (en) * 1995-02-28 1997-12-16 Nec Corporation Bus driver
US5587951A (en) * 1995-08-04 1996-12-24 Atmel Corporation High speed, low voltage non-volatile memory
US6236239B1 (en) * 1998-07-31 2001-05-22 Fujitsu Limited Output buffer circuit achieving stable operation and cost reduction

Also Published As

Publication number Publication date
KR100600918B1 (en) 2006-07-13
JP2004527973A (en) 2004-09-09
EP1405415B1 (en) 2006-03-15
AU2002257274A1 (en) 2002-12-03
ATE320675T1 (en) 2006-04-15
EP1589661A1 (en) 2005-10-26
KR20040007603A (en) 2004-01-24
KR20060028659A (en) 2006-03-30
US20020176285A1 (en) 2002-11-28
JP3950058B2 (en) 2007-07-25
DE60209891T2 (en) 2006-08-31
DE60209891D1 (en) 2006-05-11
KR100595080B1 (en) 2006-06-30
WO2002095531A2 (en) 2002-11-28
EP1405415A2 (en) 2004-04-07
CN1529937A (en) 2004-09-15
CN100459432C (en) 2009-02-04
US6606271B2 (en) 2003-08-12

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