WO2002102005A3 - Pre-emphasis scheme - Google Patents

Pre-emphasis scheme Download PDF

Info

Publication number
WO2002102005A3
WO2002102005A3 PCT/US2002/016305 US0216305W WO02102005A3 WO 2002102005 A3 WO2002102005 A3 WO 2002102005A3 US 0216305 W US0216305 W US 0216305W WO 02102005 A3 WO02102005 A3 WO 02102005A3
Authority
WO
WIPO (PCT)
Prior art keywords
logic
transmitted
signal
value
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2002/016305
Other languages
French (fr)
Other versions
WO2002102005A2 (en
Inventor
Jyh-Ming Jong
Prabhansu Chakrabarti
Leo Yuan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to EP02726916A priority Critical patent/EP1332593B1/en
Priority to AU2002257317A priority patent/AU2002257317A1/en
Priority to JP2003504615A priority patent/JP2004522359A/en
Priority to DE60226001T priority patent/DE60226001D1/en
Publication of WO2002102005A2 publication Critical patent/WO2002102005A2/en
Publication of WO2002102005A3 publication Critical patent/WO2002102005A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0286—Provision of wave shaping within the driver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Amplifiers (AREA)
  • Gyroscopes (AREA)
  • Television Signal Processing For Recording (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)

Abstract

The disclosed method and circuitry for pre-emphasizing transmitted logic signals, may be applied to single-ended center-tapped terminated I/0 lines. In one embodiment, a driver circuit is configured for monitoring the logic values of signals transmitted by the driver circuit. The driver circuit compares the logic value of a next logic signal to be transmitted with a first and a second previously transmitted signal. Pre-emphasis of the next logic signal occurs based on the logic value of the next logic signal to be transmitted as well as the logic values of the first and second logic signals. If the first and second logic signals have the same logic value, and the next logic signal has a different value, the next logic value is pre-emphasized. If the next logic signal has a logic value that is equivalent to either the first logic signal or the second logic signal, it is transmitted without pre-emphasis.
PCT/US2002/016305 2001-06-11 2002-05-22 Pre-emphasis scheme Ceased WO2002102005A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP02726916A EP1332593B1 (en) 2001-06-11 2002-05-22 Pre-emphasis scheme
AU2002257317A AU2002257317A1 (en) 2001-06-11 2002-05-22 Pre-emphasis scheme
JP2003504615A JP2004522359A (en) 2001-06-11 2002-05-22 Method and circuit for pre-emphasis scheme for single-ended middle tap terminated high speed digital signaling
DE60226001T DE60226001D1 (en) 2001-06-11 2002-05-22 predistortion

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/879,501 2001-06-11
US09/879,501 US6518792B2 (en) 2001-06-11 2001-06-11 Method and circuitry for a pre-emphasis scheme for single-ended center taped terminated high speed digital signaling

Publications (2)

Publication Number Publication Date
WO2002102005A2 WO2002102005A2 (en) 2002-12-19
WO2002102005A3 true WO2002102005A3 (en) 2003-05-01

Family

ID=25374298

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/016305 Ceased WO2002102005A2 (en) 2001-06-11 2002-05-22 Pre-emphasis scheme

Country Status (7)

Country Link
US (1) US6518792B2 (en)
EP (1) EP1332593B1 (en)
JP (1) JP2004522359A (en)
AT (1) ATE392076T1 (en)
AU (1) AU2002257317A1 (en)
DE (1) DE60226001D1 (en)
WO (1) WO2002102005A2 (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3976734B2 (en) * 2002-03-29 2007-09-19 富士通株式会社 Driver driving method, driver circuit, and transmission method
US7307446B1 (en) 2003-01-07 2007-12-11 Altera Corporation Integrated circuit output driver circuitry with programmable preemphasis
US6940302B1 (en) 2003-01-07 2005-09-06 Altera Corporation Integrated circuit output driver circuitry with programmable preemphasis
JP3791498B2 (en) 2003-01-17 2006-06-28 日本電気株式会社 Output buffer circuit with pre-emphasis function
US7203243B2 (en) * 2003-03-10 2007-04-10 Acuid Corporation (Guernsey) Limited Line driver with reduced power consumption
US7126378B2 (en) 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
JP4245144B2 (en) * 2003-08-07 2009-03-25 株式会社ルネサステクノロジ Transmission signal correction circuit
US6975132B2 (en) * 2003-09-11 2005-12-13 Xilinx, Inc. DAC based driver with selectable pre-emphasis signal levels
KR100640593B1 (en) * 2004-10-26 2006-11-01 삼성전자주식회사 Output Driver Circuit with Cascaded Pre-Ampasis
US7227382B1 (en) 2005-02-01 2007-06-05 Advanced Micro Devices, Inc. Transmit based equalization using a voltage mode driver
JP4872228B2 (en) * 2005-03-28 2012-02-08 日本電気株式会社 Output buffer circuit
US7233165B2 (en) * 2005-03-31 2007-06-19 Seiko Epson Corporation High speed driver for serial communications
KR100688567B1 (en) 2005-08-25 2007-03-02 삼성전자주식회사 Pre-emphasis circuit with buffer with adjustable slew rate
JP5017903B2 (en) * 2006-03-30 2012-09-05 日本電気株式会社 Pre-emphasis adjustment method and method
US7991020B2 (en) * 2006-03-31 2011-08-02 Intel Corporation Quad rate transmitter equalization
US8315303B1 (en) * 2008-04-25 2012-11-20 Pmc-Sierra, Inc. Phase pre-emphasis for a serial data transmitter
JP5417105B2 (en) * 2009-09-28 2014-02-12 株式会社日立製作所 Serial output circuit and semiconductor device
US20160365137A1 (en) * 2015-06-11 2016-12-15 Broadcom Corporation Pre-Emphasis and Equalization for DRAM
US12388490B2 (en) 2022-03-25 2025-08-12 Advanced Micro Devices, Inc. Receiver equalization circuitry using variable termination and T-coil

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008903A (en) * 1989-05-25 1991-04-16 A.T. & T. Paradyne Adaptive transmit pre-emphasis for digital modem computed from noise spectrum
EP0763917A2 (en) * 1995-09-06 1997-03-19 Lucent Technologies Inc. Line driver with pulse shaper
US5896417A (en) * 1996-10-25 1999-04-20 National Semiconductor Corporation Apparatus utilizing current-to-voltage conversion for transmitting data at different data transfer rates especially in applications such as dual-rate ethernet local-area networks

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5942690A (en) * 1982-09-03 1984-03-09 Toshiba Corp Semiconductor storage device
JPH09214315A (en) * 1996-02-08 1997-08-15 Toshiba Corp Output buffer, semiconductor integrated circuit, and method for adjusting output buffer drive capability
JPH09266460A (en) 1996-03-28 1997-10-07 Sony Corp Transmission / reception system
JPH1125678A (en) * 1997-06-27 1999-01-29 Samsung Electron Co Ltd Output driver and semiconductor memory device
TW440767B (en) 1998-06-02 2001-06-16 Fujitsu Ltd Method of and apparatus for correctly transmitting signals at high speed without waveform distortion
US6393062B1 (en) 1998-09-21 2002-05-21 Maxim Integrated Products, Inc. Methods and circuits for generating a preemphasis waveform

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5008903A (en) * 1989-05-25 1991-04-16 A.T. & T. Paradyne Adaptive transmit pre-emphasis for digital modem computed from noise spectrum
EP0763917A2 (en) * 1995-09-06 1997-03-19 Lucent Technologies Inc. Line driver with pulse shaper
US5896417A (en) * 1996-10-25 1999-04-20 National Semiconductor Corporation Apparatus utilizing current-to-voltage conversion for transmitting data at different data transfer rates especially in applications such as dual-rate ethernet local-area networks

Also Published As

Publication number Publication date
JP2004522359A (en) 2004-07-22
US6518792B2 (en) 2003-02-11
US20020186056A1 (en) 2002-12-12
ATE392076T1 (en) 2008-04-15
EP1332593B1 (en) 2008-04-09
DE60226001D1 (en) 2008-05-21
WO2002102005A2 (en) 2002-12-19
EP1332593A2 (en) 2003-08-06
AU2002257317A1 (en) 2002-12-23

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