WO2003023602A1 - Data processing system and control method thereof - Google Patents
Data processing system and control method thereof Download PDFInfo
- Publication number
- WO2003023602A1 WO2003023602A1 PCT/JP2002/009108 JP0209108W WO03023602A1 WO 2003023602 A1 WO2003023602 A1 WO 2003023602A1 JP 0209108 W JP0209108 W JP 0209108W WO 03023602 A1 WO03023602 A1 WO 03023602A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- data
- processing units
- transfer means
- data transfer
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Multi Processors (AREA)
- Stored Programmes (AREA)
- Advance Control (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020047000161A KR100960518B1 (ko) | 2001-09-07 | 2002-09-06 | 데이터 처리 시스템 및 그 제어방법 |
| US10/399,360 US7380100B2 (en) | 2001-09-07 | 2002-09-06 | Data processing system and control method utilizing a plurality of date transfer means |
| CA2459411A CA2459411C (en) | 2001-09-07 | 2002-09-06 | Data processing system and control method |
| JP2003527588A JP4152319B2 (ja) | 2001-09-07 | 2002-09-06 | データ処理システムおよびその制御方法 |
| EP02767916A EP1443392A4 (en) | 2001-09-07 | 2002-09-06 | DATA PROCESSING DEVICE AND ASSOCIATED CONTROL METHOD |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001-272257 | 2001-09-07 | ||
| JP2001272257 | 2001-09-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2003023602A1 true WO2003023602A1 (en) | 2003-03-20 |
Family
ID=19097658
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2002/009108 Ceased WO2003023602A1 (en) | 2001-09-07 | 2002-09-06 | Data processing system and control method thereof |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7380100B2 (ja) |
| EP (1) | EP1443392A4 (ja) |
| JP (1) | JP4152319B2 (ja) |
| KR (1) | KR100960518B1 (ja) |
| CN (1) | CN100397331C (ja) |
| CA (1) | CA2459411C (ja) |
| TW (1) | TWI238317B (ja) |
| WO (1) | WO2003023602A1 (ja) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006083137A1 (en) * | 2005-02-07 | 2006-08-10 | Samsung Electronics Co., Ltd. | Method of generating usage rule information for broadcast channel |
| JP2007241830A (ja) * | 2006-03-10 | 2007-09-20 | Fujitsu Ltd | リコンフィグラブル回路 |
| WO2009005089A1 (ja) * | 2007-07-03 | 2009-01-08 | Nec Corporation | データ暗号化/復号化処理方法およびデータ処理装置 |
| JP2009157613A (ja) * | 2007-12-26 | 2009-07-16 | Fujitsu Microelectronics Ltd | リコンフィギュラブル回路 |
| WO2009096482A1 (ja) | 2008-01-31 | 2009-08-06 | Ipflex Inc. | 再構成可能なデバイス |
| US7941794B2 (en) | 2004-08-30 | 2011-05-10 | Sanyo Electric Co., Ltd. | Data flow graph processing method and processing apparatus provided with reconfigurable circuit |
| JP2011154534A (ja) * | 2010-01-27 | 2011-08-11 | Fujitsu Semiconductor Ltd | リコンフィギュラブル回路および半導体集積回路 |
| JP2011170900A (ja) * | 2011-06-08 | 2011-09-01 | Canon Inc | データ処理装置及びその制御方法 |
| US8243084B2 (en) | 2004-12-20 | 2012-08-14 | Canon Kabushiki Kaisha | Apparatus and method for processing data |
| WO2018179739A1 (ja) * | 2017-03-28 | 2018-10-04 | 富士通株式会社 | 情報処理装置、情報処理方法及びプログラム |
| JP2018530025A (ja) * | 2015-06-26 | 2018-10-11 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated | 高速で再構成可能な回路及び高帯域幅のメモリインタフェースを用いたコンピュータアーキテクチャ |
| JP2018180805A (ja) * | 2017-04-10 | 2018-11-15 | 東芝デベロップメントエンジニアリング株式会社 | 管理装置 |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7380100B2 (en) | 2001-09-07 | 2008-05-27 | Ipflex Inc. | Data processing system and control method utilizing a plurality of date transfer means |
| US7715377B2 (en) * | 2002-01-03 | 2010-05-11 | Integrated Device Technology, Inc. | Apparatus and method for matrix memory switching element |
| US7937557B2 (en) * | 2004-03-16 | 2011-05-03 | Vns Portfolio Llc | System and method for intercommunication between computers in an array |
| US7447725B2 (en) * | 2004-11-05 | 2008-11-04 | International Business Machines Corporation | Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units |
| US7668979B1 (en) * | 2005-03-25 | 2010-02-23 | Tilera Corporation | Buffering data in a parallel processing environment |
| US7904695B2 (en) * | 2006-02-16 | 2011-03-08 | Vns Portfolio Llc | Asynchronous power saving computer |
| JP4596538B2 (ja) * | 2005-09-05 | 2010-12-08 | 京セラミタ株式会社 | 情報処理装置、記録媒体、およびプログラム |
| US7904615B2 (en) | 2006-02-16 | 2011-03-08 | Vns Portfolio Llc | Asynchronous computer communication |
| US7934075B2 (en) * | 2006-02-16 | 2011-04-26 | Vns Portfolio Llc | Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array |
| US7966481B2 (en) | 2006-02-16 | 2011-06-21 | Vns Portfolio Llc | Computer system and method for executing port communications without interrupting the receiving computer |
| JP4866194B2 (ja) * | 2006-09-29 | 2012-02-01 | 富士通セミコンダクター株式会社 | 集積回路及びリコンフィギュラブル回路の入力データ制御方法 |
| US10007486B2 (en) * | 2008-12-01 | 2018-06-26 | Micron Technology, Inc. | Systems and methods to enable identification of different data sets |
| JP2011203935A (ja) * | 2010-03-25 | 2011-10-13 | Olympus Corp | 分散処理システム、制御部、演算部、分散処理方法、及びプログラム |
| AU2014222148A1 (en) * | 2013-03-01 | 2015-09-17 | Atonarp Inc. | Data processing device and control method therefor |
| IT201700062830A1 (it) | 2017-06-08 | 2018-12-08 | Stmicroelectronics Application Gmbh | Sistema di elaborazione, relativo circuito integrato, dispositivo e procedimento |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997003444A1 (en) * | 1995-07-10 | 1997-01-30 | Xilinx, Inc. | System comprising field programmable gate array and intelligent memory |
| JP2000324102A (ja) * | 1999-05-12 | 2000-11-24 | Toshiba Corp | 伝送装置および伝送システム |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06500655A (ja) * | 1990-10-03 | 1994-01-20 | スィンキング マシンズ コーポレーション | 並列コンピュータ・システム |
| TW330265B (en) * | 1994-11-22 | 1998-04-21 | Hitachi Ltd | Semiconductor apparatus |
| US5887146A (en) * | 1995-08-14 | 1999-03-23 | Data General Corporation | Symmetric multiprocessing computer with non-uniform memory access architecture |
| US5778439A (en) | 1995-08-18 | 1998-07-07 | Xilinx, Inc. | Programmable logic device with hierarchical confiquration and state storage |
| US5784636A (en) * | 1996-05-28 | 1998-07-21 | National Semiconductor Corporation | Reconfigurable computer architecture for use in signal processing applications |
| US5838165A (en) * | 1996-08-21 | 1998-11-17 | Chatter; Mukesh | High performance self modifying on-the-fly alterable logic FPGA, architecture and method |
| US6108760A (en) | 1997-10-31 | 2000-08-22 | Silicon Spice | Method and apparatus for position independent reconfiguration in a network of multiple context processing elements |
| US6122719A (en) * | 1997-10-31 | 2000-09-19 | Silicon Spice | Method and apparatus for retiming in a network of multiple context processing elements |
| DE19807872A1 (de) * | 1998-02-25 | 1999-08-26 | Pact Inf Tech Gmbh | Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl. |
| WO2000079394A1 (en) * | 1999-06-21 | 2000-12-28 | Bops Incorporated | Methods and apparatus for providing manifold array (manarray) program context switch with array reconfiguration control |
| US7380100B2 (en) | 2001-09-07 | 2008-05-27 | Ipflex Inc. | Data processing system and control method utilizing a plurality of date transfer means |
-
2002
- 2002-09-06 US US10/399,360 patent/US7380100B2/en not_active Expired - Lifetime
- 2002-09-06 JP JP2003527588A patent/JP4152319B2/ja not_active Expired - Fee Related
- 2002-09-06 WO PCT/JP2002/009108 patent/WO2003023602A1/ja not_active Ceased
- 2002-09-06 CN CNB028157214A patent/CN100397331C/zh not_active Expired - Lifetime
- 2002-09-06 CA CA2459411A patent/CA2459411C/en not_active Expired - Lifetime
- 2002-09-06 EP EP02767916A patent/EP1443392A4/en not_active Withdrawn
- 2002-09-06 KR KR1020047000161A patent/KR100960518B1/ko not_active Expired - Lifetime
- 2002-09-09 TW TW091120505A patent/TWI238317B/zh not_active IP Right Cessation
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997003444A1 (en) * | 1995-07-10 | 1997-01-30 | Xilinx, Inc. | System comprising field programmable gate array and intelligent memory |
| JP2000324102A (ja) * | 1999-05-12 | 2000-11-24 | Toshiba Corp | 伝送装置および伝送システム |
Non-Patent Citations (1)
| Title |
|---|
| See also references of EP1443392A4 * |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7941794B2 (en) | 2004-08-30 | 2011-05-10 | Sanyo Electric Co., Ltd. | Data flow graph processing method and processing apparatus provided with reconfigurable circuit |
| US8243084B2 (en) | 2004-12-20 | 2012-08-14 | Canon Kabushiki Kaisha | Apparatus and method for processing data |
| WO2006083137A1 (en) * | 2005-02-07 | 2006-08-10 | Samsung Electronics Co., Ltd. | Method of generating usage rule information for broadcast channel |
| JP2007241830A (ja) * | 2006-03-10 | 2007-09-20 | Fujitsu Ltd | リコンフィグラブル回路 |
| US8099540B2 (en) | 2006-03-10 | 2012-01-17 | Fujitsu Semiconductor Limited | Reconfigurable circuit |
| WO2009005089A1 (ja) * | 2007-07-03 | 2009-01-08 | Nec Corporation | データ暗号化/復号化処理方法およびデータ処理装置 |
| JP5487966B2 (ja) * | 2007-07-03 | 2014-05-14 | 日本電気株式会社 | データ暗号化/復号化処理方法およびデータ処理装置 |
| US8341394B2 (en) | 2007-07-03 | 2012-12-25 | Nec Corporation | Data encryption/decryption method and data processing device |
| JP2009157613A (ja) * | 2007-12-26 | 2009-07-16 | Fujitsu Microelectronics Ltd | リコンフィギュラブル回路 |
| WO2009096482A1 (ja) | 2008-01-31 | 2009-08-06 | Ipflex Inc. | 再構成可能なデバイス |
| JP2011154534A (ja) * | 2010-01-27 | 2011-08-11 | Fujitsu Semiconductor Ltd | リコンフィギュラブル回路および半導体集積回路 |
| US9720879B2 (en) | 2010-01-27 | 2017-08-01 | Cypress Semiconductor Corporation | Reconfigurable circuit having rows of a matrix of registers connected to corresponding ports and a semiconductor integrated circuit |
| JP2011170900A (ja) * | 2011-06-08 | 2011-09-01 | Canon Inc | データ処理装置及びその制御方法 |
| JP2018530025A (ja) * | 2015-06-26 | 2018-10-11 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated | 高速で再構成可能な回路及び高帯域幅のメモリインタフェースを用いたコンピュータアーキテクチャ |
| WO2018179739A1 (ja) * | 2017-03-28 | 2018-10-04 | 富士通株式会社 | 情報処理装置、情報処理方法及びプログラム |
| JP2018180805A (ja) * | 2017-04-10 | 2018-11-15 | 東芝デベロップメントエンジニアリング株式会社 | 管理装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1443392A1 (en) | 2004-08-04 |
| JP4152319B2 (ja) | 2008-09-17 |
| KR100960518B1 (ko) | 2010-06-03 |
| CA2459411C (en) | 2013-04-02 |
| CA2459411A1 (en) | 2003-03-20 |
| KR20040027871A (ko) | 2004-04-01 |
| CN1541355A (zh) | 2004-10-27 |
| EP1443392A4 (en) | 2007-08-15 |
| US7380100B2 (en) | 2008-05-27 |
| CN100397331C (zh) | 2008-06-25 |
| TWI238317B (en) | 2005-08-21 |
| JPWO2003023602A1 (ja) | 2004-12-24 |
| US20040030815A1 (en) | 2004-02-12 |
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