WO2003077115A3 - Control procedure selection - Google Patents

Control procedure selection Download PDF

Info

Publication number
WO2003077115A3
WO2003077115A3 PCT/US2003/004641 US0304641W WO03077115A3 WO 2003077115 A3 WO2003077115 A3 WO 2003077115A3 US 0304641 W US0304641 W US 0304641W WO 03077115 A3 WO03077115 A3 WO 03077115A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
control procedure
procedure selection
circuitry
procedure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/004641
Other languages
French (fr)
Other versions
WO2003077115A2 (en
Inventor
Paul Luse
Wolfgang Michel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP03711072A priority Critical patent/EP1481321A2/en
Priority to AU2003215256A priority patent/AU2003215256A1/en
Publication of WO2003077115A2 publication Critical patent/WO2003077115A2/en
Publication of WO2003077115A3 publication Critical patent/WO2003077115A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Abstract

In one embodiment of the present invention, a process that uses a first processor is provided. The process includes the operation of blocking by the first processor of completion by a second processor of a configuration cycle. The process also includes the operation of selecting by the first processor of one procedure from a plurality of procedures that are associated with respective types of circuitry that may be used to permit the first processor to control a device. The one procedure is associated with one of the respective types of circuitry that is actually available to be used by the first processor.
PCT/US2003/004641 2002-03-04 2003-02-13 Control procedure selection Ceased WO2003077115A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP03711072A EP1481321A2 (en) 2002-03-04 2003-02-13 Control procedure selection
AU2003215256A AU2003215256A1 (en) 2002-03-04 2003-02-13 Control procedure selection

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/090,944 US6922746B2 (en) 2002-03-04 2002-03-04 Data processing system preventing configuration cycles to permit control procedure selection for access to attached devices
US10/090,944 2002-03-04

Publications (2)

Publication Number Publication Date
WO2003077115A2 WO2003077115A2 (en) 2003-09-18
WO2003077115A3 true WO2003077115A3 (en) 2004-06-03

Family

ID=27804079

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/004641 Ceased WO2003077115A2 (en) 2002-03-04 2003-02-13 Control procedure selection

Country Status (6)

Country Link
US (2) US6922746B2 (en)
EP (1) EP1481321A2 (en)
CN (1) CN100549953C (en)
AU (1) AU2003215256A1 (en)
TW (1) TWI276962B (en)
WO (1) WO2003077115A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060129758A1 (en) * 2004-12-13 2006-06-15 Lsi Logic Corporation Zero channel raid architecture
KR20150017574A (en) * 2013-08-07 2015-02-17 에스케이하이닉스 주식회사 Sense amplifier driving device and semiconductor device including the same
CN112559075B (en) * 2020-12-18 2022-02-01 核工业西南物理研究院 IOC remote control system
CN119226207B (en) * 2024-11-28 2025-04-25 苏州元脑智能科技有限公司 Device, server and method for implementing hot removal of expansion equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260094B1 (en) * 1995-06-15 2001-07-10 Intel Corporation Method and apparatus providing programmable decode modes for secondary PCI bus interfaces

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5359715A (en) * 1991-09-16 1994-10-25 Ncr Corporation Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces
US6179489B1 (en) * 1997-04-04 2001-01-30 Texas Instruments Incorporated Devices, methods, systems and software products for coordination of computer main microprocessor and second microprocessor coupled thereto
US6298370B1 (en) * 1997-04-04 2001-10-02 Texas Instruments Incorporated Computer operating process allocating tasks between first and second processors at run time based upon current processor load
KR100241596B1 (en) * 1997-11-24 2000-02-01 윤종용 A computer system for pursuing raid by using on-board scsi
US6684282B1 (en) * 2001-01-26 2004-01-27 Dell Products L.P. System and method for adding an internal RAID controller
US6915365B2 (en) * 2002-03-22 2005-07-05 Intel Corporation Mechanism for PCI I/O-initiated configuration cycles

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6260094B1 (en) * 1995-06-15 2001-07-10 Intel Corporation Method and apparatus providing programmable decode modes for secondary PCI bus interfaces

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
A. TISCHENKO: "Zero-Channel RAID. The economic approach", COMPUTER REVIEW, 30 January 2002 (2002-01-30), pages 1 - 4, XP002266763, Retrieved from the Internet <URL:http://www.itc.ua/article.phtml?ID=8820> [retrieved on 20040102] *
INTEL CORP.: "DK440LX Motherboard. Technical Product Specification", October 1997, INTEL CORPORATION, INTEL CORPORATION, XP002274571 *
INTEL CORP.: "MROMB Design Considerations Using the Intel 80303 I/O Processor. Application Note.", September 2001, INTEL CORPORATION, XP002274842 *
R. RUSSELL: "BIOS Basics", 5 June 2001 (2001-06-05), pages 1 - 1, XP002266574, Retrieved from the Internet <URL:http://web.archive.org/web/20010605201959/peripherals.about.com/compute/peripherals/library/weekly/aa052201a.htm> [retrieved on 20040112] *

Also Published As

Publication number Publication date
US6922746B2 (en) 2005-07-26
US20050125611A1 (en) 2005-06-09
TW200304069A (en) 2003-09-16
WO2003077115A2 (en) 2003-09-18
US20030167359A1 (en) 2003-09-04
CN100549953C (en) 2009-10-14
CN1643497A (en) 2005-07-20
US7089358B2 (en) 2006-08-08
EP1481321A2 (en) 2004-12-01
AU2003215256A8 (en) 2003-09-22
AU2003215256A1 (en) 2003-09-22
TWI276962B (en) 2007-03-21

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