WO2003083669A3 - Inexact addressable digital memory - Google Patents

Inexact addressable digital memory Download PDF

Info

Publication number
WO2003083669A3
WO2003083669A3 PCT/GB2002/004650 GB0204650W WO03083669A3 WO 2003083669 A3 WO2003083669 A3 WO 2003083669A3 GB 0204650 W GB0204650 W GB 0204650W WO 03083669 A3 WO03083669 A3 WO 03083669A3
Authority
WO
WIPO (PCT)
Prior art keywords
address
memory
identifier
bits
inexact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/GB2002/004650
Other languages
French (fr)
Other versions
WO2003083669A2 (en
Inventor
Stephen Byram Furber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cogniscience Ltd
Original Assignee
Cogniscience Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cogniscience Ltd filed Critical Cogniscience Ltd
Priority to US10/509,086 priority Critical patent/US7512572B2/en
Priority to JP2003581025A priority patent/JP4209335B2/en
Priority to DE60213007T priority patent/DE60213007T2/en
Priority to EP02767715A priority patent/EP1488425B1/en
Priority to AU2002330642A priority patent/AU2002330642B2/en
Priority to CA2479944A priority patent/CA2479944C/en
Publication of WO2003083669A2 publication Critical patent/WO2003083669A2/en
Publication of WO2003083669A3 publication Critical patent/WO2003083669A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Error Detection And Correction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Communication Control (AREA)
  • Holo Graphy (AREA)
  • Magnetically Actuated Valves (AREA)

Abstract

A memory configuration for use in a computer system, the memory comprising a plurality of address decoders each of which is allocated an identifier having a predetermined number of bits, each bit having first and second selectable states, and a data memory having a plurality of word lines of predetermined length, each of the said address decoders being activatable to select one of the plurality of word lines, and the address decoders comprising means to receive an input address having a predetermined number of bits and means to compare the identifier of an address decoder with the input address wherein the memory further comprises means to activate an address decoder if at least a predetermined minimum number of bits set to the first selectable state in the input address correspond to bits set to the first selectable state in the decoder identifier.
PCT/GB2002/004650 2002-03-28 2002-10-14 Inexact addressable digital memory Ceased WO2003083669A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
US10/509,086 US7512572B2 (en) 2002-03-28 2002-10-14 Digital memory
JP2003581025A JP4209335B2 (en) 2002-03-28 2002-10-14 Digital memory
DE60213007T DE60213007T2 (en) 2002-03-28 2002-10-14 BAD ADDRESSABLE DIGITAL MEMORY
EP02767715A EP1488425B1 (en) 2002-03-28 2002-10-14 Inexact addressable digital memory
AU2002330642A AU2002330642B2 (en) 2002-03-28 2002-10-14 Inexact addressable digital memory
CA2479944A CA2479944C (en) 2002-03-28 2002-10-14 Digital memory

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0207372.4 2002-03-28
GBGB0207372.4A GB0207372D0 (en) 2002-03-28 2002-03-28 Digital memory

Publications (2)

Publication Number Publication Date
WO2003083669A2 WO2003083669A2 (en) 2003-10-09
WO2003083669A3 true WO2003083669A3 (en) 2003-12-31

Family

ID=9933933

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB2002/004650 Ceased WO2003083669A2 (en) 2002-03-28 2002-10-14 Inexact addressable digital memory

Country Status (10)

Country Link
US (1) US7512572B2 (en)
EP (1) EP1488425B1 (en)
JP (1) JP4209335B2 (en)
AT (1) ATE332564T1 (en)
AU (1) AU2002330642B2 (en)
CA (1) CA2479944C (en)
DE (1) DE60213007T2 (en)
ES (1) ES2268084T3 (en)
GB (1) GB0207372D0 (en)
WO (1) WO2003083669A2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0524126D0 (en) * 2005-11-26 2006-01-04 Cogniscience Ltd Data transmission method
WO2008021554A2 (en) * 2006-08-18 2008-02-21 Board Of Supervisors Of Louisiana State University And Agricultural And Mechanical College A configurable decoder with applications in fpgas
US20100114760A1 (en) * 2008-08-04 2010-05-06 Raj Sundarasen Online interactive issued account acquired transaction information management
US8473439B2 (en) 2010-12-08 2013-06-25 International Business Machines Corporation Integrate and fire electronic neurons
US8812414B2 (en) 2011-05-31 2014-08-19 International Business Machines Corporation Low-power event-driven neural computing architecture in neural networks
US8909576B2 (en) 2011-09-16 2014-12-09 International Business Machines Corporation Neuromorphic event-driven neural computing architecture in a scalable neural network
US8891872B2 (en) 2011-12-16 2014-11-18 General Electric Company System and method for identifying physical markings on objects
US9235499B2 (en) 2011-12-16 2016-01-12 General Electric Company System and method for identifying a character-of-interest
US9558443B2 (en) 2013-08-02 2017-01-31 International Business Machines Corporation Dual deterministic and stochastic neurosynaptic core circuit
EP3089080A1 (en) * 2015-04-27 2016-11-02 Universität Zürich Networks and hierarchical routing fabrics with heterogeneous memory structures for scalable event-driven computing systems
US10169701B2 (en) * 2015-05-26 2019-01-01 International Business Machines Corporation Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models
TWI653584B (en) * 2017-09-15 2019-03-11 中原大學 Method of judging neural network with non-volatile memory cells
WO2023041919A1 (en) * 2021-09-17 2023-03-23 The University Of Manchester Computer memory

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990004830A1 (en) * 1988-10-20 1990-05-03 Universities Space Research Association Method and apparatus for a sparse distributed memory system
EP0626650A1 (en) * 1993-05-28 1994-11-30 Texas Instruments Incorporated Devices, systems and methods for implementing a Kanerva memory
US5457408A (en) * 1994-11-23 1995-10-10 At&T Corp. Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended for that FPGA
US5829009A (en) * 1993-01-07 1998-10-27 Texas Instruments Incorporated Method and device for storing and recalling information implementing a kanerva memory system

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990077091A (en) * 1996-01-25 1999-10-25 피터 토마스 Semiconductor neurons with variable input weights
US6226710B1 (en) * 1997-11-14 2001-05-01 Utmc Microelectronic Systems Inc. Content addressable memory (CAM) engine
FI107767B (en) * 1998-05-26 2001-09-28 Nokia Mobile Phones Ltd Procedure and arrangement for realizing convolutional decoding
US6460112B1 (en) * 1999-02-23 2002-10-01 Netlogic Microsystems, Llc Method and apparatus for determining a longest prefix match in a content addressable memory device
US7043673B1 (en) * 2001-08-03 2006-05-09 Netlogic Microsystems, Inc. Content addressable memory with priority-biased error detection sequencing
US6597595B1 (en) * 2001-08-03 2003-07-22 Netlogic Microsystems, Inc. Content addressable memory with error detection signaling

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990004830A1 (en) * 1988-10-20 1990-05-03 Universities Space Research Association Method and apparatus for a sparse distributed memory system
US5829009A (en) * 1993-01-07 1998-10-27 Texas Instruments Incorporated Method and device for storing and recalling information implementing a kanerva memory system
EP0626650A1 (en) * 1993-05-28 1994-11-30 Texas Instruments Incorporated Devices, systems and methods for implementing a Kanerva memory
US5457408A (en) * 1994-11-23 1995-10-10 At&T Corp. Method and apparatus for verifying whether a bitstream received by a field programmable gate array (FPGA) is intended for that FPGA

Also Published As

Publication number Publication date
DE60213007T2 (en) 2007-02-08
AU2002330642B2 (en) 2008-12-04
EP1488425A2 (en) 2004-12-22
JP2005521940A (en) 2005-07-21
WO2003083669A2 (en) 2003-10-09
US7512572B2 (en) 2009-03-31
CA2479944A1 (en) 2003-10-09
ES2268084T3 (en) 2007-03-16
JP4209335B2 (en) 2009-01-14
ATE332564T1 (en) 2006-07-15
GB0207372D0 (en) 2002-05-08
US20050281116A1 (en) 2005-12-22
EP1488425B1 (en) 2006-07-05
AU2002330642A1 (en) 2003-10-13
DE60213007D1 (en) 2006-08-17
CA2479944C (en) 2013-04-23

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