WO2003107199A3 - BUS SYSTEM, STATION USED IN A BUS SYSTEM, AND BUS INTERFACE - Google Patents

BUS SYSTEM, STATION USED IN A BUS SYSTEM, AND BUS INTERFACE Download PDF

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Publication number
WO2003107199A3
WO2003107199A3 PCT/IB2003/002196 IB0302196W WO03107199A3 WO 2003107199 A3 WO2003107199 A3 WO 2003107199A3 IB 0302196 W IB0302196 W IB 0302196W WO 03107199 A3 WO03107199 A3 WO 03107199A3
Authority
WO
WIPO (PCT)
Prior art keywords
station
requests
request
bus
format
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2003/002196
Other languages
French (fr)
Other versions
WO2003107199A2 (en
Inventor
Jerome Tjia
Bart Vertenten
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to AU2003228060A priority Critical patent/AU2003228060A1/en
Priority to EP03725529A priority patent/EP1516261B1/en
Priority to US10/517,513 priority patent/US7383372B2/en
Priority to JP2004513949A priority patent/JP4444101B2/en
Priority to DE60322702T priority patent/DE60322702D1/en
Priority to KR10-2004-7020256A priority patent/KR20050010906A/en
Publication of WO2003107199A2 publication Critical patent/WO2003107199A2/en
Publication of WO2003107199A3 publication Critical patent/WO2003107199A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/102—Program control for peripheral devices where the program performs an interfacing function, e.g. device driver

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)
  • Traffic Control Systems (AREA)

Abstract

L'invention concerne un système de bus comprenant une première station et une seconde station couplées par un bus de manière à transférer des signaux. Ce bus est élaboré pour fonctionner selon un protocole, dans lequel ladite première station envoie de manière répétée des demandes de données à la seconde station. Ce protocole comporte un premier mode de transfert des demandes dans un premier format de demande à une première vitesse de communication et au moins un second mode de transfert desdites demandes dans un second format de demande à une seconde vitesse. Ladite seconde station est conçue pour recevoir des demandes dans un mode sélectionné parmi un groupe de modes comprenant lesdits premier et second modes, et pour donner une première indication à la première station, si elle est installée pour fonctionner selon le premier mode et une seconde indication si elle est installée pour fonctionner selon le second mode. La première station comprend un processeur, un contrôleur et un traducteur. Le processeur fonctionne pour engendrer des propriétés de demandes dans le premier format de demande. Le contrôleur fonctionne pour produire les demandes dans le premier format de demande à partir des propriétés des demandes, ainsi que pour transmettre la demande dans le premier format à la seconde station, suite à la détection de la première indication et pour envoyer les demandes au traducteur suite à la détection de la seconde indication, ledit traducteur fonctionnant pour transmettre les demandes dans le second format à la seconde station.A bus system includes a first station and a second station coupled by a bus to transfer signals. This bus is designed to operate according to a protocol, in which said first station repeatedly sends requests for data to the second station. This protocol includes a first mode of transferring requests in a first request format at a first communication speed and at least a second mode of transferring said requests in a second request format at a second speed. Said second station is adapted to receive requests in a mode selected from a group of modes comprising said first and second modes, and to give a first indication to the first station, if it is installed to operate in the first mode and a second indication if it is installed to operate in the second mode. The first station includes a processor, a controller and a translator. The processor operates to generate request properties in the first request format. The controller operates to generate the requests in the first request format from the request properties, as well as to transmit the request in the first format to the second station, following the detection of the first indication and to send the requests to the translator. following the detection of the second indication, said translator operating to transmit the requests in the second format to the second station.

PCT/IB2003/002196 2002-06-12 2003-05-21 Bus system, station for use in a bus system, and bus interface Ceased WO2003107199A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
AU2003228060A AU2003228060A1 (en) 2002-06-12 2003-05-21 Bus system, station for use in a bus system, and bus interface
EP03725529A EP1516261B1 (en) 2002-06-12 2003-05-21 Bus system, station for use in a bus system, and bus interface
US10/517,513 US7383372B2 (en) 2002-06-12 2003-05-21 Bus system, station for use in a bus system, and bus interface
JP2004513949A JP4444101B2 (en) 2002-06-12 2003-05-21 Bus system, station for use in the bus system, and bus interface
DE60322702T DE60322702D1 (en) 2002-06-12 2003-05-21 BUS SYSTEM, STATION FOR USE IN A BUS SYSTEM AND BUS INTERFACE
KR10-2004-7020256A KR20050010906A (en) 2002-06-12 2003-05-21 Bus system, station for use in a bus system, and bus interface

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SGPCT/SG02/00162 2002-06-12
SG0200162 2002-06-12

Publications (2)

Publication Number Publication Date
WO2003107199A2 WO2003107199A2 (en) 2003-12-24
WO2003107199A3 true WO2003107199A3 (en) 2004-03-18

Family

ID=29729281

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/002196 Ceased WO2003107199A2 (en) 2002-06-12 2003-05-21 Bus system, station for use in a bus system, and bus interface

Country Status (10)

Country Link
US (1) US7383372B2 (en)
EP (1) EP1516261B1 (en)
JP (1) JP4444101B2 (en)
KR (1) KR20050010906A (en)
CN (1) CN100343840C (en)
AT (1) ATE403906T1 (en)
AU (1) AU2003228060A1 (en)
DE (1) DE60322702D1 (en)
TW (1) TWI313814B (en)
WO (1) WO2003107199A2 (en)

Families Citing this family (15)

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Publication number Priority date Publication date Assignee Title
DE10239814B4 (en) * 2002-08-29 2008-06-05 Advanced Micro Devices, Inc., Sunnyvale Extended test mode support for host controllers
WO2005125093A2 (en) * 2004-06-15 2005-12-29 Koninklijke Philips Electronics N.V. Bus controller for handling split transactions
DE102004057756B4 (en) * 2004-11-30 2009-08-06 Advanced Micro Devices Inc., Sunnyvale USB control device with OTG control unit
US8103813B2 (en) 2005-07-08 2012-01-24 Broadcom Corporation Method and system for hardware based implementation of USB 1.1 over a high speed link
JP4779955B2 (en) * 2006-01-06 2011-09-28 富士通株式会社 Packet processing apparatus and packet processing method
US7984228B2 (en) * 2006-02-28 2011-07-19 Microsoft Corporation Device connection routing for controller
ES2329091T3 (en) * 2007-05-24 2009-11-20 Research In Motion Limited SYSTEM AND METHOD FOR THE INTERCONNECTION OF AN ELECTRONIC DEVICE WITH A MAIN COMPUTER SYSTEM.
US7631126B2 (en) 2007-05-24 2009-12-08 Research In Motion Limited System and method for interfacing an electronic device with a host system
US7840733B2 (en) * 2008-07-03 2010-11-23 Intel Corporation Power optimized dynamic port association
KR101256942B1 (en) * 2009-10-06 2013-04-25 한국전자통신연구원 Method of serial bus communication and bus interface device for the same
CN101788972B (en) * 2010-03-08 2012-07-11 威盛电子股份有限公司 A system and method for data transmission
CN101854314B (en) * 2010-06-09 2013-11-06 中兴通讯股份有限公司 Home gateway and method for adapting universal serial bus wireless data card
JP5874739B2 (en) 2011-12-16 2016-03-02 株式会社村田製作所 Touch operation input device
US11087801B1 (en) 2020-02-06 2021-08-10 Micron Technology, Inc. Configuring a host interface of a memory device based on mode of operation
US11243896B2 (en) * 2020-03-25 2022-02-08 Micron Technology, Inc. Multiple pin configurations of memory devices

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259706B1 (en) * 1997-10-23 2001-07-10 Fujitsu Limited Communication controlling apparatus and recording medium for recording communication controlling programs

Family Cites Families (9)

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Publication number Priority date Publication date Assignee Title
US6611552B2 (en) * 1999-01-28 2003-08-26 Intel Corporation Universal serial bus transceiver and associated methods
US6901471B2 (en) * 2001-03-01 2005-05-31 Synopsys, Inc. Transceiver macrocell architecture allowing upstream and downstream operation
US6775733B2 (en) * 2001-06-04 2004-08-10 Winbond Electronics Corp. Interface for USB host controller and root hub
US6721815B1 (en) * 2001-09-27 2004-04-13 Intel Corporation Method and apparatus for iTD scheduling
TW538364B (en) * 2001-12-10 2003-06-21 Via Tech Inc USB control circuit capable of automatically switching paths
US7000057B1 (en) * 2002-02-11 2006-02-14 Cypress Semiconductor Corp. Method and apparatus for adding OTG dual role device capability to a USB peripheral
DE10224163B4 (en) * 2002-05-31 2005-05-04 Advanced Micro Devices, Inc., Sunnyvale Transaction duration management in a USB host controller
DE10234991B4 (en) * 2002-07-31 2008-07-31 Advanced Micro Devices, Inc., Sunnyvale Host controller diagnostics for a serial bus
US6959355B2 (en) * 2003-02-24 2005-10-25 Standard Microsystems Corporation Universal serial bus hub with shared high speed handler

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6259706B1 (en) * 1997-10-23 2001-07-10 Fujitsu Limited Communication controlling apparatus and recording medium for recording communication controlling programs

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
"On-The-Go supplement to the USB 2.0 specifition, Revision 1,0", UNIVERSAL SERIAL BUS (USB), XX, XX, PAGE(S) 1-66,1-3,2-6, XP002952944 *
ANONYMOUS: "Enhanced Host Controller Interface Specification for Universal Serial Bus, Rev. 1.0", 12 March 2002, XP002255364 *

Also Published As

Publication number Publication date
EP1516261A2 (en) 2005-03-23
ATE403906T1 (en) 2008-08-15
DE60322702D1 (en) 2008-09-18
CN1659533A (en) 2005-08-24
TWI313814B (en) 2009-08-21
AU2003228060A1 (en) 2003-12-31
TW200404215A (en) 2004-03-16
WO2003107199A2 (en) 2003-12-24
JP4444101B2 (en) 2010-03-31
US7383372B2 (en) 2008-06-03
KR20050010906A (en) 2005-01-28
US20050216650A1 (en) 2005-09-29
EP1516261B1 (en) 2008-08-06
JP2005529430A (en) 2005-09-29
CN100343840C (en) 2007-10-17

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