WO2004005946A3 - Electronic circuit with test unit for testing interconnects - Google Patents
Electronic circuit with test unit for testing interconnects Download PDFInfo
- Publication number
- WO2004005946A3 WO2004005946A3 PCT/IB2003/002957 IB0302957W WO2004005946A3 WO 2004005946 A3 WO2004005946 A3 WO 2004005946A3 IB 0302957 W IB0302957 W IB 0302957W WO 2004005946 A3 WO2004005946 A3 WO 2004005946A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electronic circuit
- test unit
- nodes
- test
- selection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/022—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in I/O circuitry
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318544—Scanning methods, algorithms and patterns
- G01R31/31855—Interconnection testing, e.g. crosstalk, shortcircuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE60323232T DE60323232D1 (en) | 2002-07-08 | 2003-06-20 | ELECTRONIC CIRCUIT WITH INSPECTION UNIT FOR VERIFYING CONNECTING LINES |
| JP2004519104A JP4176716B2 (en) | 2002-07-08 | 2003-06-20 | Electronic circuit with test unit |
| US10/520,198 US7199573B2 (en) | 2002-07-08 | 2003-06-20 | Electronic circuit with test unit |
| EP03738449A EP1521974B1 (en) | 2002-07-08 | 2003-06-20 | Electronic circuit with test unit for testing interconnects |
| AU2003244975A AU2003244975A1 (en) | 2002-07-08 | 2003-06-20 | Electronic circuit with test unit for testing interconnects |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP02077733.0 | 2002-07-08 | ||
| EP02077733 | 2002-07-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2004005946A2 WO2004005946A2 (en) | 2004-01-15 |
| WO2004005946A3 true WO2004005946A3 (en) | 2004-06-03 |
Family
ID=30011175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2003/002957 Ceased WO2004005946A2 (en) | 2002-07-08 | 2003-06-20 | Electronic circuit with test unit for testing interconnects |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US7199573B2 (en) |
| EP (1) | EP1521974B1 (en) |
| JP (1) | JP4176716B2 (en) |
| CN (1) | CN100401086C (en) |
| AT (1) | ATE406582T1 (en) |
| AU (1) | AU2003244975A1 (en) |
| DE (1) | DE60323232D1 (en) |
| TW (1) | TWI287638B (en) |
| WO (1) | WO2004005946A2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7567521B2 (en) * | 2006-06-06 | 2009-07-28 | Litepoint Corp. | Apparatus for capturing multiple data packets in a data signal for analysis |
| US20090021383A1 (en) * | 2007-07-16 | 2009-01-22 | International Business Machines Corporation | Method for redundant control of service indicator leds |
| JP4365433B2 (en) * | 2007-09-11 | 2009-11-18 | Okiセミコンダクタ株式会社 | Semiconductor integrated circuit |
| US7928755B2 (en) * | 2008-02-21 | 2011-04-19 | Verigy (Singapore) Pte. Ltd. | Methods and apparatus that selectively use or bypass a remote pin electronics block to test at least one device under test |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS635272A (en) * | 1986-06-25 | 1988-01-11 | Fujitsu Ten Ltd | Logic circuit device with output abnormality detecting function |
| WO1999039218A2 (en) * | 1998-02-02 | 1999-08-05 | Koninklijke Philips Electronics N.V. | Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit |
| US6208571B1 (en) * | 1999-04-30 | 2001-03-27 | Fujitsu Limited | Semiconductor memory device, circuit board mounted with semiconductor memory device, and method for testing interconnection between a semiconductor memory device with a circuit board |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4556840A (en) * | 1981-10-30 | 1985-12-03 | Honeywell Information Systems Inc. | Method for testing electronic assemblies |
| US4575648A (en) * | 1983-12-23 | 1986-03-11 | At&T Bell Laboratories | Complementary field effect transistor EXCLUSIVE OR logic gates |
| US4789951A (en) * | 1986-05-16 | 1988-12-06 | Advanced Micro Devices, Inc. | Programmable array logic cell |
| ATE125386T1 (en) * | 1989-05-31 | 1995-08-15 | Siemens Ag | METHOD AND DEVICE FOR INTERNAL PARALLEL TESTING OF SEMICONDUCTOR MEMORY. |
| GB2244364B (en) * | 1990-05-24 | 1994-03-09 | Coin Controls | Coin discrimination apparatus |
| US5241265A (en) * | 1992-03-26 | 1993-08-31 | Northern Telecom Limited | Logic function circuit with an array of data stores and their circuit testing |
| JP3865828B2 (en) * | 1995-11-28 | 2007-01-10 | 株式会社ルネサステクノロジ | Semiconductor memory device |
| JPH10303737A (en) * | 1997-04-23 | 1998-11-13 | Mitsubishi Electric Corp | 3-input exclusive NOR circuit |
| JP4044663B2 (en) * | 1998-02-25 | 2008-02-06 | 富士通株式会社 | Semiconductor device |
| TW444127B (en) * | 1999-08-20 | 2001-07-01 | Taiwan Semiconductor Mfg | Comparing circuit, testing circuit and testing method for the parallel test of DRAM devices |
-
2003
- 2003-06-20 AT AT03738449T patent/ATE406582T1/en not_active IP Right Cessation
- 2003-06-20 WO PCT/IB2003/002957 patent/WO2004005946A2/en not_active Ceased
- 2003-06-20 CN CNB038157551A patent/CN100401086C/en not_active Expired - Fee Related
- 2003-06-20 US US10/520,198 patent/US7199573B2/en not_active Expired - Lifetime
- 2003-06-20 AU AU2003244975A patent/AU2003244975A1/en not_active Abandoned
- 2003-06-20 DE DE60323232T patent/DE60323232D1/en not_active Expired - Lifetime
- 2003-06-20 JP JP2004519104A patent/JP4176716B2/en not_active Expired - Fee Related
- 2003-06-20 EP EP03738449A patent/EP1521974B1/en not_active Expired - Lifetime
- 2003-07-04 TW TW092118363A patent/TWI287638B/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS635272A (en) * | 1986-06-25 | 1988-01-11 | Fujitsu Ten Ltd | Logic circuit device with output abnormality detecting function |
| WO1999039218A2 (en) * | 1998-02-02 | 1999-08-05 | Koninklijke Philips Electronics N.V. | Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit |
| EP0979418A2 (en) * | 1998-02-02 | 2000-02-16 | Koninklijke Philips Electronics N.V. | Circuit with interconnect test unit and a method of testing interconnects between a first and a second electronic circuit |
| US6208571B1 (en) * | 1999-04-30 | 2001-03-27 | Fujitsu Limited | Semiconductor memory device, circuit board mounted with semiconductor memory device, and method for testing interconnection between a semiconductor memory device with a circuit board |
Non-Patent Citations (2)
| Title |
|---|
| BIEWENGA A ET AL: "STATIC COMPONENT INTERCONNECT TEST TECHNOLOGY (SCITT). A NEW TECHNOLOGY FOR ASSEMBLY TESTING", PROCEEDINGS INTERNATIONAL TEST CONFERENCE 1999. ITC'99. ATLANTIC CITY, NJ, SEPT. 28 - 30, 1999, INTERNATIONAL TEST CONFERENCE, NEW YORK, NY: IEEE, US, vol. CONF. 30, September 1999 (1999-09-01), pages 439 - 448, XP000928860, ISBN: 0-7803-5754-X * |
| PATENT ABSTRACTS OF JAPAN vol. 012, no. 203 (P - 715) 11 June 1988 (1988-06-11) * |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4176716B2 (en) | 2008-11-05 |
| CN1666110A (en) | 2005-09-07 |
| WO2004005946A2 (en) | 2004-01-15 |
| AU2003244975A8 (en) | 2004-01-23 |
| DE60323232D1 (en) | 2008-10-09 |
| TW200403444A (en) | 2004-03-01 |
| ATE406582T1 (en) | 2008-09-15 |
| EP1521974A2 (en) | 2005-04-13 |
| US7199573B2 (en) | 2007-04-03 |
| EP1521974B1 (en) | 2008-08-27 |
| TWI287638B (en) | 2007-10-01 |
| US20060061376A1 (en) | 2006-03-23 |
| AU2003244975A1 (en) | 2004-01-23 |
| CN100401086C (en) | 2008-07-09 |
| JP2005532548A (en) | 2005-10-27 |
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