WO2004010316A3 - Method, system, and program for handling input/output commands - Google Patents

Method, system, and program for handling input/output commands Download PDF

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Publication number
WO2004010316A3
WO2004010316A3 PCT/US2003/022941 US0322941W WO2004010316A3 WO 2004010316 A3 WO2004010316 A3 WO 2004010316A3 US 0322941 W US0322941 W US 0322941W WO 2004010316 A3 WO2004010316 A3 WO 2004010316A3
Authority
WO
WIPO (PCT)
Prior art keywords
target device
program
initiator
handling input
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/022941
Other languages
French (fr)
Other versions
WO2004010316A2 (en
Inventor
David Smith
Sailesh Bissessur
Richard Mackey
Mark Schmisseur
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to EP03765941A priority Critical patent/EP1573559B1/en
Priority to AT03765941T priority patent/ATE433584T1/en
Priority to DE60327945T priority patent/DE60327945D1/en
Priority to AU2003259210A priority patent/AU2003259210A1/en
Publication of WO2004010316A2 publication Critical patent/WO2004010316A2/en
Publication of WO2004010316A3 publication Critical patent/WO2004010316A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Programmable Controllers (AREA)

Abstract

Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. To device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
PCT/US2003/022941 2002-07-24 2003-07-23 Method, system, and program for handling input/output commands Ceased WO2004010316A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP03765941A EP1573559B1 (en) 2002-07-24 2003-07-23 Method, system, and program for handling input/output commands
AT03765941T ATE433584T1 (en) 2002-07-24 2003-07-23 METHOD, SYSTEM AND PROGRAM FOR HANDLING INPUT/OUTPUT COMMANDS
DE60327945T DE60327945D1 (en) 2002-07-24 2003-07-23 METHOD, SYSTEM AND PROGRAM FOR HANDLING INPUT / OUTPUT COMMANDS
AU2003259210A AU2003259210A1 (en) 2002-07-24 2003-07-23 Method, system, and program for handling input/output commands

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/205,663 US7130933B2 (en) 2002-07-24 2002-07-24 Method, system, and program for handling input/output commands
US10/205,663 2002-07-24

Publications (2)

Publication Number Publication Date
WO2004010316A2 WO2004010316A2 (en) 2004-01-29
WO2004010316A3 true WO2004010316A3 (en) 2004-05-27

Family

ID=30770115

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/022941 Ceased WO2004010316A2 (en) 2002-07-24 2003-07-23 Method, system, and program for handling input/output commands

Country Status (8)

Country Link
US (2) US7130933B2 (en)
EP (1) EP1573559B1 (en)
CN (1) CN100481043C (en)
AT (1) ATE433584T1 (en)
AU (1) AU2003259210A1 (en)
DE (1) DE60327945D1 (en)
TW (1) TWI298838B (en)
WO (1) WO2004010316A2 (en)

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US8140826B2 (en) * 2007-05-29 2012-03-20 International Business Machines Corporation Executing a gather operation on a parallel computer
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US20090006663A1 (en) * 2007-06-27 2009-01-01 Archer Charles J Direct Memory Access ('DMA') Engine Assisted Local Reduction
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US8422402B2 (en) 2008-04-01 2013-04-16 International Business Machines Corporation Broadcasting a message in a parallel computer
US8484440B2 (en) 2008-05-21 2013-07-09 International Business Machines Corporation Performing an allreduce operation on a plurality of compute nodes of a parallel computer
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US8161268B2 (en) * 2008-05-21 2012-04-17 International Business Machines Corporation Performing an allreduce operation on a plurality of compute nodes of a parallel computer
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US9424087B2 (en) 2010-04-29 2016-08-23 International Business Machines Corporation Optimizing collective operations
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US8489859B2 (en) 2010-05-28 2013-07-16 International Business Machines Corporation Performing a deterministic reduction operation in a compute node organized into a branched tree topology
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US9626127B2 (en) * 2010-07-21 2017-04-18 Nxp Usa, Inc. Integrated circuit device, data storage array system and method therefor
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Also Published As

Publication number Publication date
ATE433584T1 (en) 2009-06-15
US7130933B2 (en) 2006-10-31
TW200406680A (en) 2004-05-01
CN1864145A (en) 2006-11-15
TWI298838B (en) 2008-07-11
EP1573559A2 (en) 2005-09-14
US7464199B2 (en) 2008-12-09
US20040019711A1 (en) 2004-01-29
EP1573559B1 (en) 2009-06-10
US20060168359A1 (en) 2006-07-27
CN100481043C (en) 2009-04-22
WO2004010316A2 (en) 2004-01-29
DE60327945D1 (en) 2009-07-23
AU2003259210A1 (en) 2004-02-09

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