WO2004015759A3 - A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine - Google Patents

A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine Download PDF

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Publication number
WO2004015759A3
WO2004015759A3 PCT/IB2003/003640 IB0303640W WO2004015759A3 WO 2004015759 A3 WO2004015759 A3 WO 2004015759A3 IB 0303640 W IB0303640 W IB 0303640W WO 2004015759 A3 WO2004015759 A3 WO 2004015759A3
Authority
WO
WIPO (PCT)
Prior art keywords
thickness
layer
correcting
preparing
thin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2003/003640
Other languages
French (fr)
Other versions
WO2004015759A2 (en
Inventor
Bruno Ghyselen
Cecile Aulnette
Benedite Osternaud
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from FR0210209A external-priority patent/FR2843487B1/en
Priority claimed from FR0210208A external-priority patent/FR2843486B1/en
Application filed by Soitec SA filed Critical Soitec SA
Priority to JP2004527229A priority Critical patent/JP4684650B2/en
Priority to AU2003263391A priority patent/AU2003263391A1/en
Priority to EP03784416A priority patent/EP1547143B1/en
Priority to AT03784416T priority patent/ATE484847T1/en
Priority to DE60334555T priority patent/DE60334555D1/en
Publication of WO2004015759A2 publication Critical patent/WO2004015759A2/en
Publication of WO2004015759A3 publication Critical patent/WO2004015759A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H10P14/6309—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors of silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6322—Formation by thermal treatments
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/23—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by multiple measurements, corrections, marking or sorting processes

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Formation Of Insulating Films (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Physical Vapour Deposition (AREA)
  • Length Measuring Devices With Unspecified Measuring Means (AREA)

Abstract

The invention relates to a method of preparing a thin layer of semiconductor material, the method including a step (1050') of correcting the thickness of the layer, said step of correcting thickness of the layer itself comprising the following operations: acquiring a measured thickness profile of the layer; deducing thickness correction specifications from the measured thickness profile; and correcting the thickness of the layer in accordance with said specifications; the method being characterized in that thickness correction implements a technique which simultaneously treats the entire surface of the layer, while locally and selectively adapt layer thickness in different regions of the layer surface. The invention also relates to an associated machine.
PCT/IB2003/003640 2002-08-12 2003-08-11 A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine Ceased WO2004015759A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2004527229A JP4684650B2 (en) 2002-08-12 2003-08-11 Method for forming a thin layer, method comprising correcting thickness by sacrificial oxidation, and associated machine
AU2003263391A AU2003263391A1 (en) 2002-08-12 2003-08-11 A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine
EP03784416A EP1547143B1 (en) 2002-08-12 2003-08-11 A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine
AT03784416T ATE484847T1 (en) 2002-08-12 2003-08-11 METHOD FOR PRODUCING A THIN LAYER INCLUDING A STEP OF CORRECTING THE THICKNESS BY AUXILIARY OXIDATION AND ASSOCIATED APPARATUS
DE60334555T DE60334555D1 (en) 2002-08-12 2003-08-11 METHOD FOR PRODUCING A THIN LAYER, INCLUDING A STEP OF CORRECTING THE THICKNESS THROUGH AUXILIARY OXIDATION AND ASSOCIATED DEVICE

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
FR02/10208 2002-08-12
FR0210209A FR2843487B1 (en) 2002-08-12 2002-08-12 THIN LAYER ENABLING PROCESS COMPRISING SACRIFICIAL OXIDATION THICKNESS CORRECTION STEP AND ASSOCIATED MACHINE
FR0210208A FR2843486B1 (en) 2002-08-12 2002-08-12 PROCESS FOR PRODUCING SEMICONDUCTOR THIN FILMS COMPRISING A FINISHING STEP
FR02/10209 2002-08-12
US46724103P 2003-04-30 2003-04-30
US60/467,241 2003-04-30

Publications (2)

Publication Number Publication Date
WO2004015759A2 WO2004015759A2 (en) 2004-02-19
WO2004015759A3 true WO2004015759A3 (en) 2004-06-03

Family

ID=31721058

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/003640 Ceased WO2004015759A2 (en) 2002-08-12 2003-08-11 A method of preparing a thin layer, the method including a step of correcting thickness by sacrificial oxidation, and an associated machine

Country Status (7)

Country Link
EP (2) EP2190010A2 (en)
JP (1) JP4684650B2 (en)
AT (1) ATE484847T1 (en)
AU (1) AU2003263391A1 (en)
DE (1) DE60334555D1 (en)
TW (1) TWI298919B (en)
WO (1) WO2004015759A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2991099B1 (en) 2012-05-25 2014-05-23 Soitec Silicon On Insulator PROCESS FOR PROCESSING A SEMICONDUCTOR STRUCTURE ON AN INSULATION FOR THE UNIFORMIZATION OF THE THICKNESS OF THE SEMICONDUCTOR LAYER
JP6747386B2 (en) * 2017-06-23 2020-08-26 信越半導体株式会社 Method for manufacturing SOI wafer
KR20260046249A (en) * 2019-02-15 2026-04-06 램 리써치 코포레이션 Trim and deposition profile control with multi-zone heated substrate support for multi-patterning processes
FR3099291A1 (en) 2019-07-23 2021-01-29 Soitec method of preparing a thin film, including a sequence of steps to improve the uniformity of thickness of said thin film
FR3104810B1 (en) 2019-12-17 2023-03-31 Soitec Silicon On Insulator METHOD FOR ETCHING SUBSTRATES COMPRISING A THIN SUPERFICIAL LAYER, IN ORDER TO IMPROVE THE UNIFORMITY OF THICKNESS OF SAID LAYER
CN114894132A (en) * 2022-05-08 2022-08-12 三河建华高科有限责任公司 Semiconductor wafer thickness detection control system
FR3155359A1 (en) 2023-11-14 2025-05-16 Soitec METHOD FOR THINNING THE SURFACE LAYER OF AN SOI SUBSTRATE

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0881040A2 (en) * 1997-05-28 1998-12-02 LAM Research Corporation Method and apparatus for in-situ monitoring of thickness using a multi-wavelength spectrometer during chemical-mechanical polishing
US6096233A (en) * 1996-09-24 2000-08-01 Tokyo Electron Limited Method for wet etching of thin film
WO2000060657A1 (en) * 1999-04-05 2000-10-12 Applied Materials, Inc. Endpoint detection in the fabrication of electronic devices
FR2797714A1 (en) * 1999-08-20 2001-02-23 Soitec Silicon On Insulator PROCESS FOR TREATMENT OF SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY THIS PROCESS
WO2002025708A2 (en) * 2000-09-20 2002-03-28 Kla-Tencor-Inc. Methods and systems for semiconductor fabrication processes

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3154100B2 (en) * 1991-08-02 2001-04-09 キヤノン株式会社 Manufacturing method of liquid crystal image display device
JP3272815B2 (en) * 1993-05-20 2002-04-08 株式会社東芝 Resist sensitivity adjustment apparatus and method
JP3612836B2 (en) * 1996-01-26 2005-01-19 三菱化学株式会社 Thin film manufacturing method
JP3660469B2 (en) * 1996-07-05 2005-06-15 日本電信電話株式会社 Manufacturing method of SOI substrate
JP2002118242A (en) * 1996-11-15 2002-04-19 Canon Inc Method for manufacturing semiconductor member
FR2777115B1 (en) 1998-04-07 2001-07-13 Commissariat Energie Atomique PROCESS FOR TREATING SEMICONDUCTOR SUBSTRATES AND STRUCTURES OBTAINED BY THIS PROCESS
FR2797713B1 (en) 1999-08-20 2002-08-02 Soitec Silicon On Insulator PROCESS FOR PROCESSING SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY THIS PROCESS
JP2001118832A (en) * 1999-10-21 2001-04-27 Toshiba Corp Method and apparatus for measuring etching groove depth, film thickness and step
US6750460B2 (en) 2000-05-02 2004-06-15 Epion Corporation System and method for adjusting the properties of a device by GCIB processing
JP2002134466A (en) * 2000-10-25 2002-05-10 Sony Corp Method for manufacturing semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6096233A (en) * 1996-09-24 2000-08-01 Tokyo Electron Limited Method for wet etching of thin film
EP0881040A2 (en) * 1997-05-28 1998-12-02 LAM Research Corporation Method and apparatus for in-situ monitoring of thickness using a multi-wavelength spectrometer during chemical-mechanical polishing
WO2000060657A1 (en) * 1999-04-05 2000-10-12 Applied Materials, Inc. Endpoint detection in the fabrication of electronic devices
FR2797714A1 (en) * 1999-08-20 2001-02-23 Soitec Silicon On Insulator PROCESS FOR TREATMENT OF SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY THIS PROCESS
WO2002025708A2 (en) * 2000-09-20 2002-03-28 Kla-Tencor-Inc. Methods and systems for semiconductor fabrication processes

Also Published As

Publication number Publication date
DE60334555D1 (en) 2010-11-25
EP1547143B1 (en) 2010-10-13
ATE484847T1 (en) 2010-10-15
JP4684650B2 (en) 2011-05-18
EP1547143A2 (en) 2005-06-29
JP2005536043A (en) 2005-11-24
EP2190010A2 (en) 2010-05-26
AU2003263391A1 (en) 2004-02-25
WO2004015759A2 (en) 2004-02-19
TWI298919B (en) 2008-07-11
TW200414392A (en) 2004-08-01

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