WO2004015781A1 - 化合物半導体ウェーハの製造方法及び化合物半導体素子 - Google Patents
化合物半導体ウェーハの製造方法及び化合物半導体素子 Download PDFInfo
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- WO2004015781A1 WO2004015781A1 PCT/JP2003/009818 JP0309818W WO2004015781A1 WO 2004015781 A1 WO2004015781 A1 WO 2004015781A1 JP 0309818 W JP0309818 W JP 0309818W WO 2004015781 A1 WO2004015781 A1 WO 2004015781A1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/80—Heterojunction BJTs
- H10D10/821—Vertical heterojunction BJTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
- H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
- H10D62/854—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs further characterised by the dopants
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2907—Materials being Group IIIA-VA materials
- H10P14/2911—Arsenides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
- H10P14/3221—Arsenides
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
- H10P14/3421—Arsenides
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3438—Doping during depositing
- H10P14/3441—Conductivity type
- H10P14/3444—P-type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/82—Heterojunctions
- H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
Definitions
- the present invention relates to a method of manufacturing a compound semiconductor wafer for manufacturing a heterojunction bipolar transistor (HBT) and a compound semiconductor device.
- HBT heterojunction bipolar transistor
- a heterojunction bipolar transistor is a bipolar transistor in which the emitter-base junction is a heterojunction using a material having a larger band gap than the base layer in the emitter layer in order to increase the emitter injection efficiency. Since it is suitable as a semiconductor device for use in the above-mentioned frequency range, it is expected as a semiconductor device for next-generation mobile phones.
- HBT The structure of HBT is as follows.
- an n + -GaAs layer (subcollector layer) and an n-GaAs layer (sub-collector layer) are generally formed on a semi-insulating GaAs substrate using metalorganic pyrolysis (MOCVD).
- MOCVD metalorganic pyrolysis
- a collector layer), a p-GaAs layer (base layer), an n-InGaP layer (emitter layer), and an n-GaAs layer (sub-emitter layer) are grown one after another to form an emitter-base junction.
- a thin-film crystal wafer having the above-mentioned layer structure in which the junction has a head-joined structure is formed, and an HBT is manufactured using this.
- FIG. 7 is a diagram schematically showing the structure of a conventional general GaAs-based HBT.
- a sub-collector layer 102 composed of an n + -GaAs layer
- a collector layer 103 composed of an n-GaAs layer
- a base composed of a p-GaAs layer layer 104
- n- I n G a P E emitter layer 105 made of layer ⁇ Pi n + - Sapuemitta layer 106 made of GaAs layer, n + -
- An emitter contact layer 107 composed of an InGaAs layer is formed in this order as a semiconductor thin-film crystal layer using an appropriate vapor deposition method such as an M ⁇ C VD method, and a collector electrode is formed on the sub-collector layer 102.
- I n is the electron injection current from the emitter to the base
- I p is the hole injection current from the base to the emitter
- Is is the emitter recombination current at the Z-base interface
- Ir is the recombination current in the base. is there.
- Japanese Patent Application Laid-Open No. HEI 3-111809 discloses that a substrate temperature during the growth of a compound semiconductor thin film is set at 450 to 65 ° C. There has been proposed a method for producing a compound semiconductor thin film in which the supply molar ratio of the group III source and the group III source is set within the range of 0.3 to 2.5.
- An object of the present invention is to propose a method of manufacturing a compound semiconductor wafer and a compound semiconductor element capable of solving the above-mentioned problems in the conventional technology.
- An object of the present invention is to provide a method of manufacturing a compound semiconductor wafer and a compound semiconductor element which can control a carrier concentration by adding an impurity from the outside and form a base layer having good crystallinity. It is in.
- the crystallinity of the base layer is improved by setting the growth conditions of the base layer to be conditions for controlling the group V gas flow rate supply, thereby significantly improving the current amplification factor.
- V / III ratio between 1.0 and 0.3 Within this range, the rate-controlled growth of the group 5 gas flow can be achieved.
- the V / III ratio is the supply ratio of the group 5 raw material to the group 3 raw material during the growth of the group 3-5 compound semiconductor crystal.
- the raw material is supplied in a gas state from a gas cylinder puller.
- the amount of gas supplied from the gas cylinder is controlled by a flow control device such as a mass flow controller installed in the supply line, and (the gas concentration in the cylinder) X (gas flow rate) becomes the actual flow rate of the raw material.
- the amount of gas supplied from the bubbler is controlled by a flow control device such as a mass flow controller installed in the carrier gas supply line that flows through the bubbler. Is the actual flow rate of the raw material.
- the actual flow rate of raw materials supplied by these methods is the V / III ratio, which is the ratio of group 5 raw materials to group 3 raw materials. Also in this specification, the term V / II ratio is used according to the above definition.
- the sub-collector layer, the collector layer, the base layer, and the emitter layer are formed on the compound semiconductor substrate by vapor-phase growth using the MOC VD method in this order.
- the crystallinity of the grown base layer becomes good, the recombination current in the base layer can be reduced, and the current amplification rate of the HBT can be increased. Can be.
- a method of manufacturing a compound semiconductor wafer according to the first aspect wherein the base layer is grown with a VZIII ratio in a range of 0.3 to 1.0. Is proposed.
- a method for manufacturing a compound semiconductor wafer wherein the adjustment of the carrier concentration of the base layer is controlled by the flow rate of halogenated methane. Is proposed.
- a method for producing a compound semiconductor wafer in which the adjustment of the carrier concentration of the semiconductor layer is controlled by the flow rate of CBrC13 is proposed.
- a compound semiconductor device in which a subcollector layer, a collector layer, a base layer, and an emitter layer are formed on a compound semiconductor substrate in this order as a thin film crystal layer by vapor phase growth.
- the compound semiconductor device is proposed, wherein the minority carrier in the base layer has a lifetime of 200 psec or more.
- a heterojunction bipolar transistor in which a subcollector layer, a collector layer, a base layer, and an emitter layer are formed on a compound semiconductor substrate in this order as thin film crystal layers by vapor phase growth.
- FIG. 1 is a layer structure diagram schematically showing an example of an HBT thin film crystal wafer manufactured by the method of the present invention.
- FIG. 2 is a view schematically showing a main part of a vapor growth semiconductor manufacturing apparatus used for manufacturing the semiconductor wafer shown in FIG.
- FIG. 3 is a diagram showing the relationship between the VZIII ratio of P—GaAs and the growth rate.
- Figure 4 is a graph showing the relationship between the flow rate and the carrier concentration of CB r C 1 3.
- FIG. 5 is a graph showing the relationship between the VZIII ratio and the current gain in the base layer.
- FIG. 6 is a graph showing the relationship between the current amplification factor and the base resistance according to the present invention in comparison with the case of the conventional example.
- FIG. 7 is a diagram schematically showing a layer structure of a conventional general GaAs-based HBT.
- FIG. 1 is a layer structure diagram schematically showing an example of a thin film crystal wafer for wafers manufactured by the method of the present invention.
- This thin-film crystal wafer is a compound semiconductor wafer used in the manufacture of GaAs-based HBTs. JP2003 / 009818
- the structure of the semiconductor wafer 1 shown in FIG. 1 is as follows.
- the semiconductor layer 1 is formed by laminating a plurality of semiconductor thin-film crystal growth layers on a GaAs substrate 2, which is a semi-insulating GaAs compound semiconductor crystal, using the MOC VD method. It was done. Referring to FIG. 1, the semiconductor wafer 1 will be described.
- the GaAs substrate 2 is composed of a semi-insulating GaAs (001) layer, and the buffer layer is composed of an i—GaAs layer on the GaAs substrate 2. 3 are formed.
- the HBT functional layer 4 has, on the buffer layer 3, an n + — GaAs layer serving as a sub-collector layer 41 and an ⁇ -GaAs layer serving as a collector layer 42, which are sequentially formed on the semiconductor layer.
- the epitaxially grown crystal layer is formed to a predetermined thickness.
- a p + -GaAs layer serving as a base layer 43 is also formed as a semiconductor epitaxial growth crystal layer, and on the base layer 43, serves as an emitter layer 44.
- a P layer is formed.
- an ⁇ ——GaAs layer is formed as a sub-emitter layer 45, and an n + —GaAs layer and an n + —InGaAs layer are formed as emitter contact layers 46 and 47.
- MOCVD method A method for forming each of the above layers as an epitaxially grown semiconductor thin film crystal layer by the MOCVD method will be described in detail below.
- FIG. 2 schematically shows a main part of a vapor growth semiconductor manufacturing apparatus 10 used for manufacturing the semiconductor wafer 1 shown in FIG. 1 by MOCVD.
- the semiconductor manufacturing apparatus 10 is provided with a reactor 12 to which a raw material gas from a raw material supply system (not shown) is supplied via a raw material supply line 11.
- a susceptor 13 for mounting and heating is provided.
- the susceptor 13 is a polygonal column, and a plurality of GaAs substrates 2 are attached to the surface thereof.
- the susceptor 13 has a known configuration that can be rotated by the rotating device 14.
- Reference numeral 15 denotes a coil for high-frequency induction heating of the susceptor 13.
- the source gas supplied into the buffer layer 3 through the source supply line 11 is thermally decomposed on the GaAs substrate 2, and a desired semiconductor thin film crystal is vaporized on the GaAs substrate 2. Phase growth is possible.
- the used gas is exhausted from the exhaust port 12A to the outside and sent to the exhaust gas treatment device.
- the GaAs substrate 2 After placing the GaAs substrate 2 on the susceptor 13 in the reactor 12, use hydrogen as a carrier gas, arsine and trimethylgallium (TMG) as raw materials, and apply G at 650 ° C. a As is grown as a buffer layer 3 by about 500 nm. Thereafter, the sub-collector layer 41 and the collector layer 42 are grown on the buffer layer 3 at a growth temperature of 620 ° C.
- TMG trimethylgallium
- the base layer 43 is grown at a growth temperature of 62 ° C.
- the base layer 43 is grown with the VZIII ratio in the range of 0.3 to 1.0 so that the growth rate of the group V gas is controlled when the base layer 43 is grown.
- VZIII ratio is 1.
- the growth rate is group III gas flow rate-controlled growth. If the v, m ratio is less than 1.0, the growth rate is group V gas flow rate-controlled growth, and the V / III ratio is small. As it grows, the growth rate decreases.
- Fig. 3 shows the relationship between the VZIII ratio and the growth rate (a.u.) when the Group 3 gas flow rate was kept constant and the Group 5 gas flow rate was changed. It is shown.
- the growth rate is constant because the growth rate is determined by the Group 3 gas flow rate.
- the growth rate is determined by the group 5 gas flow rate.However, since the group 5 gas flow rate decreases as the VZIII ratio decreases, the growth rate decreases as the ⁇ ratio decreases. Decreases. If the VZIII ratio is less than 0.3, the flatness of the crystal will deteriorate. Therefore, it is impractical to make the V / III ratio smaller than 0.3.
- the VII ratio should be set to an appropriate value within the range of 1.0 to 0.3. But preferred.
- the emitter layer 44 and the sub-emitter layer 45 are grown on the base layer 43 at a growth temperature of 62 ° C. Emitter contact layers 46 and 47 are formed on 45.
- the base layer 43 constituting the HBT was grown with the V / III ratio in the range of 0.3 to 1.0 so that the group V gas flow rate controlled growth was achieved as described above.
- the crystallinity of the base layer 43 becomes extremely good, whereby the recombination current in the base layer can be reduced, and the current amplification factor of the HBT can be greatly improved.
- TMG that is, a Ga-based raw material is used as the Group 3 raw material.
- an A1-based raw material or an In-based raw material can be used.
- the Ga-based raw material, the A1-based raw material and the In-based raw material may be used alone, but some of them may be used in combination.
- the base layer 43 may be grown using an appropriate Group 5 material including As as well as arsine as the Group 5 material.
- the CB r C 1 3 is a dopant and 10 ° C, subjected to CB r C l 3 Papura It can be seen that by adjusting the flow rate (sc cra) of the supplied carrier gas, the carrier concentration can be independently controlled within the range of 1.0 ⁇ 10 19 cm— 3 to 1.0 ⁇ 10 20 c ⁇ 3 . The same applies when the temperature is other than 620 ° C.
- the control of the Kiyaria concentration in the base layer 43, CB r C 1 3 In addition to flow rate control, flow of halogenated methane during growth, can be carried out in the same manner by controlling the flow rate.
- the halogenated methane in addition to the above, for example CB r 4, CB r 3 C l, such as CB r 2 C l 2, CC 1 4 may be used.
- the semiconductor wafer 1 having the layer configuration shown in FIG. 1 is manufactured, and the HBT is manufactured using the semiconductor wafer 1, the crystallinity of the base layer 43 is improved, so that an amplifying element having a large current amplification factor Can be made.
- the minority carriers of the base layer 43 have a lifetime of 200 psec or more.
- the ratio of the current amplification factor Z base sheet resistance is preferably 0.60 or more.
- a semiconductor wafer having the structure shown in FIG. 1 was manufactured, and an HBT element was manufactured using the semiconductor wafer as in the following example.
- the emitter size is 100 // mX 10 ⁇ ⁇ .
- the Z base current is assumed to be the current amplification factor] 3.
- Time-resolved PL measurement cannot be performed with the HBT structure because the base layer is thin. Therefore, a measurement was performed on a sample in which p-GaAs thin films were stacked at a thickness of 1 ⁇ m under the same conditions as those for forming the HBT base layer.
- a growth temperature is set to 620 ° C, trimethylgallium (TMG) is used as a Group 3 material, and arsine (AsH 3 ) is used as a Group 5 material, and CB is used as a p-type dopant. with r C 1 3, it was VZIII ratio and 0.9.
- the carrier concentration of the base layer 43 was adjusted to 3.6 ⁇ 10 19 cm by adjusting the doping amount of the dopant C.
- the current amplification factor ⁇ of the HBT element was measured. It was 180.
- the ratio of the current amplification factor ⁇ ⁇ base sheet resistance BR s was 0.60.
- a device was manufactured under exactly the same conditions as in Example 1 except that the VZIII ratio was 0.7, and the current amplification factor was measured to be 215. When the life of the minor carrier in the base layer 43 was measured, it was 230 psec. The current amplification rate was measured to be 0.70 when the ratio of the sheet resistance B R s was measured.
- An HBT device for comparison was manufactured under the same growth conditions as in Example I, with the VZIII ratio set to 1.3, 3.3, and 25 of 1.0 or more.
- the current gain ⁇ was 150 in all cases.
- the ratio of the current amplification factor ⁇ / base sheet resistance BRs was measured to be 0.50.
- the lifetime of the minority carrier when the VZIII ratio was 25 was measured, it was 160 psec.
- Figures 5 and 6 show the results of these measurements. Under the growth conditions of V group gas with a V / III ratio of 1.0 or less, the base layer has good crystal quality with few defects. The life of the rear has been extended. As a result, it is considered that] 3 was improved.
- Example 1 0.9 0.9 0.60 200
- the crystallinity of the base layer can be improved by setting the growth conditions of the base layer to the conditions for controlling the group V gas flow rate supply, thereby extending the life of the minority carrier.
- the ratio of the current amplification factor Z base sheet resistance is set to a high value, thereby making it possible to significantly improve the current amplification factor.
- the carrier concentration of the base layer can be controlled independently of the growth conditions, it is easy to control the carrier concentration to a desired value.
- the device using the compound semiconductor wafer of the present invention is used as an HBT in a frequency range above the microwave band.
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Abstract
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Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/524,013 US7208387B2 (en) | 2002-08-09 | 2003-08-01 | Method for manufacturing compound semiconductor wafer and compound semiconductor device |
| AU2003252335A AU2003252335A1 (en) | 2002-08-09 | 2003-08-01 | Method for manufacturing compound semiconductor wafer and compound semiconductor device |
| EP03784504A EP1542288A4 (en) | 2002-08-09 | 2003-08-01 | METHOD FOR PRODUCING A COMPOSED SEMICONDUCTOR WAFERS AND ASSEMBLING SEMICONDUCTOR EQUIPMENT |
| US11/688,166 US7576352B2 (en) | 2002-08-09 | 2007-03-19 | Method for producing compound semiconductor wafer and compound semiconductor device |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002/233708 | 2002-08-09 | ||
| JP2002233708A JP2004079574A (ja) | 2002-08-09 | 2002-08-09 | 化合物半導体ウェーハの製造方法及び化合物半導体素子 |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10524013 A-371-Of-International | 2003-08-01 | ||
| US11/688,166 Division US7576352B2 (en) | 2002-08-09 | 2007-03-19 | Method for producing compound semiconductor wafer and compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2004015781A1 true WO2004015781A1 (ja) | 2004-02-19 |
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ID=31711872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2003/009818 Ceased WO2004015781A1 (ja) | 2002-08-09 | 2003-08-01 | 化合物半導体ウェーハの製造方法及び化合物半導体素子 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7208387B2 (ja) |
| EP (1) | EP1542288A4 (ja) |
| JP (1) | JP2004079574A (ja) |
| KR (1) | KR100990350B1 (ja) |
| AU (1) | AU2003252335A1 (ja) |
| TW (1) | TW200402766A (ja) |
| WO (1) | WO2004015781A1 (ja) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006009782A2 (en) * | 2004-06-17 | 2006-01-26 | On International, Inc. | Persistent p-type group ii-vi semiconductors |
| JP2006185990A (ja) * | 2004-12-27 | 2006-07-13 | Renesas Technology Corp | 半導体装置およびその製造方法ならびに電子装置 |
| US8193609B2 (en) * | 2008-05-15 | 2012-06-05 | Triquint Semiconductor, Inc. | Heterojunction bipolar transistor device with electrostatic discharge ruggedness |
| JP5507975B2 (ja) * | 2009-11-19 | 2014-05-28 | 住友化学株式会社 | 半導体基板、電子デバイスおよび半導体基板の製造方法 |
| CN106435522B (zh) * | 2016-09-27 | 2019-04-12 | 中国电子科技集团公司第四十八研究所 | 晶硅太阳电池氧化铝钝化膜的pecvd沉积工艺 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792526A (en) * | 1980-11-28 | 1982-06-09 | Toshiba Corp | Vaper growth of compound semiconductor |
| EP0390552A2 (en) * | 1989-03-31 | 1990-10-03 | Kabushiki Kaisha Toshiba | Method of manufacturing compound semiconductor thin film |
| JPH06236852A (ja) * | 1993-02-12 | 1994-08-23 | Matsushita Electron Corp | 半導体装置の製造方法および半導体装置 |
| EP0977245A2 (en) * | 1998-07-27 | 2000-02-02 | Sumitomo Chemical Company, Limited | Method for manufacturing carbon-doped compound semiconductors |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2885435B2 (ja) | 1989-09-25 | 1999-04-26 | 株式会社東芝 | 化合物半導体薄膜の製造方法 |
| JP2000068284A (ja) * | 1998-08-19 | 2000-03-03 | Sharp Corp | ヘテロ接合バイポーラトランジスタの製造方法及びパワーアンプ |
| JP4126812B2 (ja) * | 1999-07-07 | 2008-07-30 | 富士ゼロックス株式会社 | 光半導体素子 |
| US6847060B2 (en) * | 2000-11-27 | 2005-01-25 | Kopin Corporation | Bipolar transistor with graded base layer |
| KR100469642B1 (ko) * | 2002-05-31 | 2005-02-02 | 한국전자통신연구원 | 특정 파장의 빛을 선택적으로 검출하는 광수신기 및 그제조 방법 |
-
2002
- 2002-08-09 JP JP2002233708A patent/JP2004079574A/ja active Pending
-
2003
- 2003-08-01 US US10/524,013 patent/US7208387B2/en not_active Expired - Lifetime
- 2003-08-01 WO PCT/JP2003/009818 patent/WO2004015781A1/ja not_active Ceased
- 2003-08-01 EP EP03784504A patent/EP1542288A4/en not_active Withdrawn
- 2003-08-01 KR KR1020057002270A patent/KR100990350B1/ko not_active Expired - Fee Related
- 2003-08-01 AU AU2003252335A patent/AU2003252335A1/en not_active Abandoned
- 2003-08-06 TW TW092121492A patent/TW200402766A/zh not_active IP Right Cessation
-
2007
- 2007-03-19 US US11/688,166 patent/US7576352B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5792526A (en) * | 1980-11-28 | 1982-06-09 | Toshiba Corp | Vaper growth of compound semiconductor |
| EP0390552A2 (en) * | 1989-03-31 | 1990-10-03 | Kabushiki Kaisha Toshiba | Method of manufacturing compound semiconductor thin film |
| JPH06236852A (ja) * | 1993-02-12 | 1994-08-23 | Matsushita Electron Corp | 半導体装置の製造方法および半導体装置 |
| EP0977245A2 (en) * | 1998-07-27 | 2000-02-02 | Sumitomo Chemical Company, Limited | Method for manufacturing carbon-doped compound semiconductors |
Non-Patent Citations (1)
| Title |
|---|
| See also references of EP1542288A4 * |
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| Publication number | Publication date |
|---|---|
| US20060001044A1 (en) | 2006-01-05 |
| KR20050060064A (ko) | 2005-06-21 |
| US7576352B2 (en) | 2009-08-18 |
| AU2003252335A1 (en) | 2004-02-25 |
| US7208387B2 (en) | 2007-04-24 |
| KR100990350B1 (ko) | 2010-10-29 |
| US20070170466A1 (en) | 2007-07-26 |
| TWI312534B (ja) | 2009-07-21 |
| EP1542288A1 (en) | 2005-06-15 |
| JP2004079574A (ja) | 2004-03-11 |
| TW200402766A (en) | 2004-02-16 |
| AU2003252335A8 (en) | 2004-02-25 |
| EP1542288A4 (en) | 2008-05-21 |
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