WO2004017223A3 - Programmable pipeline fabric utilizing partially global configuration buses - Google Patents
Programmable pipeline fabric utilizing partially global configuration buses Download PDFInfo
- Publication number
- WO2004017223A3 WO2004017223A3 PCT/US2003/025391 US0325391W WO2004017223A3 WO 2004017223 A3 WO2004017223 A3 WO 2004017223A3 US 0325391 W US0325391 W US 0325391W WO 2004017223 A3 WO2004017223 A3 WO 2004017223A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- stripes
- stripe
- virtual
- physical
- processing elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Software Systems (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Advance Control (AREA)
- Storage Device Security (AREA)
- Image Processing (AREA)
Abstract
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004529378A JP2005539293A (en) | 2002-08-16 | 2003-08-14 | Programmable pipeline fabric using a partially global configuration bus |
| DE60323847T DE60323847D1 (en) | 2002-08-16 | 2003-08-14 | PROGRAMMABLE PIPELINE MATRIX WITH PARTIAL GLOBAL CONFIGURATION BUSS |
| EP03788452A EP1535189B1 (en) | 2002-08-16 | 2003-08-14 | Programmable pipeline fabric utilizing partially global configuration buses |
| AU2003262645A AU2003262645A1 (en) | 2002-08-16 | 2003-08-14 | Programmable pipeline fabric utilizing partially global configuration buses |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/222,645 | 2002-08-16 | ||
| US10/222,645 US7263602B2 (en) | 2002-08-16 | 2002-08-16 | Programmable pipeline fabric utilizing partially global configuration buses |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2004017223A2 WO2004017223A2 (en) | 2004-02-26 |
| WO2004017223A3 true WO2004017223A3 (en) | 2004-04-08 |
Family
ID=31715027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2003/025391 Ceased WO2004017223A2 (en) | 2002-08-16 | 2003-08-14 | Programmable pipeline fabric utilizing partially global configuration buses |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7263602B2 (en) |
| EP (1) | EP1535189B1 (en) |
| JP (1) | JP2005539293A (en) |
| CN (1) | CN100392635C (en) |
| AT (1) | ATE409916T1 (en) |
| AU (1) | AU2003262645A1 (en) |
| DE (1) | DE60323847D1 (en) |
| WO (1) | WO2004017223A2 (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4547198B2 (en) * | 2004-06-30 | 2010-09-22 | 富士通株式会社 | Arithmetic device, control method of arithmetic device, program, and computer-readable recording medium |
| JP4546775B2 (en) * | 2004-06-30 | 2010-09-15 | 富士通株式会社 | Reconfigurable circuit capable of time-division multiplex processing |
| KR100662873B1 (en) * | 2006-01-03 | 2007-01-02 | 삼성전자주식회사 | Loop Accelerators and Data Processing Systems Including the Same |
| KR101586770B1 (en) * | 2008-10-14 | 2016-01-19 | 고쿠리츠다이가쿠호징 나라 센탄카가쿠기쥬츠 다이가쿠인 다이가쿠 | Data processing device |
| JP5552855B2 (en) * | 2010-03-19 | 2014-07-16 | 富士ゼロックス株式会社 | Image processing apparatus, image forming system, and image processing program |
| GB2535547B (en) * | 2015-04-21 | 2017-01-11 | Adaptive Array Systems Ltd | Data processor |
| US11093251B2 (en) | 2017-10-31 | 2021-08-17 | Micron Technology, Inc. | System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network |
| EP3776241B1 (en) | 2018-03-31 | 2023-06-28 | Micron Technology, Inc. | Loop thread order execution control of a multi-threaded, self-scheduling reconfigurable computing fabric |
| EP3776239A1 (en) * | 2018-03-31 | 2021-02-17 | Micron Technology, Inc. | Loop execution control for a multi-threaded, self-scheduling reconfigurable computing fabric using a reenter queue |
| US11010161B2 (en) | 2018-03-31 | 2021-05-18 | Micron Technology, Inc. | Multiple types of thread identifiers for a multi-threaded, self-scheduling reconfigurable computing fabric |
| EP3776236A1 (en) * | 2018-03-31 | 2021-02-17 | Micron Technology, Inc. | Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric |
| KR102504080B1 (en) | 2018-03-31 | 2023-02-28 | 마이크론 테크놀로지, 인크. | Multithreaded, self-scheduling reconfigurable computing fabric |
| US10990391B2 (en) | 2018-03-31 | 2021-04-27 | Micron Technology, Inc. | Backpressure control using a stop signal for a multi-threaded, self-scheduling reconfigurable computing fabric |
| US11003451B2 (en) | 2018-03-31 | 2021-05-11 | Micron Technology, Inc. | Execution control of a multi-threaded, self-scheduling reconfigurable computing fabric |
| KR102465213B1 (en) | 2018-03-31 | 2022-11-10 | 마이크론 테크놀로지, 인크. | Conditional branching control for multi-threaded, self-scheduling, reconfigurable compute fabrics |
| US11573834B2 (en) | 2019-08-22 | 2023-02-07 | Micron Technology, Inc. | Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric |
| US11150900B2 (en) | 2019-08-28 | 2021-10-19 | Micron Technology, Inc. | Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric |
| US11886377B2 (en) | 2019-09-10 | 2024-01-30 | Cornami, Inc. | Reconfigurable arithmetic engine circuit |
| CN116521134A (en) * | 2023-03-13 | 2023-08-01 | 广州嘉为科技有限公司 | Method, device and medium for modifying parameters of CI pipeline in execution process |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5684980A (en) * | 1992-07-29 | 1997-11-04 | Virtual Computer Corporation | FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions |
| JP3308770B2 (en) * | 1994-07-22 | 2002-07-29 | 三菱電機株式会社 | Information processing apparatus and calculation method in information processing apparatus |
| US5794062A (en) * | 1995-04-17 | 1998-08-11 | Ricoh Company Ltd. | System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization |
| JPH09106389A (en) * | 1995-10-12 | 1997-04-22 | Sony Corp | Signal processor |
| FI971718L (en) * | 1997-04-22 | 1998-10-23 | Nokia Telecommunications Oy | Adding slots to a high-capacity bus |
| US6167502A (en) * | 1997-10-10 | 2000-12-26 | Billions Of Operations Per Second, Inc. | Method and apparatus for manifold array processing |
| JPH11259436A (en) * | 1998-03-10 | 1999-09-24 | Toppan Printing Co Ltd | Data parallel processing method |
| US6119215A (en) * | 1998-06-29 | 2000-09-12 | Cisco Technology, Inc. | Synchronization and control system for an arrayed processing engine |
| US6442732B1 (en) * | 1999-04-21 | 2002-08-27 | Lucent Technologies, Inc. | Virtual logic system for solving satisfiability problems using reconfigurable hardware |
| WO2002037264A2 (en) * | 2000-11-06 | 2002-05-10 | Broadcom Corporation | Reconfigurable processing system and method |
| CN1156760C (en) * | 2000-12-12 | 2004-07-07 | 智原科技股份有限公司 | Memory data access device and method suitable for processor |
| US6526559B2 (en) * | 2001-04-13 | 2003-02-25 | Interface & Control Systems, Inc. | Method for creating circuit redundancy in programmable logic devices |
-
2002
- 2002-08-16 US US10/222,645 patent/US7263602B2/en not_active Expired - Fee Related
-
2003
- 2003-08-14 AT AT03788452T patent/ATE409916T1/en not_active IP Right Cessation
- 2003-08-14 JP JP2004529378A patent/JP2005539293A/en active Pending
- 2003-08-14 AU AU2003262645A patent/AU2003262645A1/en not_active Abandoned
- 2003-08-14 CN CNB038242648A patent/CN100392635C/en not_active Expired - Fee Related
- 2003-08-14 DE DE60323847T patent/DE60323847D1/en not_active Expired - Fee Related
- 2003-08-14 WO PCT/US2003/025391 patent/WO2004017223A2/en not_active Ceased
- 2003-08-14 EP EP03788452A patent/EP1535189B1/en not_active Expired - Lifetime
Non-Patent Citations (3)
| Title |
|---|
| GOLDSTEIN S C ET AL: "PIPERENCH: A COPROCESSOR FOR STREAMING MULTIMEDIA ACCELERATION", PROCEEDINGS OF THE 26TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE. ATLANTA, GA, MAY 2 - 4, 1999, INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE. (ISCA), LOS ALAMITOS, CA: IEEE COMP. SOC, US, vol. CONF. 26, 2 May 1999 (1999-05-02), pages 28 - 39, XP000887607, ISBN: 0-7695-0171-0 * |
| SCHMIT H H ET AL: "PIPELINE RECONFIGURABLE FPGAS", JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL, IMAGE, AND VIDEO TECHNOLOGY, KLUWER ACADEMIC PUBLISHERS, DORDRECHT, NL, vol. 24, no. 2/3, March 2000 (2000-03-01), pages 129 - 145, XP000908461, ISSN: 0922-5773 * |
| SCHMIT H: "Incremental reconfiguration for pipelined applications", FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, 1997. PROCEEDINGS., THE 5TH ANNUAL IEEE SYMPOSIUM ON NAPA VALLEY, CA, USA 16-18 APRIL 1997, LOS ALAMITOS, CA, USA,IEEE COMPUT. SOC, US, 16 April 1997 (1997-04-16), pages 47 - 55, XP010247467, ISBN: 0-8186-8159-4 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US20040034761A1 (en) | 2004-02-19 |
| US7263602B2 (en) | 2007-08-28 |
| EP1535189B1 (en) | 2008-10-01 |
| JP2005539293A (en) | 2005-12-22 |
| EP1535189A2 (en) | 2005-06-01 |
| CN1688991A (en) | 2005-10-26 |
| AU2003262645A1 (en) | 2004-03-03 |
| CN100392635C (en) | 2008-06-04 |
| AU2003262645A8 (en) | 2004-03-03 |
| DE60323847D1 (en) | 2008-11-13 |
| ATE409916T1 (en) | 2008-10-15 |
| WO2004017223A2 (en) | 2004-02-26 |
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