WO2004034252A3 - Vliw processor with instruction address modification - Google Patents

Vliw processor with instruction address modification Download PDF

Info

Publication number
WO2004034252A3
WO2004034252A3 PCT/IB2003/004184 IB0304184W WO2004034252A3 WO 2004034252 A3 WO2004034252 A3 WO 2004034252A3 IB 0304184 W IB0304184 W IB 0304184W WO 2004034252 A3 WO2004034252 A3 WO 2004034252A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
instructions
instruction address
program
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2003/004184
Other languages
French (fr)
Other versions
WO2004034252A2 (en
Inventor
Pinto Carlos A Alba
Ramanathan Sethuraman
Balakrishnan Srinivasan
Harm J A M Peters
Llopis Rafael Peset
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to JP2004542710A priority Critical patent/JP2006502489A/en
Priority to US10/530,375 priority patent/US7664929B2/en
Priority to AU2003263491A priority patent/AU2003263491A1/en
Priority to EP03807919A priority patent/EP1554648A2/en
Publication of WO2004034252A2 publication Critical patent/WO2004034252A2/en
Publication of WO2004034252A3 publication Critical patent/WO2004034252A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least some of the instruction words are fetched from respective memory units in parallel, addressed with an instruction address that is common for the functional units. Translation of the instruction address into a physical address can be modified for one or more particular ones of the memory units. Modification is controlled by modification update instructions in the program. Thus, it can be selected dependent on program execution which instructions from the memory units will be combined into the instruction word in response to the instruction address.
PCT/IB2003/004184 2002-10-11 2003-09-17 Vliw processor with instruction address modification Ceased WO2004034252A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2004542710A JP2006502489A (en) 2002-10-11 2003-09-17 Data processing apparatus having functional units for parallel processing
US10/530,375 US7664929B2 (en) 2002-10-11 2003-09-17 Data processing apparatus with parallel operating functional units
AU2003263491A AU2003263491A1 (en) 2002-10-11 2003-09-17 Vliw processor with instruction address modification
EP03807919A EP1554648A2 (en) 2002-10-11 2003-09-17 Data processing apparatus with parallel operating functional units

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02079221 2002-10-11
EP02079221.4 2002-10-11

Publications (2)

Publication Number Publication Date
WO2004034252A2 WO2004034252A2 (en) 2004-04-22
WO2004034252A3 true WO2004034252A3 (en) 2004-10-21

Family

ID=32088029

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2003/004184 Ceased WO2004034252A2 (en) 2002-10-11 2003-09-17 Vliw processor with instruction address modification

Country Status (6)

Country Link
US (1) US7664929B2 (en)
EP (1) EP1554648A2 (en)
JP (1) JP2006502489A (en)
CN (1) CN1688967A (en)
AU (1) AU2003263491A1 (en)
WO (1) WO2004034252A2 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100636596B1 (en) * 2004-11-25 2006-10-23 한국전자통신연구원 High Energy Efficiency Parallel Processing Data Path Structure
US8745359B2 (en) * 2008-02-26 2014-06-03 Nec Corporation Processor for concurrently executing plural instruction streams
JP2009211192A (en) * 2008-02-29 2009-09-17 Toshiba Corp Memory system
US8510709B2 (en) * 2009-06-01 2013-08-13 National Instruments Corporation Graphical indicator which specifies parallelization of iterative program code in a graphical data flow program
US9733914B2 (en) * 2009-06-01 2017-08-15 National Instruments Corporation Loop parallelization analyzer for data flow programs
US9703559B2 (en) 2011-11-09 2017-07-11 Nec Corporation Digital signal processor, program control method, and control program
US10936317B2 (en) * 2019-05-24 2021-03-02 Texas Instruments Incorporated Streaming address generation

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0473420A2 (en) * 1990-08-29 1992-03-04 Hitachi, Ltd. Virtual long instruction word memory architecture for digital signal processor
US6026479A (en) * 1998-04-22 2000-02-15 Hewlett-Packard Company Apparatus and method for efficient switching of CPU mode between regions of high instruction level parallism and low instruction level parallism in computer programs
EP1176505A1 (en) * 2000-07-27 2002-01-30 STMicroelectronics S.A. Parallel digital signal processor architecture
WO2003058433A1 (en) * 2001-12-21 2003-07-17 Hewlett-Packard Company Multiple function unit processor using distributed variable length instruction words

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3061836B2 (en) * 1990-05-22 2000-07-10 日本電気株式会社 Memory device
KR960024924A (en) * 1994-12-23 1996-07-20 리 패치 Method and device for generating identification bit for Annex register file
US6076159A (en) * 1997-09-12 2000-06-13 Siemens Aktiengesellschaft Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline
US7349992B2 (en) * 2002-01-24 2008-03-25 Emulex Design & Manufacturing Corporation System for communication with a storage area network

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0473420A2 (en) * 1990-08-29 1992-03-04 Hitachi, Ltd. Virtual long instruction word memory architecture for digital signal processor
US6026479A (en) * 1998-04-22 2000-02-15 Hewlett-Packard Company Apparatus and method for efficient switching of CPU mode between regions of high instruction level parallism and low instruction level parallism in computer programs
EP1176505A1 (en) * 2000-07-27 2002-01-30 STMicroelectronics S.A. Parallel digital signal processor architecture
WO2003058433A1 (en) * 2001-12-21 2003-07-17 Hewlett-Packard Company Multiple function unit processor using distributed variable length instruction words

Also Published As

Publication number Publication date
AU2003263491A8 (en) 2004-05-04
US20050273569A1 (en) 2005-12-08
WO2004034252A2 (en) 2004-04-22
CN1688967A (en) 2005-10-26
JP2006502489A (en) 2006-01-19
AU2003263491A1 (en) 2004-05-04
EP1554648A2 (en) 2005-07-20
US7664929B2 (en) 2010-02-16

Similar Documents

Publication Publication Date Title
WO2007012794A3 (en) Algebraic single instruction multiple data processing
WO2007002550A3 (en) Primitives to enhance thread-level speculation
WO2007095397A3 (en) Programmable processing unit
JP2004054585A5 (en)
WO2004109499A3 (en) Predication instruction within a data processing system
WO2007112406A3 (en) Programming a multi-processor system
RU2009109242A (en) METHOD AND DEVICE FOR PERFORMING PROCESSOR INSTRUCTIONS BASED ON DYNAMICALLY VARIABLE DELAY
WO2007092528A3 (en) Thread optimized multiprocessor architecture
EP3644179A3 (en) Apparatus and method for tile gather and tile scatter
WO2006113420A3 (en) System and method wherein conditional instructions unconditionally provide output
WO2007072324A3 (en) Multi-processor circuit with shared memory banks
DE602005025677D1 (en) PROGRAMMABLE DATA PROCESSING CIRCUIT SUPPORTING SIMD COMMANDS
WO2001086432A3 (en) Cryptographic data processing systems, computer program products, and methods of operating same, using parallel execution units
KR960706124A (en) Processing system with word aligned branch target
TW200741550A (en) Methods and arrangements to dynamically modify the number of active processors in a multi-node system
WO2002057908A3 (en) A superscalar processor having content addressable memory structures for determining dependencies
WO2007008880A3 (en) Changing code execution path using kernel mode redirection
WO2006085639A3 (en) Methods and apparatus for instruction set emulation
ATE403903T1 (en) CONTEXT SCHEDULING
US7620804B2 (en) Central processing unit architecture with multiple pipelines which decodes but does not execute both branch paths
EP1089168A3 (en) Very long instruction word processor
EP1770516A4 (en) METHOD OF CONTROLLING THE SAME FOR CONTROLLING THE EXECUTION OF A PROGRAM / INSTRUCTION AND ARCHITECTURE, AND ASSOCIATED PROCESSOR
WO2004046955A3 (en) A configurable processor architecture
ATE463011T1 (en) HIERARCHICAL PROCESSOR ARCHITECTURE FOR VIDEO PROCESSING
TW200741536A (en) Computer having dynamically-changeable instruction set in real time

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 2003807919

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 10530375

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 20038240270

Country of ref document: CN

Ref document number: 2004542710

Country of ref document: JP

WWP Wipo information: published in national office

Ref document number: 2003807919

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 2003807919

Country of ref document: EP