WO2004059473A3 - Performing hardware scout threading in a system that supports simultaneous multithreading - Google Patents

Performing hardware scout threading in a system that supports simultaneous multithreading Download PDF

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Publication number
WO2004059473A3
WO2004059473A3 PCT/US2003/040598 US0340598W WO2004059473A3 WO 2004059473 A3 WO2004059473 A3 WO 2004059473A3 US 0340598 W US0340598 W US 0340598W WO 2004059473 A3 WO2004059473 A3 WO 2004059473A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
thread
memory reference
speculative execution
simultaneous multithreading
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/040598
Other languages
French (fr)
Other versions
WO2004059473A2 (en
Inventor
Shailender Chaudhry
Marc Tremblay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AU2003303438A priority Critical patent/AU2003303438A1/en
Priority to EP03808497A priority patent/EP1576480A2/en
Publication of WO2004059473A2 publication Critical patent/WO2004059473A2/en
Publication of WO2004059473A3 publication Critical patent/WO2004059473A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)

Abstract

One embodiment of the present invention provides a system that generates prefetches by speculatively executing code during stalls through a technique known as 'hardware scout threading.' The system starts by executing code within a processor. Upon encountering a stall, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. If the system encounters a memory reference during this speculative execution, the system determines if a target address for the memory reference can be resolved. If so, the system issues a prefetch for the memory reference to load a cache line for the memory reference into a cache within the processor. In a variation on this embodiment, the processor supports simultaneous multithreading (SMT), which enables multiple threads to execute concurrently through time-multiplexed interleaving in a single processor pipeline. In this variation, the non-speculative execution is carried out by a first thread and the speculative execution is carried out by a second thread, wherein the first thread and the second thread simultaneously execute on the processor.
PCT/US2003/040598 2002-12-24 2003-12-19 Performing hardware scout threading in a system that supports simultaneous multithreading Ceased WO2004059473A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU2003303438A AU2003303438A1 (en) 2002-12-24 2003-12-19 Performing hardware scout threading in a system that supports simultaneous multithreading
EP03808497A EP1576480A2 (en) 2002-12-24 2003-12-19 Performing hardware scout threading in a system that supports simultaneous multithreading

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US43649202P 2002-12-24 2002-12-24
US60/436,492 2002-12-24

Publications (2)

Publication Number Publication Date
WO2004059473A2 WO2004059473A2 (en) 2004-07-15
WO2004059473A3 true WO2004059473A3 (en) 2005-06-09

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/040598 Ceased WO2004059473A2 (en) 2002-12-24 2003-12-19 Performing hardware scout threading in a system that supports simultaneous multithreading

Country Status (5)

Country Link
US (1) US20040133767A1 (en)
EP (1) EP1576480A2 (en)
AU (1) AU2003303438A1 (en)
TW (1) TWI260540B (en)
WO (1) WO2004059473A2 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040154010A1 (en) * 2003-01-31 2004-08-05 Pedro Marcuello Control-quasi-independent-points guided speculative multithreading
US8166282B2 (en) * 2004-07-21 2012-04-24 Intel Corporation Multi-version register file for multithreading processors with live-in precomputation
WO2006120367A1 (en) * 2005-05-11 2006-11-16 Arm Limited A data processing apparatus and method employing multiple register sets
WO2006122990A2 (en) * 2005-05-19 2006-11-23 Intel Corporation Storage-deployment apparatus, system and method for multiple sets of speculative-type instructions
US20080016325A1 (en) * 2006-07-12 2008-01-17 Laudon James P Using windowed register file to checkpoint register state
US7984272B2 (en) * 2007-06-27 2011-07-19 International Business Machines Corporation Design structure for single hot forward interconnect scheme for delayed execution pipelines
US7769987B2 (en) * 2007-06-27 2010-08-03 International Business Machines Corporation Single hot forward interconnect scheme for delayed execution pipelines
US8935489B2 (en) 2010-01-19 2015-01-13 Rambus Inc. Adaptively time-multiplexing memory references from multiple processor cores
US8601240B2 (en) * 2010-05-04 2013-12-03 Oracle International Corporation Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative execution
US8918626B2 (en) * 2011-11-10 2014-12-23 Oracle International Corporation Prefetching load data in lookahead mode and invalidating architectural registers instead of writing results for retiring instructions
US9697145B2 (en) 2015-06-12 2017-07-04 Apple Inc. Memory interface system
US11106494B2 (en) * 2018-09-28 2021-08-31 Intel Corporation Memory system architecture for multi-threaded processors
GB2580426B (en) * 2019-01-11 2021-06-30 Advanced Risc Mach Ltd Controlling use of data determined by a resolve-pending speculative operation
CN112052041B (en) * 2020-10-10 2022-03-11 乐鑫信息科技（上海）股份有限公司 Method for updating register

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020055964A1 (en) * 2000-04-19 2002-05-09 Chi-Keung Luk Software controlled pre-execution in a multithreaded processor
US20020116584A1 (en) * 2000-12-20 2002-08-22 Intel Corporation Runahead allocation protection (rap)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5393483A (en) * 1990-04-02 1995-02-28 General Electric Company High-temperature fatigue-resistant nickel based superalloy and thermomechanical process
US5395584A (en) * 1992-06-17 1995-03-07 Avco Corporation Nickel-base superalloy compositions
ATE218167T1 (en) * 1995-12-21 2002-06-15 Teledyne Ind NICKEL-CHROME-COBALT ALLOY WITH IMPROVED HIGH TEMPERATURE PROPERTIES
US5938863A (en) * 1996-12-17 1999-08-17 United Technologies Corporation Low cycle fatigue strength nickel base superalloys
US6065103A (en) * 1997-12-16 2000-05-16 Advanced Micro Devices, Inc. Speculative store buffer
US6175910B1 (en) * 1997-12-19 2001-01-16 International Business Machines Corportion Speculative instructions exection in VLIW processors
US6521175B1 (en) * 1998-02-09 2003-02-18 General Electric Co. Superalloy optimized for high-temperature performance in high-pressure turbine disks
US6468368B1 (en) * 2000-03-20 2002-10-22 Honeywell International, Inc. High strength powder metallurgy nickel base alloy
US6665776B2 (en) * 2001-01-04 2003-12-16 Hewlett-Packard Development Company L.P. Apparatus and method for speculative prefetching after data cache misses
US20020199179A1 (en) * 2001-06-21 2002-12-26 Lavery Daniel M. Method and apparatus for compiler-generated triggering of auxiliary codes
US7313676B2 (en) * 2002-06-26 2007-12-25 Intel Corporation Register renaming for dynamic multi-threading

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020055964A1 (en) * 2000-04-19 2002-05-09 Chi-Keung Luk Software controlled pre-execution in a multithreaded processor
US20020116584A1 (en) * 2000-12-20 2002-08-22 Intel Corporation Runahead allocation protection (rap)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DUNDAS J ET AL: "IMPROVING DATA CACHE PERFORMANCE BY PRE-EXECUTING INSTRUCTIONS UNDER A CACHE MISS", PROCEEDINGS OF THE 1997 INTERNATIONAL CONFERENCE ON SUPERCOMPUTING. VIENNA, JULY 7 - 11, 1997, PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON SUPERCOMPUTING, NEW YORK, ACM, US, vol. CONF. 11, 7 July 1997 (1997-07-07), pages 68 - 75, XP000755242, ISBN: 0-89791-902-5 *

Also Published As

Publication number Publication date
AU2003303438A1 (en) 2004-07-22
US20040133767A1 (en) 2004-07-08
TWI260540B (en) 2006-08-21
EP1576480A2 (en) 2005-09-21
AU2003303438A8 (en) 2004-07-22
WO2004059473A2 (en) 2004-07-15
TW200424931A (en) 2004-11-16

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