WO2005011120A1

WO2005011120A1 - Voltage controlled oscillator with drift compensation

Info

Publication number: WO2005011120A1
Application number: PCT/IB2004/002232
Authority: WO
Inventors: Patrick Attia; Dominique Delbecq; Michel Germe; Walter Jaudard
Original assignee: Koninklijke Philips Electronics NV
Current assignee: Koninklijke Philips NV
Priority date: 2003-07-31
Filing date: 2004-07-02
Publication date: 2005-02-03
Anticipated expiration: 2006-01-31

Abstract

The present invention relates to a transceiver adapted to transmit a radio-signal and to compensate for a drift frequency of a voltage controlled oscillator (VCO) included in said transceiver, wherein said transceiver comprises compensation means (CM) for applying a direct voltage input signal (VDCOMP) to the voltage controlled oscillator (VCO), said direct voltage input signal (VDCOMP) having a curve opposite to the drift frequency curve.

Description

Voltage controlled oscillator with drift compensation

FIELD OF THE INVENTION The present invention relates to a transceiver adapted to transmit a radio-signal and to a corresponding method to compensate for a drift frequency of a voltage controlled oscillator included in said transceiver. Such a transceiver may be used in, for example, a communication system in a mobile phone.

BACKGROUND OF THE INVENTION A communication system for radio-transmission in FM modulation can be found in any wireless telephone for example for voice transmission, said transmission having an emitting mode and a receiving mode. Such a system typically comprises a transceiver with a voltage controlled oscillator. A voltage controlled oscillator is an oscillator designed so that it outputs a central frequency and that said output frequency can be changed by applying a tuning voltage to its tuning port. The voltage controlled oscillator permits to synchronize said central frequency of the transceiver either with a receiving frequency or with a transmitting frequency. When the voltage controlled oscillator is running, the overheating of all the components of the transceiver results in a drift frequency, which is a frequency error (expressed as a relative percentage change per unit temperature, or as a frequency change per unit temperature or also in Hz, kHz) compared to a final wanted stabilised value of the central frequency at a fixed tuning voltage. This drift frequency prevents the voltage controlled oscillator from running according to its technical specifications and thus disrupts the whole running of the transceiver. One well-known solution to this problem is to apply a phase locked loop PLL as disclosed in the US patent US 5,382,922 referenced "Calibration systems and Methods for settling PLL Gain characteristics and Center Frequency". It permits to compensate for the drift frequency during the receiving mode. One drawback of such PLL is that it comprises a lot of components, resulting in high energy consumption. Moreover, it produces some noise that disturbs the other components of the transceiver.

SUMMARY OF THE INVENTION Accordingly, it is an object of the invention to provide a transceiver adapted to transmit a radio-signal, and a corresponding method to compensate for a drift frequency of a voltage controlled oscillator included in said transceiver, which allow to simply avoid the drift frequency effect in particular during the receiving and emitting modes and this without additional noise.

To this end, there is provided a transceiver adapted to transmit a radio-signal, said transceiver comprising a voltage controlled oscillator, wherein said transceiver comprises compensation means for applying a direct voltage input signal to the voltage controlled oscillator, said direct voltage input signal having a curve opposite to the drift frequency curve.

In addition, there is provided a method for transmitting a radio-signal and for processing a drift frequency of a voltage controlled oscillator, wherein said method comprises the step of applying a direct voltage input signal at the voltage controlled oscillator, said direct voltage input signal having a curve opposite to the drift frequency curve.

As we will see in detail further on, as the direct voltage input signal applied is opposite to the drift frequency, it permits to output a frequency that makes the drift frequency effect transparent for the whole transceiver.

Advantageously, said compensation means comprises a network with a resistor associated with a capacitor for inputting the direct voltage input signal. Preferably in a non-limited embodiment, said capacitor is external to the transceiver.

Advantageously, the compensation means is connected to a supply voltage for triggering/stopping said compensation means. Preferably, in a non-limited embodiment, the supply voltage used to trigger/stop the compensation means is the supply voltage of said voltage controlled oscillator.

Advantageously, the compensation means comprises a voltage divider for defining a maximum to the direct voltage input signal corresponding to a maximum drift frequency that can be reached in the transceiver. Preferably, in a non-limited embodiment, the values of the resistors within the voltage divider are smaller than the one of the resistor within the network.

BRIEF DESCRIPTION OF THE DRAWINGS Additional objects, features and advantages of the invention will become apparent upon reading the following detailed description and with reference to the accompanying drawings in which: - Fig. 1 illustrates a transceiver with a voltage controlled oscillator and compensation means according to the invention,

- Fig.2 is a graph showing a drift frequency, which appears in the voltage controlled oscillator of FigJ when the transceiver runs.

- Fig. 3 is a diagram showing a voltage input signal issued from the compensated means when the transceiver of Fig.1 runs,

- Fig. 4 is diagram showing a drift frequency compensation by the compensation means of FigJ,

- Fig. 5 is a diagram showing a voltage input signal issued from the compensation means when the transceiver of FigJ does not runs, - Fig. 6 is a diagram showing some drift frequency variations during a plurality of blind- active cycles of the voltage controlled oscillator of FigJ,

- Fig. 7 is a first diagram explaining the variations of the drift frequency of Fig.6, and

- Fig. 8 is a second diagram explaining the variations of the drift frequency of Fig.6.

DETAILED DESCRIPTION OF THE INVENTION In the following description, functions or constructions well known to the person skilled in the art are not described in detail since they would obscure the invention in unnecessary detail. The present invention relates to a communication system comprising a transceiver TR for radio-transmission in FM modulation, said transceiver comprising a voltage controlled oscillator VCO for outputting a central frequency FC according to a tuning voltage VT. Said transceiver is an integrated circuit. An example in radio-transmission in the DECT "Digital Enhanced Cordless

Telecommunications" standard referenced EN300- 175-1 VI.6J published by the ETSI is taken for the further description. Of course, it does not exclude other examples in other standards that deal with drift frequency in radio-transmission. Said transceiver TR is described in Fig.1. It comprises a phase locked loop

PLL and compensation means CM with a resistor Rl associated with a capacitor C. In addition, the transceiver preferably comprises a voltage divider R2R3. When the transceiver TR is running, a drift frequency DRIFT appears because of the heating of all the components of said transceiver. Said drift frequency is illustrated in Fig.2. Fig. 2 shows a drift frequency DRIFT in kHz plotted against time T in ms. The measures of the graph show said drift frequency DRIFT when the transceiver runs continuously during 8ms in open loop (the PLL is not used). It corresponds to a long period called active slot when the transceiver transmits or receives some voice information. As can be seen in the example of Fig.2, said drift frequency DRIFT is fitted with an exponential curve and its maximum variation is of Fmax=155kHz in the example taken. It can be approximated by the following equation: DRIFT= Fmax *(exp (-t/τ)-l) [1] with Fmax the maximum drift frequency reached in the transceiver TR.

In order to compensate for this drift frequency DRIFT, the compensation means CM issues a voltage input signal VDCOMP that is applied directly to the voltage controlled oscillator VCO as shown in Fig.1. It results in a frequency FDCOMP, which is produced by the voltage controlled oscillator VCO that compensates for the drift frequency DRIFT such that FDCOMP=FC+KDCOMP*VDCOMP [2] with the central frequency FC equal to 1.9GHz for the DECT standard and KDCOMP the gain of the voltage controlled oscillator VCO corresponding to the voltage input signal VDCOMP. Thus, when the drift frequency DRIFT is 10kHz for example, the gain KDCOMP and the voltage input signal VDCOMP have to be chosen so that the frequency obtained FDCOMP is 10kHz. For example if the gain KDCOMP is lOOOkHz/N and the voltage input signal is lOmV, it results in the right frequency value FDCOMP 10kHz. From the equation [2], one can see that the curve of the resulting frequency FDCOMP will have the same shape as the one of the voltage input signal VDCOMP applied within about the fixed central frequency FC and the gain KDCOMP. Hence, in order to compensate for the drift frequency that has an exponential curve, said voltage input signal VDCOMP has to have an exponential curve, which is opposite to the curve of said drift frequency DRIFT, so that Vdcomp=Vmax*(l-exp (-t/τ)) [3], with Vmax the maximum voltage input signal applied corresponding to the maximum drift frequency reached in the transceiver TR, Vmax=Fmax/KDCOMP [4]. Preferably, the gain KDCOMP taken is low compared to the gain of the voltage controlled oscillator VCO corresponding to the tuning voltage VT used by the phase locked loop PLL to reach the desired central frequency. It avoids having a low direct voltage input signal VDCOMP to compensate for the drift DRIFT. Indeed a low voltage is too sensitive to other disruptions such as noise or small voltage on the supply voltage or on the ground of the transceiver TR. For example, if one takes a gain KDCOMP equal to lOMHz/N to compensate for 10kHz, one has a voltage of lmV, which is a too low voltage. Hence, in the example taken, the gain corresponding to the tuning voltage VT is 60MHz/V and preferably KDCOMP is 730kHz/V.

In order to obtain the right direct voltage input signal VDCOMP, said voltage input signal is constructed from the network R1C of FigJ so that VDCOMP=Vmax*(l-exp (-t/τ)) with τ=Rl*C [5] when the capacitor C is charged. Advantageously, the capacitor C of this network R1C is external to the transceiver TR. It is connected to said transceiver via a pin (not represented on the FigJ). It permits to adjust the value of the capacitor C according to the drift frequency DRIFT that is to be compensated for. Thus, if the drift frequency DRIFT varies differently because of a different application for example, said capacitor C will be easily changed. Note that the term τ in the equation [5] is the same as the one in the equation [1] so that the curve of the direct voltage input signal VDCOMP undergoes the same variations (in the opposite way) as the curve of the drift frequency DRIFT. Thus, the direct voltage input signal VDCOMP will always compensate for the drift frequency DRIFT in an adequate manner, wherever the drift frequency variations are, as will be described below. The direct voltage input signal VDCOMP according to the equation [5] is illustrated in FigJ. The Y-axis represents the voltage in Volts, and the X-axis the time T in ms. The direct voltage input signal VDCOMP has an exponential curve with a maximum of Vmax=0.2V at time T=8ms and a minimum of 0V at T=0ms.

Fig. 4 shows a drift frequency signal DRIFT when it is compensated for by the direct voltage input signal VDCOMP of FigJ. The Y-axis is in kHz ranging from -100 to 80 kHz and the X-axis is the time T ranging from 0 to 8ms. The solid line shows the drift frequency DRIFT, the dotted line shows the drift signal compensated for. Thus, one can see that with the compensation, the drift frequency is cancelled. Note that 3 time intervals also called slots are illustrated in this Fig. 4. The first one is called blind TBLIND, the second is called active TACTIVE and the third is called power-down TPOWERDOWN. The blind interval TBLIND corresponds to the power-on of the transceiver and to the central frequency FC adjustment by means of the phase locked loop PLL via the tuning voltage VT. The active interval TACTIVE corresponds to the reception or transmission of information such as the voice by the transceiver. During this interval, the PLL is inactive and the drift frequency is present and is thus compensated for by the compensation means CM as described before. The power-down interval TPOWERDOWN corresponds to the power-down of the transceiver IC. The temperature of the transceiver returns to its usual value, which is the ambient temperature and the drift frequency returns to a zero value. When the transceiver runs, more specifically during the active interval

TACTIVE, the drift frequency DRIFT is compensated for by the direct voltage input signal VDCOMP such that VDCOMP=Vmax*(l-exp (-t/τ)) with τ=Rl*C as described before. The capacitor C is charged through the resistor Rl. Note that the maximum voltage Vmax is constant during all the time the transceiver runs, i.e. during a blind+active cycle. When the transceiver is powered-down, more specifically during the power- down interval TPOWERDOWN, the voltage controlled oscillator VCO outputs no frequency anymore, thus, there is no drift frequency DRIFT and the voltage input signal VDCOMP is such that VDCOMP=VS* (exp (-t/τ) - 1) [7] with τ=Rl*C and VS being the voltage value of the direct voltage input signal VDCOMP reached during the running interval. For example, in Fig. 3, at T=4ms, the voltage input signal VDCOMP has a value VS = 0J6V. The capacitor C is discharged through the resistor Rl to reach VDCOMP = 0V. Note that the equation [7] is the opposite to the equation [5] and is illustrated in Fig.5. Indeed, experiments have shown that the drift frequency DRIFT varies in the same way during the heating of the transceiver as during the cooling. This leads to a decreasing exponential curve and an increasing exponential curve respectively, with the same time constant τ as described previously. Hence, this also explains the shape of the curves of the direct voltage input signal VDCOMP during the blind+active cycle and during a power- down.

It can be noted that if the power-down of the transceiver does not last long enough so that the temperature of the transceiver has not reached the ambient temperature, in the next blind and active intervals, the drift frequency DRIFT will begin from a value which is not its initial point PT, for example 0, but which will take into account that there is still a heating of the transceiver TR. For example, if the power-down does not last long enough, the new initial point PT for the drift frequency will be the value 80kHz at T=2ms in Fig.2. In this case, the direct voltage input signal VDCOMP will have a corresponding value VS and for the next blind and active intervals it will begin from this value VS. For example in Fig.3, at T=2ms, it will begin from VS=0J2V. Thus, as can be seen, the capacitor C permits to store the fact that there has been a heating of the transceiver TR, and thanks to it, the direct voltage input signal VDCOMP will compensate adequately for the new variation of the drift signal DRIFT taking into account its new initial point PT.

Typically, during a radio-transmission, there are a plurality of intervals of power-on, reception-emission and power-down. During a first blind slot followed by a first active slot at T=500μs, and followed by a power-down slot beginning at t=lms and lasting for 4ms, the drift frequency DRIFT is the same for all the slots. But, when the power-down slot is followed by a plurality of blind+active cycles, the drift frequency DRIFT decreases during the active slot as can be seen on Fig.6. The X-axis represents the time T, which ranges from 0 to 6 ms, and the Y- axis represents the drift frequency in kHz and ranges from -50kHz to +50kHz. Each 500μs, there is a blind interval followed by an active interval that also lasts 500μs. Here 6 blind+active cycles are represented. Indeed, if the power-down interval is zero, the temperature of the components of the transceiver does not decrease and so it does not reach its usual value, i.e. the ambient temperature. Hence, neither does the drift frequency DRIFT. There is also a memory effect. Fig. 7 shows this memory effect. The X-axis is the time T ranging from 0 to 8ms, the Y-axis the drift frequency DRIFT ranging from -160kHz to 0 kHz. The curve of the drift frequency as illustrated in Fig.2 is represented in this Fig. in a dotted line (the first power-down interval that is not zero is not represented). When a plurality of cycles blind+active (B, A) is applied (a blind+active cycle each millisecond), in the end of the first cycle, at T=lms, the drift frequency is equal to FI, i.e. 21kHz. It is the difference between a frequency value at a final point PF2 and a frequency value at a first initial point PT1. At the following end cycle, at T= 2ms, the drift frequency is equal to F2, i.e. 14kHz. It is the difference between a frequency value at a second final point PF4 and a frequency value at a second initial point PT3. At the last active interval, the drift frequency is about 5kHz. It is the same effect as the one described before when the power-down is too short. Hence, another advantage of the compensation means CM is that the direct voltage input signal VDCOMP permits to compensate for the drift frequency DRIFT variations that can occur during a plurality of blind+active cycles when the power-down is zero, taking into account the right initial point of the drift frequency DRIFT. Note that during a blind interval TBLIND, there is also a drift frequency, still compensated for partly by the present invention as described above but this one is not observed at the output due to the loop locked (PLL). Indeed, the PLL permits to totally clean the few kHz left of the drift frequency if said drift frequency has not been totally compensated for by the compensation means CM of the transceiver TR. This compensation due to the PLL is represented in the FigJ by the horizontal lines on the line OkHz during the blind slots TBLIND (or B). Practically, for the following active slot, the drift frequency value will be the difference ΔF between a frequency value at another final point PF and a frequency value at another initial point PT. Thus, the Fig.8 illustrates the real shape of the drift frequency during a plurality of blind+active cycles. The X-axis is the time T ranging from 0 to 8 ms. The Y-axis is the drift frequency in kHz ranging from -25kHz to OkHz. At T=0ms, a blind slot begins and lasts for 500μs. Then begins an active slot that also lasts 500μs. All the blind slots and active slots last 500μs in the example of the Fig.8. In the first active slot, the drift frequency DRIFT of ΔFl=21kHz. In the second active slot, it is ΔF2=14kHz. Then it is ΔF3=10, ΔF4=7, ΔF5=5... 4, 3 and 2 kHz.

As can be seen, the compensation means CM has to be triggered and stopped in order to take into account the different states of the transceiver TR (power-on or power- down), and more specifically to manage the different states of the network R1C (charge, discharge). Therefore, preferably, a supply voltage VREG connected to the compensation means CM is used to trigger and to stop said compensation means CM. Preferably, the supply voltage VREG is the supply voltage of the voltage controlled oscillator VCO itself. Indeed, when the voltage controlled oscillator VCO runs, the supply voltage VREG runs and ranges from the value 0 to 2.3 V for example. The components of the transceiver TR begin to consume some energy resulting in the increase of the temperature of the circuit and thus in the drift frequency DRIFT. When the voltage controlled oscillator VCO does not run the supply voltage VREG does not run and the drift frequency DRIFT is zero.

As described before, the maximum voltage value Vmax is needed to construct the curve of the direct voltage input signal VDCOMP when the transceiver TR runs. In practice, in order to obtain this maximum voltage value Vmax corresponding to the maximum drift frequency Fmax, in a first non-limited embodiment, the voltage divider R2R3 with a supply voltage VREG is used such that Vmax = VREG*R3/(R2+R3). Thus, the equation [5] results in the new equation [8] VDCOMP = VREG*R3/(R2+R3)*(l-exp (-t/τ) when the transceiver runs. Preferably, the supply voltage VREG of the voltage controlled oscillator VCO is used.

As may be seen in the Fig. 1, the charge (when the transceiver runs, i.e., when VREG=2.3V) and the discharge (when the transceiver does not run, i.e. VREG = 0) of the capacitor C is obtained through the resistor (R1+(R2//R3)). The time constant τ is equal to (R1+(R2//R3))*C. Preferably, Rl is greater than R2//R3, resulting in τ=Rl *C. The term τ is the same when the transceiver runs or does not run in order to store the right heating of the temperature of said transceiver. The direct voltage input signal VDCOMP obtained when the transceiver runs then results in the equation [5] and is illustrated in FigJ as described before. The voltage input signal VDCOMP obtained when the transceiver does not run then results in the equation [7] and is illustrated in Fig.45. Practically, in the example taken, the following values are applied for the voltage divider R2R3 and the network RIC. Rl=340kΩ C = 8.2nF τ=2.8ms R2=80kΩ, R3=8kΩ, Note that, the current in the voltage divider R2R3 is preferably equal to VREG/(R2+R3) and is 25 μA maximum. It avoids having considerable consumption in terms of energy.

Thus, the drift frequency DRIFT, which occurs during the emitting or receiving modes, is compensated for by the means of the compensation means CM of the transceiver according to the invention, and thus, the transceiver TR is able to run within its technical specifications. Moreover, as the phase locked loop PLL is not used during the active slot (the communication system comprising the transceiver is in open loop), the compensation of the drift frequency DRIFT is simpler and noiseless. The compensation means also permits to compensate partly for the drift frequency during the blind slot. Furthermore, the compensation is adaptable because it permits to follow adequately the variations of the drift frequency DRIFT, taking into account the different initial points of said drift frequency according to the heating of the components of said transceiver. Another advantage is that the compensation of said drift frequency is performed without a complex system using only a network RIC. The capacitor C of said network RIC is external to the transceiver and can be easily replaced with another one that fits with the drift frequency to be compensated. Finally, the maximum input voltage signal Vmax is obtained by means of a simple system R2R3. And said system does not alter the compensation of the drift frequency as the values of this system are taken such that they are smaller than the value of the resistor of the network RIC.

It is to be understood that the present invention is not limited to the aforementioned embodiments and variations and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims. In this respect, the following closing remarks are made. It is to be understood that the present invention is not limited to the aforementioned mobile phone application. It can be used in any application using a system with a voltage controlled oscillator where a drift frequency occurs, in automobile applications for example. It is to be understood that the method according to the present invention is not limited to the aforementioned implementation. There are numerous ways of implementing functions of the method according to the invention by means of items of hardware or software, or both, provided that a single item of hardware or software can carry out several functions. It does not exclude that an assembly of items of hardware or software or both carry out a function, thus forming a single function without modifying the method of processing the drift frequency in accordance with the invention. Said hardware or sof ware items can be implemented in several manners, such as by means of wired electronic circuits or by means of an integrated circuit that is suitably programmed respectively. The integrated circuit can be contained in a computer or in a mobile phone. In the second case, the mobile phone comprises compensation means adapted to apply a direct voltage input signal to the voltage controlled oscillator, said direct voltage input signal having a curve opposite to the drift frequency curve, as described previously, said means being hardware or software items as above stated. The integrated circuit comprises a set of instructions. Thus, said set of instructions contained, for example, in a computer programming memory or in a mobile phone memory may cause the computer or the mobile phone to carry out the different steps of the method for processing a drift frequency. The set of instructions may be loaded into the programming memory by reading a data carrier such as, for example, a disk. A service provider can also make the set of instructions available via a communication network such as, for example, the Internet. Any reference sign in the following claims should not be construed as limiting the claim. It will be obvious that the use of the verb "to comprise" and its conjugations do not exclude the presence of any other steps or elements besides those defined in any claim. The article "a" or "an" preceding an element or step does not exclude the presence of a plurality of such elements or steps.

Claims

1. Transceiver adapted to transmit a radio-signal and to compensate for a drift frequency (DRIFT) of a voltage controlled oscillator (VCO) included in said transceiver, wherein said transceiver comprises compensation means (CM) for applying a direct voltage input signal (VDCOMP) to the voltage controlled oscillator (VCO), said direct voltage input signal (VDCOMP) having a curve opposite to the drift frequency curve.

2. Transceiver as claimed in claim 1, wherein said compensation means (CM) comprises a network (RIC) with a resistor (R) associated with a capacitor (C) for inputting the direct voltage input signal (VDCOMP).

3. Transceiver as claimed in claim 2, wherein said capacitor (C) is external to the transceiver.

4. Transceiver as claimed in claim 1, wherein the compensation means (CM) is connected to a supply voltage (VREG) for triggering/stopping said compensation means (CM).

5. Transceiver as claimed in claim 4, wherein the supply voltage (VREG) used to trigger/stop the compensation means (CM) is the supply voltage (VREG) of said voltage controlled oscillator (VCO).

Transceiver as claimed in claim 1, wherein the compensation means (CM) comprises a voltage divider (R2R3) for defining a maximum (VMAX) to the direct voltage input signal (VDCOMP) corresponding to a maximum drift frequency (FMAX) that can be reached in the transceiver.

Transceiver as claimed in claim 6, wherein the values of the resistors within the voltage divider (R2R3) are smaller than the one of the resistor within the network (RIC).

8. Method for transmitting a radio-signal and for processing a drift frequency (DRIFT) of a voltage controlled oscillator (VCO), wherein said method comprises the step of applying a direct voltage input signal (VDCOMP) at the voltage controlled oscillator (VCO), said direct voltage input signal (VDCOMP) having a curve opposite to the drift frequency curve.

9. A computer program product comprising program instructions for implementing a drift frequency processing method as claimed in claim 8 when said program is executed by a processor.

10. Mobile phone comprising a transceiver as claimed in claim 1.