WO2005017760A3 - Split t-chain memory command and address bus topology - Google Patents

Split t-chain memory command and address bus topology Download PDF

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Publication number
WO2005017760A3
WO2005017760A3 PCT/US2004/025220 US2004025220W WO2005017760A3 WO 2005017760 A3 WO2005017760 A3 WO 2005017760A3 US 2004025220 W US2004025220 W US 2004025220W WO 2005017760 A3 WO2005017760 A3 WO 2005017760A3
Authority
WO
WIPO (PCT)
Prior art keywords
dimm
signal
dram
split
memory command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2004/025220
Other languages
French (fr)
Other versions
WO2005017760A2 (en
Inventor
Michael Leddige
James Mccall
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to DE602004012113T priority Critical patent/DE602004012113T2/en
Priority to EP04780114A priority patent/EP1652097B1/en
Publication of WO2005017760A2 publication Critical patent/WO2005017760A2/en
Publication of WO2005017760A3 publication Critical patent/WO2005017760A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4239—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with asynchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

Embodiments of the invention provide a memory command and address (CA) bus architecture that can accommodate higher CA data output frequencies with reduced signal degradation. For one embodiment of the invention the CA is divided on the motherboard and a CA signal component routed to each of two dual in-line memory modules (DIMMs) of a two-DIMM/channel memory bus design. The CA signal component on each DIMM is then routed sequentially through each dynamic random access memory (DRAM) chip on the respective DIMM. In one embodiment, after routing through each DRAM, the CA signal is terminated on the DIMM. In an alternative embodiment, the CA signal is terminated on the die at the last DRAM of each respective DIMM.
PCT/US2004/025220 2003-08-08 2004-08-04 Split t-chain memory command and address bus topology Ceased WO2005017760A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE602004012113T DE602004012113T2 (en) 2003-08-08 2004-08-04 COMMAND AND ADDRESS BUSTOPOLOGY WITH DISTRIBUTED T-CHAIN STORAGE
EP04780114A EP1652097B1 (en) 2003-08-08 2004-08-04 Split t-chain memory command and address bus topology

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/638,069 US7194572B2 (en) 2003-08-08 2003-08-08 Memory system and method to reduce reflection and signal degradation
US10/638,069 2003-08-08

Publications (2)

Publication Number Publication Date
WO2005017760A2 WO2005017760A2 (en) 2005-02-24
WO2005017760A3 true WO2005017760A3 (en) 2005-06-30

Family

ID=34116714

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/025220 Ceased WO2005017760A2 (en) 2003-08-08 2004-08-04 Split t-chain memory command and address bus topology

Country Status (6)

Country Link
US (1) US7194572B2 (en)
EP (1) EP1652097B1 (en)
CN (1) CN100456275C (en)
AT (1) ATE387668T1 (en)
DE (1) DE602004012113T2 (en)
WO (1) WO2005017760A2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7133962B2 (en) * 2003-09-09 2006-11-07 Intel Corporation Circulator chain memory command and address bus topology
US20070189049A1 (en) * 2006-02-16 2007-08-16 Srdjan Djordjevic Semiconductor memory module
DE102008010544A1 (en) 2008-02-22 2009-09-17 Qimonda Ag Memory module for use in e.g. personal computer, to store digital data in dynamic RAM, has termination device switchably implemented at end of command and address bus connected, where bus is guided sequentially through memory chips
US7944726B2 (en) * 2008-09-30 2011-05-17 Intel Corporation Low power termination for memory modules
US8225069B2 (en) * 2009-03-31 2012-07-17 Intel Corporation Control of on-die system fabric blocks
JP5471631B2 (en) * 2010-03-10 2014-04-16 セイコーエプソン株式会社 Electronics
US20150227461A1 (en) * 2012-10-31 2015-08-13 Hewlett-Packard Development Company, Lp. Repairing a memory device
WO2014085268A1 (en) 2012-11-30 2014-06-05 Intel Corporation Apparatus, method and system for memory device access with a multi-cycle command
US9489323B2 (en) * 2013-02-20 2016-11-08 Rambus Inc. Folded memory modules
CN105828822B (en) 2013-08-14 2019-10-18 诺华股份有限公司 Combination therapy for the treatment of cancer
JP6434870B2 (en) * 2015-07-28 2018-12-05 ルネサスエレクトロニクス株式会社 Electronic equipment
US10146711B2 (en) 2016-01-11 2018-12-04 Intel Corporation Techniques to access or operate a dual in-line memory module via multiple data channels
TWI717092B (en) * 2018-11-07 2021-01-21 財團法人工業技術研究院 Reconfigurable data bus system and method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668834A (en) * 1993-12-28 1997-09-16 Hitachi, Ltd. Signal transmitting device suitable for fast signal transmission including an arrangement to reduce signal amplitude in a second stage transmission line
US6125419A (en) * 1996-06-13 2000-09-26 Hitachi, Ltd. Bus system, printed circuit board, signal transmission line, series circuit and memory module
WO2002084428A2 (en) * 2000-12-22 2002-10-24 Micron Technology, Inc. High speed interface with looped bus

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6587912B2 (en) * 1998-09-30 2003-07-01 Intel Corporation Method and apparatus for implementing multiple memory buses on a memory module
US6882082B2 (en) * 2001-03-13 2005-04-19 Micron Technology, Inc. Memory repeater
US6757755B2 (en) * 2001-10-15 2004-06-29 Advanced Micro Devices, Inc. Peripheral interface circuit for handling graphics responses in an I/O node of a computer system
KR100502408B1 (en) * 2002-06-21 2005-07-19 삼성전자주식회사 Memory system for controlling power-up sequence of memory device embedding active termination and the method of power-up and initialization thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5668834A (en) * 1993-12-28 1997-09-16 Hitachi, Ltd. Signal transmitting device suitable for fast signal transmission including an arrangement to reduce signal amplitude in a second stage transmission line
US6125419A (en) * 1996-06-13 2000-09-26 Hitachi, Ltd. Bus system, printed circuit board, signal transmission line, series circuit and memory module
WO2002084428A2 (en) * 2000-12-22 2002-10-24 Micron Technology, Inc. High speed interface with looped bus

Also Published As

Publication number Publication date
DE602004012113D1 (en) 2008-04-10
DE602004012113T2 (en) 2009-02-19
WO2005017760A2 (en) 2005-02-24
CN100456275C (en) 2009-01-28
EP1652097A2 (en) 2006-05-03
US20050033905A1 (en) 2005-02-10
EP1652097B1 (en) 2008-02-27
US7194572B2 (en) 2007-03-20
ATE387668T1 (en) 2008-03-15
CN1860461A (en) 2006-11-08

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