WO2005045904A2 - Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation - Google Patents
Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation Download PDFInfo
- Publication number
- WO2005045904A2 WO2005045904A2 PCT/US2004/034803 US2004034803W WO2005045904A2 WO 2005045904 A2 WO2005045904 A2 WO 2005045904A2 US 2004034803 W US2004034803 W US 2004034803W WO 2005045904 A2 WO2005045904 A2 WO 2005045904A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- bias
- frequency
- modulated
- substrate
- vacuum chamber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P50/00—Etching of wafers, substrates or parts of devices
- H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
- H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
- H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
- H10P50/244—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials comprising alternated and repeated etching and passivation steps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
- H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
Definitions
- the present invention relates generally to the manufacture of
- present invention relates to the manufacture of high aspect ratio silicon
- MEMS microelectromechanical
- TDM Time Division Multiplexed
- a reactor configured with a high-density plasma source, such as an
- ICP Inductively Coupled Plasma
- the TDM etch process for silicon are sulfur hexafluoride and
- SF ⁇ sulfur hexafluoride
- the TDM process cyclically alternates between
- TDM approach allows high aspect ratio features to be defined into silicon
- a complex TDM process may incorporate
- Certain MEMS devices require that the silicon substrate be etched
- silicon dioxide Si ⁇ 2
- SOI structure Silicon On Insulator, SOI structure
- SOI structure Silicon On Insulator
- substrate is sufficiently conductive, current flow within the substrate
- RIE reactive ion etching
- TDM deposition / etch process has also been described by Hopkins et al.
- RF bias power is also disclosed, including the case of pulsing between
- Another object of the present invention is to provide a method for
- etching a feature in a substrate comprising the steps of: placing the
- an etching step comprising introducing a
- a passivation step comprising
- Yet another object of the present invention is to provide an
- apparatus for etching a feature in a substrate comprising: a vacuum chamber; at least one gas supply source for supplying at least one process
- this invention comprises an improved method and an apparatus for deep silicon trench
- TDM multiplexed
- a feature of the present invention is to provide a method for etching
- the substrate can be a semiconductor substrate
- the substrate may also be a
- the substrate support is a lower electrode to which is
- One part of the process is an etching step which is carried out
- a first process gas such as Sulfur hexafluoride
- process is a passivation step which is carried out by introducing a second
- process gas such as octofluorocyclobutane into the vacuum chamber.
- second plasma is generated from the second process gas to deposit a
- the passivation layer consists of a
- polymer or a fluorocarbon polymer can be silicon, carbon, nitride or any
- the bias can be voltage controlled.
- the bias can be any bias
- the bias can be switched between two distinct frequencies
- the switching is defined by a switching rate and a switching
- the switching rate can be less than about 10kHz and the
- the RF bias frequency can be
- the RF bias can additionally be amplitude modulated.
- the RF bias can be phase modulated or wave shaped modulated.
- Still yet another feature of the present invention is to provide an
- the apparatus for etching a feature in a substrate.
- the apparatus comprising
- a vacuum chamber having at least one gas supply source for supplying at
- a lower electrode is positioned
- a substrate holder that is connected to the lower electrode.
- plasma source generates a plasma within the vacuum chamber.
- the bias can be powered
- bias is powered by RF or DC power. If the bias is powered by an RF source, it can be
- the frequency of the RF bias can be phase
- Figures l(a-d) is a pictorial example of one type of the TDM process
- Figure 1(e) is a typical scanning electron microscopy photograph of
- Figure 2 is a scanning electron microscopy photograph of an etch
- Figures 3A and 3B are a pictorial of charge buildup at the surface of
- Figure 4 is a graph of amplitude versus time showing a pulsed
- Figure 5 is a graph of amplitude versus time showing frequency
- Figure 6 is a graph of amplitude versus time showing continuous
- Figure 7 is a schematic of a plasma reactor configured for providing
- Figure 8 is a schematic of a plasma reactor configured for providing
- Figure 9 is a scanning electron microscopy photograph of an etch
- the present invention provides a method and apparatus for
- bias voltage applied to the cathode is changed between at least two frequencies, either discretely switched ( Figure 5) or continuously
- wave shaped modulation it is meant that the bias voltage
- waveform to the cathode is changed between at least two shapes, either
- Such waveform shapes may be, for example
- phase modulated bias it is meant that the bias waveform is
- a reactor 10 configured for frequency modulated RF bias is shown
- the reactor 10 shown comprises a vacuum chamber 12, a gas
- modulation signal generator 30 that is connected to a voltage control
- modulated RF bias is not limited to this configuration and one skilled in
- waveform can be digitally synthesized and applied to the broadband
- the RF Bias frequency is preferentially modulated during the etch sub-cycle of the
- the RF bias frequency can also be modulated through both deposition and etch sub-cycles.
- the duration of the RF Bias high-frequency state should be short enough that charge build-up on the feature surfaces has not reached a
- time scale is typically on the order of a few microseconds to a few milliseconds.
- the duration of the low-frequency RF bias state should be
- the low-frequency duration should also be of the
- cycle period should be in the range of 5-90%, preferably 10-50%
- the RF bias frequency for the high-frequency state should be below
- ⁇ p ( e n 0 / ⁇ 0 M ) ⁇ Where e - charge on an electron n 0 - ion density ⁇ 0 - permittivity in a vacuum M - mass of the ion
- the ion transit frequency is approximately 2 MHz. Notching performance is improved by using a high frequency state in the range of
- a preferred embodiment uses a high frequency state in the range of 50kHz to 300kHz and a low frequency state in the range of
- the etch step proceeds in two
- This passivation removal process typically follows an ion assisted etch
- Si then proceeds to etch by a primarily chemical etch mechanism.
- the amplitude of the modulated bias is
- the amplitude can be switched discreetly between two
- a sequence refers to a group of deposition and/or etch steps. In the single sequence implementation,
- the first sequence can be
- TDM TDM or conventional plasma etch process
- the RF bias need only be
- the etch is completed using a modulated RF bias
- finish etch to avoid notching at the silicon/insulator interface.
- Etch endpoint detection methods such as laser reflectance and
- OES optical emission spectroscopy
- the ICP power can be maintained "on" continuously during the etch
- This pulsing can be either in phase with the
- RF bias modulation i.e., the ICP is "on" when the RF bias frequency
- ICP is "on" when the RF bias frequency or amplitude is low) or can bear
- phase shifted some other phase relationship to the RF bias (i.e., can be phase shifted).
- a reactor 10 configured for a modulated RF bias in conjunction with a modulated high density source is shown in Figure 8.
- the reactor 10 is shown in Figure 8.
- a vacuum chamber 12 a gas inlet 14, an exhaust 16, an
- inductively coupled plasma power source (RF generator) 20 that is connected to a first impedance matching network 21 that provides power
- a modulation signal generator 30 that is connected to both the RF Generator 20 and an RF Bias
- the high density source 36 that supplies power to the lower electrode 24.
- ECR ECR
- helicon helicon
- TCP TCP
- the notch at the silicon-insulator interface is evident, and extends ⁇ 3 ⁇ m
- the reactor is a commercially
- the modulated RF bias is amplified and is applied through an impedance matching network to the electrode.
- the test pattern used to characterize the notch performance has ⁇
- the oxide layer acts as an
- the lines are 4 ⁇ m wide and spaces range from the
- the resist is ⁇
- the TDM Si finish etch (present invention) is made using an optical
- Si finish etch is shown in Figure 9.
Landscapes
- Drying Of Semiconductors (AREA)
- Micromachines (AREA)
- Peptides Or Proteins (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006536773A JP2007509506A (en) | 2003-10-21 | 2004-10-19 | High-aspect SOI structure notch-etching using time division multiplexing and RF bias modulation |
| EP04817803A EP1676302B1 (en) | 2003-10-21 | 2004-10-19 | Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation |
| DE602004018531T DE602004018531D1 (en) | 2003-10-21 | 2004-10-19 | TOOL-FREE SEEDING OF SOI STRUCTURES WITH HIGH SEULTIPLEXED PROCESSES AND HF PREMODULATION |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US51293303P | 2003-10-21 | 2003-10-21 | |
| US60/512,933 | 2003-10-21 | ||
| US10/968,823 | 2004-10-18 | ||
| US10/968,823 US20050112891A1 (en) | 2003-10-21 | 2004-10-18 | Notch-free etching of high aspect SOI structures using a time division multiplex process and RF bias modulation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2005045904A2 true WO2005045904A2 (en) | 2005-05-19 |
| WO2005045904A3 WO2005045904A3 (en) | 2005-09-09 |
Family
ID=34576731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2004/034803 Ceased WO2005045904A2 (en) | 2003-10-21 | 2004-10-19 | Notch-free etching of high aspect soi structures using a time division multiplex process and rf bias modulation |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US20050112891A1 (en) |
| EP (1) | EP1676302B1 (en) |
| JP (1) | JP2007509506A (en) |
| AT (1) | ATE418157T1 (en) |
| DE (1) | DE602004018531D1 (en) |
| WO (1) | WO2005045904A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009539267A (en) * | 2006-05-30 | 2009-11-12 | ラム リサーチ コーポレーション | Method for minimizing mask undercuts and notches in plasma processing systems |
| GB2499816A (en) * | 2012-02-29 | 2013-09-04 | Oxford Instr Nanotechnology Tools Ltd | Controlling deposition and etching in a chamber with fine time control of parameters and gas flow |
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|---|---|---|---|---|
| EP1761947B1 (en) * | 2004-06-29 | 2015-02-25 | Unaxis USA Inc. | Method for reducing aspect ratio dependent etching in time division multiplexed etch processes |
| US7749400B2 (en) * | 2005-12-16 | 2010-07-06 | Jason Plumhoff | Method for etching photolithographic substrates |
| JP5082338B2 (en) * | 2006-08-25 | 2012-11-28 | 東京エレクトロン株式会社 | Etching method and etching apparatus |
| US7682986B2 (en) * | 2007-02-05 | 2010-03-23 | Lam Research Corporation | Ultra-high aspect ratio dielectric etch |
| US7547636B2 (en) * | 2007-02-05 | 2009-06-16 | Lam Research Corporation | Pulsed ultra-high aspect ratio dielectric etch |
| US7718538B2 (en) * | 2007-02-21 | 2010-05-18 | Applied Materials, Inc. | Pulsed-plasma system with pulsed sample bias for etching semiconductor substrates |
| US7771606B2 (en) * | 2007-02-22 | 2010-08-10 | Applied Materials, Inc. | Pulsed-plasma system with pulsed reaction gas replenish for etching semiconductors structures |
| US7737042B2 (en) * | 2007-02-22 | 2010-06-15 | Applied Materials, Inc. | Pulsed-plasma system for etching semiconductor structures |
| KR20100128333A (en) * | 2008-03-21 | 2010-12-07 | 어플라이드 머티어리얼스, 인코포레이티드 | Method and apparatus of substrate etching system and process |
| JP2010118549A (en) | 2008-11-13 | 2010-05-27 | Tokyo Electron Ltd | Plasma etching method and plasma etching device |
| JP2011100760A (en) * | 2009-11-04 | 2011-05-19 | Ulvac Japan Ltd | Etching method |
| US8658541B2 (en) * | 2010-01-15 | 2014-02-25 | Applied Materials, Inc. | Method of controlling trench microloading using plasma pulsing |
| US9373521B2 (en) | 2010-02-24 | 2016-06-21 | Tokyo Electron Limited | Etching processing method |
| US9070760B2 (en) * | 2011-03-14 | 2015-06-30 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
| US8802545B2 (en) * | 2011-03-14 | 2014-08-12 | Plasma-Therm Llc | Method and apparatus for plasma dicing a semi-conductor wafer |
| JP5718124B2 (en) | 2011-03-30 | 2015-05-13 | 株式会社日立ハイテクノロジーズ | Plasma processing apparatus and plasma processing method |
| US8758638B2 (en) * | 2011-05-10 | 2014-06-24 | Applied Materials, Inc. | Copper oxide removal techniques |
| US8609548B2 (en) * | 2011-06-06 | 2013-12-17 | Lam Research Corporation | Method for providing high etch rate |
| US20130119018A1 (en) * | 2011-11-15 | 2013-05-16 | Keren Jacobs Kanarik | Hybrid pulsing plasma processing systems |
| US8883028B2 (en) * | 2011-12-28 | 2014-11-11 | Lam Research Corporation | Mixed mode pulsing etching in plasma processing systems |
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| JP5967710B2 (en) * | 2012-09-28 | 2016-08-10 | サムコ株式会社 | End point detection method of plasma etching |
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| US9653316B2 (en) * | 2013-02-18 | 2017-05-16 | Tokyo Electron Limited | Plasma processing method and plasma processing apparatus |
| JP6173086B2 (en) * | 2013-07-19 | 2017-08-02 | キヤノン株式会社 | Etching method of silicon substrate |
| US20150371889A1 (en) * | 2014-06-20 | 2015-12-24 | Applied Materials, Inc. | Methods for shallow trench isolation formation in a silicon germanium layer |
| US9978606B2 (en) * | 2015-10-02 | 2018-05-22 | Applied Materials, Inc. | Methods for atomic level resolution and plasma processing control |
| US9691625B2 (en) * | 2015-11-04 | 2017-06-27 | Lam Research Corporation | Methods and systems for plasma etching using bi-modal process gas composition responsive to plasma power level |
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-
2004
- 2004-10-18 US US10/968,823 patent/US20050112891A1/en not_active Abandoned
- 2004-10-19 EP EP04817803A patent/EP1676302B1/en not_active Expired - Lifetime
- 2004-10-19 WO PCT/US2004/034803 patent/WO2005045904A2/en not_active Ceased
- 2004-10-19 DE DE602004018531T patent/DE602004018531D1/en not_active Expired - Lifetime
- 2004-10-19 JP JP2006536773A patent/JP2007509506A/en active Pending
- 2004-10-19 AT AT04817803T patent/ATE418157T1/en not_active IP Right Cessation
-
2007
- 2007-04-16 US US11/681,004 patent/US20070175856A1/en not_active Abandoned
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009539267A (en) * | 2006-05-30 | 2009-11-12 | ラム リサーチ コーポレーション | Method for minimizing mask undercuts and notches in plasma processing systems |
| GB2499816A (en) * | 2012-02-29 | 2013-09-04 | Oxford Instr Nanotechnology Tools Ltd | Controlling deposition and etching in a chamber with fine time control of parameters and gas flow |
| WO2013128181A1 (en) * | 2012-02-29 | 2013-09-06 | Oxford Instruments Nanotechnology Tools Limited | Methods and apparatus for depositing and/or etching material on a substrate |
| US9412566B2 (en) | 2012-02-29 | 2016-08-09 | Oxford Instruments Nanotechnology Tools Limited | Methods and apparatus for depositing and/or etching material on a substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| US20070175856A1 (en) | 2007-08-02 |
| EP1676302A2 (en) | 2006-07-05 |
| JP2007509506A (en) | 2007-04-12 |
| EP1676302B1 (en) | 2008-12-17 |
| ATE418157T1 (en) | 2009-01-15 |
| DE602004018531D1 (en) | 2009-01-29 |
| US20050112891A1 (en) | 2005-05-26 |
| WO2005045904A3 (en) | 2005-09-09 |
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