WO2005069122A3 - Procede cryptographique d'exponentiation modulaire protege contre les attaques de type dpa - Google Patents

Procede cryptographique d'exponentiation modulaire protege contre les attaques de type dpa Download PDF

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Publication number
WO2005069122A3
WO2005069122A3 PCT/EP2004/053472 EP2004053472W WO2005069122A3 WO 2005069122 A3 WO2005069122 A3 WO 2005069122A3 EP 2004053472 W EP2004053472 W EP 2004053472W WO 2005069122 A3 WO2005069122 A3 WO 2005069122A3
Authority
WO
WIPO (PCT)
Prior art keywords
bits
accumulator
modular exponentiation
protected against
against dpa
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2004/053472
Other languages
English (en)
Other versions
WO2005069122A2 (fr
Inventor
Benoit Chevallier-Mames
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Gemplus SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA, Gemplus SA filed Critical Gemplus Card International SA
Priority to EP04804829A priority Critical patent/EP1695204A2/fr
Publication of WO2005069122A2 publication Critical patent/WO2005069122A2/fr
Publication of WO2005069122A3 publication Critical patent/WO2005069122A3/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/723—Modular exponentiation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7276—Additional details of aspects covered by group G06F7/723
    • G06F2207/7285—Additional details of aspects covered by group G06F7/723 using the window method, i.e. left-to-right k-ary exponentiation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G06F7/725—Finite field arithmetic over elliptic curves

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
  • Computing Systems (AREA)
  • Storage Device Security (AREA)
  • Complex Calculations (AREA)

Abstract

Dans le domaine de la protection des procédés cryptographiques contre les attaques à canaux cachés de type DPA, l'invention concerne un procédé cryptographique au cours duquel on réalise une exponentiation modulaire de type x^d, avec d un exposant entier de m+1 bits, en balayant les bits de d de gauche à droite dans une boucle indicée par i variant de m à 0 et en calculant et en mémorisant dans un accumulateur (RO), à chaque tour de rang i, un résultat partiel actualisé égal à x^b(i), b(i) étant les m-i+1 bits de poids les plus forts de l'exposant d ( b (i) = dm->i) .Selon l'invention, à la fin d'un tour de rang i(j) (i = i(0)) choisi aléatoirement, on réalise une étape E1 de randomisation au cours de laquelle E1: on soustrait un nombre z (z= b(i(j)), z = b (i(j)) .2τ, z = u) aléatoire à une partie des bits de d non encore utilisés ( di-1->0) dans le procédé puis, après avoir utilisé les bits de d modifiés par l'étape de randomisation E1, on réalise une étape de consolidation E2 au cours de laquelle: E2 : on mémorise (R0 <- R1xR0) dans l'accumulateur (RO) le résultat de la multiplication du contenu de l'accumulateur (x^b(i)) par un nombre fonction de x^z mémorisé dans un registre (R1).
PCT/EP2004/053472 2003-12-19 2004-12-14 Procede cryptographique d'exponentiation modulaire protege contre les attaques de type dpa Ceased WO2005069122A2 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04804829A EP1695204A2 (fr) 2003-12-19 2004-12-14 Procede d'exponentiation modulaire protege contre les attaques du type dpa

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0314959 2003-12-19
FR0314959A FR2864390B1 (fr) 2003-12-19 2003-12-19 Procede cryptographique d'exponentiation modulaire protege contre les attaques de type dpa.

Publications (2)

Publication Number Publication Date
WO2005069122A2 WO2005069122A2 (fr) 2005-07-28
WO2005069122A3 true WO2005069122A3 (fr) 2006-06-01

Family

ID=34630319

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2004/053472 Ceased WO2005069122A2 (fr) 2003-12-19 2004-12-14 Procede cryptographique d'exponentiation modulaire protege contre les attaques de type dpa

Country Status (4)

Country Link
EP (1) EP1695204A2 (fr)
CN (1) CN1918543A (fr)
FR (1) FR2864390B1 (fr)
WO (1) WO2005069122A2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2888690A1 (fr) * 2005-07-13 2007-01-19 Gemplus Sa Procede cryptographique pour la mise en oeuvre securisee d'une exponentiation et composant associe
JP5482048B2 (ja) * 2009-09-18 2014-04-23 ソニー株式会社 集積回路および電子機器
FR2972064B1 (fr) * 2011-02-25 2013-03-15 Inside Secure Procede de cryptographie comprenant une operation d'exponentiation

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001031436A1 (fr) * 1999-10-28 2001-05-03 Bull Cp8 Procede de securisation d'un ensemble electronique de cryptographie a base d'exponentiation modulaire contre les attaques par analyse physique
FR2829646A1 (fr) * 2001-09-07 2003-03-14 Gemplus Card Int Procede securise de mise en oeuvre d'un algorithme de cryptographie et composant correspondant

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001031436A1 (fr) * 1999-10-28 2001-05-03 Bull Cp8 Procede de securisation d'un ensemble electronique de cryptographie a base d'exponentiation modulaire contre les attaques par analyse physique
FR2829646A1 (fr) * 2001-09-07 2003-03-14 Gemplus Card Int Procede securise de mise en oeuvre d'un algorithme de cryptographie et composant correspondant

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
CHEVALLIER-MAMES B: "Self-randomized exponentiation algorithms", TOPICS IN CRYPTOLOGY - CT-RSA 2004. PROCEEDINGS. SPRINGER-VERLAG, LECTURE NOTES IN COMPUTER SCIENCE, vol. 2964, 27 February 2004 (2004-02-27), BERLIN, GERMANY, pages 236 - 249, XP002297836, ISBN: 3-540-20996-4 *
ITOH K ET AL: "DPA COUNTERMEASURES BY IMPROVING THE WINDOW METHOD", CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS. INTERNATIONAL WORKSHOP, XX, XX, 13 August 2002 (2002-08-13), pages 303 - 317, XP001160529 *
JOYE M: "Recovering lost efficiency of exponentiation algorithms on smart cards", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 38, no. 19, 12 September 2002 (2002-09-12), pages 1095 - 1097, XP006019065, ISSN: 0013-5194 *
WALTER C D: "MIST: AN EFFICIENT, RANDOMIZED EXPONENTIATION ALGORITHM FOR RESISTING POWER ANALYSIS", LECTURE NOTES IN COMPUTER SCIENCE, SPRINGER VERLAG, NEW YORK, NY, US, vol. 2271, 18 February 2002 (2002-02-18), pages 53 - 66, XP008004946, ISSN: 0302-9743 *

Also Published As

Publication number Publication date
CN1918543A (zh) 2007-02-21
FR2864390B1 (fr) 2006-03-31
EP1695204A2 (fr) 2006-08-30
WO2005069122A2 (fr) 2005-07-28
FR2864390A1 (fr) 2005-06-24

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