WO2005112577A2 - Methods to fabricate mosfet devices using selective deposition processes - Google Patents
Methods to fabricate mosfet devices using selective deposition processes Download PDFInfo
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- WO2005112577A2 WO2005112577A2 PCT/US2005/016160 US2005016160W WO2005112577A2 WO 2005112577 A2 WO2005112577 A2 WO 2005112577A2 US 2005016160 W US2005016160 W US 2005016160W WO 2005112577 A2 WO2005112577 A2 WO 2005112577A2
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Definitions
- Embodiments of the invention generally relate to the field of semiconductor manufacturing processes and devices, more particular, to methods of depositing silicon-containing materials and films to form semiconductor devices.
- Selective epitaxy processes permits near complete dopant activation with in-situ doping, therefore removes or at least reduces the need of a post annealing process.
- Selective epitaxy processes and silicon etching processes may be used to accurately define junction depth.
- the ultra shallow source/drain junction inevitably results in increased series resistance.
- junction consumption during suicide formation further increases the series resistance.
- an elevated source/drain may be epitaxially and selectively grown on the junction.
- Selective epitaxial deposition provides growth of epilayers on silicon moats with no growth on dielectric areas.
- Selective epitaxy may be used to deposit silicon or silicon-germanium materials in semiconductor devices, such as within elevated source/drains, source/drain extensions, contact plugs, and base layer deposition of bipolar devices.
- a selective epitaxy process involves two competing chemical reactions, deposition reactions and etching reactions. The deposition and etching reactions occur simultaneously with relatively different reaction rates on single crystalline silicon surfaces and on dielectric surfaces.
- a selective process window results in the deposition of a material on exposed silicon surfaces and not on exposed dielectric surfaces, by adjusting the concentration of an etchant gas (e.g., HCl).
- an etchant gas e.g., HCl
- MOSFET metal oxide semiconductor field effect transistor
- One application is to deposit elevated source/drain (S/D) films by a selective epitaxy process.
- the epitaxial layer is undoped silicon.
- Another application is to fill recessed junction areas with epitaxial silicon-containing material, usually containing germanium, carbon or a dopant.
- a method for forming a silicon-based material on a substrate includes exposing a substrate to a first process gas containing dichlorosilane, a germanium source, a first etchant and a carrier gas to deposit a first silicon-containing layer thereon and exposing the substrate to a second process gas containing silane and a second etchant to deposit a second silicon-containing layer thereon.
- the first process gas is formed by combining dichlorosilane with a flow rate in a range from about 50 standard cubic centimeters per minute (seem) to about 200 seem, germane with a flow rate in a range from about 0.5 seem to about 5 seem, hydrogen chloride with a flow rate in a range from about 30 seem to about 500 seem and hydrogen with a flow rate in a range from about 10 standard liters per minute (slm) to about 30 slm.
- the method provides the second process gas is formed by combining silane with a flow rate in a range from about 50 seem to about 200 seem and hydrogen chloride with a flow rate in a range from about 30 seem to about 500 seem.
- the method further provides that the first silicon-containing layer and the second silicon-containing layer may be formed by a selective deposition process.
- the first and second silicon-containing layers have a boron concentration within a range from about 5*10 19 atoms/cm 3 to about 2*10 20 atoms/cm 3 .
- a method for forming a silicon-based material on a substrate in a process chamber which includes exposing a substrate to a process gas containing dichlorosilane, methylsilane, hydrogen chloride and hydrogen to deposit a silicon-containing layer thereon.
- the process gas is formed by combining dichlorosilane with a flow rate in a range from about 20 seem to about 400 seem, methylsilane with a flow rate in a range from about 0.3 seem to about 5 seem, hydrogen chloride with a flow rate in a range from about 30 seem to about 500 seem and the hydrogen with a flow rate in a range from about 10 slm to about 30 slm.
- a method for forming a silicon-based material on a substrate within a process chamber includes exposing a substrate to a process gas containing silane, methylsilane, hydrogen chloride, and hydrogen to deposit a silicon-containing layer thereon.
- the process gas is formed by combining silane with a flow rate in a range from about 20 seem to about 400 seem, methylsilane with a flow rate in a range from about 0.3 seem to about 5 seem, hydrogen chloride with a flow rate in a range from about 30 seem to about 500 seem and hydrogen with a flow rate in a range from about 10 slm to about 30 slm.
- the process gas is formed by combining silane with a flow rate in a range from about 50 seem to about 200 seem, germane with a flow rate in a range from about 0.5 seem to about 5 seem, methylsilane with a flow rate in a range from about 0.3 seem to about 5 seem, hydrogen chloride with a flow rate in a range from about 30 seem to about 500 seem and hydrogen with a flow rate in a range from about 10 slm to about 30 slm.
- the silicon-containing layer may be deposited with a composition containing silicon at a concentration of at least about 50 atomic percent (at%), carbon at a concentration of about 2 at% or less and germanium at a concentration in a range from about 15 at% to about 30 at%.
- a method for forming a silicon-based material on a substrate includes depositing a first silicon-containing layer on a substrate, depositing a second silicon-containing layer on the first silicon-containing layer and depositing a third silicon-containing layer on the second silicon-containing layer.
- the first silicon-containing layer contains about 25 at% or less of germanium
- the second silicon-containing layer contains about 25 at% or more of germanium
- the third silicon-containing layer contains about 5 at% or less of germanium.
- Figures 2A-2F show schematic illustrations of fabrication techniques for a source/drain extension device within a MOSFET.
- Source/drain layer 12 may be formed by exposing lower layer 10 to an ion implantation process. Generally, lower layer 10 is doped n-type while source/drain layer 12 is doped p-type. Silicon-containing layer 13 is selectively and epitaxially deposited on source/drain layer 12 or directly on lower layer 10 and silicon- containing layer 14 is selectively and epitaxially deposited on silicon-containing layer 13 by the various deposition processes described herein. Gate oxide layer 18 bridges segmented silicon-containing layer 13 and usually contains silicon dioxide, silicon oxynitride or hafnium oxide.
- gate oxide layer 18 Partially encompassing gate oxide layer 18 is spacer 16, which usually contains an isolation material such as a nitride/oxide stack (e.g., Si 3 N /Si0 2 /Si 3 N ).
- Gate layer 22 e.g., polysilicon
- protective layer 19 such as silicon dioxide, along the perpendicular sides, as in Figure 1A.
- gate layer 22 may have spacer 16 and off-set layers 20 (e.g., Si 3 N ) disposed on either side.
- Figure 1C depicts base layer 34 of a bipolar transistor deposited on n-type collector layer 32 disposed on lower layer 30.
- Base layer 34 contains silicon-containing material epitaxially deposited by the processes described herein.
- the device further includes isolation layer 33 (e.g., Si0 2 or Si 3 N 4 ), contact layer 36 (e.g., heavily doped poly-Si), off-set layer 38 (e.g., Si 3 N 4 ), and a second isolation layer 40 (e.g., Si0 2 or Si 3 N 4 ).
- isolation layer 33 e.g., Si0 2 or Si 3 N 4
- contact layer 36 e.g., heavily doped poly-Si
- off-set layer 38 e.g., Si 3 N 4
- second isolation layer 40 e.g., Si0 2 or Si 3 N 4
- a source/drain extension is formed within a MOSFET wherein the silicon-containing layers are epitaxially and selectively deposited on the surface of the substrate.
- Figure 2A depicts source/drain layer 132 formed by implanting ions into the surface of substrate 130. The segments of source/drain layer 132 are bridged by gate 136 formed on gate oxide layer 135 and subsequent deposition of off-set layer 134. A portion of the source/drain layer is etched and wet-cleaned, to produce recess 138, as in Figure 2B. A portion of gate 136 may also be etched, or optionally a hardmask may be deposited prior to etching to avoid removal of gate material.
- Figure 2C illustrates silicon-containing layer 140 (e.g., epitaxial or monocrystalline material) selectively deposited on source/drain layer 132 and silicon- containing layer 142 (e.g., polycrystalline or amorphous crystalline material) selectively deposited on gate 136 by deposition process described herein.
- silicon-containing layer 140 e.g., epitaxial or monocrystalline material
- silicon-containing layer 142 e.g., polycrystalline or amorphous crystalline material
- silicon-containing layers 140 and 142 are silicon-germanium containing layers with a germanium concentration in a range from about 1 atomic percent (at%) to about 50 at%, preferably about 25 at% or less. Multiple silicon-germanium containing layers containing varying amount of elements may be stacked to form silicon-containing layer 140 with a graded elemental concentration. For example, a first silicon-germanium layer may be deposited with a germanium concentration in a range from about 15 at% to about 25 at% and a second silicon-germanium layer may be deposited with a germanium concentration in a range from about 25 at% to about 35 at%.
- a first silicon-germanium layer may be deposited with a germanium concentration in a range from about 15 at% to about 25 at%
- a second silicon-germanium layer may be deposited with a germanium concentration in a range from about 25 at% to about 35 at%
- a third silicon-containing layer may be deposited with no germanium or with a germanium concentration up to about 5 at%.
- silicon-containing layer 140 Multiple layers containing silicon, silicon-germanium, silicon-carbon or silicon-germanium-carbon may be deposited in varying order to form graded elemental concentrations of silicon-containing layer 140.
- the silicon-containing layers are generally doped with a dopant (e.g., B, As or P) having a concentration in a range from about 1 ⁇ 10 19 atoms/cm 3 to about 2.5x10 21 atoms/cm 3 , preferably from about 5x10 19 atoms/cm 3 to about 2x10 20 atoms/cm 3 .
- Dopants added in individual layers of silicon-containing material form graded doped layers.
- silicon- containing layer 140 is formed by depositing a first silicon-germanium containing layer with a dopant concentration (e.g., boron) in a range from about 5*10 19 atoms/cm 3 to about 1 ⁇ 10 20 atoms/cm 3 and a second silicon-germanium containing layer with a dopant concentration (e.g., boron) in a range from about 1 *10 20 atoms/cm 3 to about 2*10 20 atoms/cm 3 .
- a dopant concentration e.g., boron
- Figure 2D shows spacer 144, generally a nitride spacer (e.g., Si 3 N 4 ) deposited on the off-set layer 134.
- Spacer 144 is usually deposited within a different process chamber than the process chamber used to deposit silicon-containing layer 140.
- the substrate may be exposed to ambient conditions, such as atmospheric air at room temperature containing water and oxygen.
- the substrate may be exposed to ambient conditions a second time prior to depositing silicon-containing layers 146 and 148.
- an epitaxial layer (not shown) containing no germanium or a minimal concentration of germanium (e.g., less than about 5 at%) is deposited on top of layer 140 prior to exposing the substrate to ambient conditions.
- the native oxides that are formed by the ambient conditions are removed easier from epitaxial layers containing minimal germanium concentrations than from an epitaxial layer formed with a germanium concentration greater than about 5 at%.
- FIG. 2E depicts elevated layer 148 epitaxially and selectively deposited from silicon-containing material, as described herein. Elevated layer 148 is deposited on layer 140 (e.g., doped SiGe) while polysilicon is deposited on the silicon-containing layer 142 to produce polysilicon layer 146. Depending on the elemental concentrations of silicon-containing layer 142 and polysilicon deposited thereto, the elemental concentrations of polysilicon layer 146 will inheritably contain these elemental concentrations, including graded concentrations when both layers are different.
- layer 140 e.g., doped SiGe
- elevated layer 148 is epitaxially deposited silicon containing little or no germanium or carbon. However, in another embodiment, elevated layer 148 contains a low concentration of germanium or carbon. For example, elevated layer 148 may have about 5 at% or less germanium. In another example, elevated layer 148 may have about 2 at% or less carbon. Elevated layer 148 may also be doped with a dopant, such as boron, arsenic or phosphorus. [0034] In the next step shown in Figure 2F, a metal layer 154 is deposited over the features and the device is exposed to an annealing process. The metal layer 154 may include cobalt, nickel or titanium, among other metals.
- polysilicon layer 146 and elevated layer 148 are converted to metal suicide layers, 150 and 152, respectively.
- metal suicide layers 150 and 152 respectively.
- cobalt may be deposited as metal layer 154 and is converted to metal suicide layers 150 and 152 containing cobalt suicide during an annealing process.
- the silicon-containing material may be heavily doped with the in-situ dopants. Therefore, annealing steps of the prior art may be omitted and the overall throughput is shorter. An increase of carrier mobility along the channel and subsequent drive current is achieved with the optional addition of germanium and/or carbon into the silicon-containing material layer. Selectively grown epilayers of the silicon-containing material above the gate oxide level can compensate junction consumption during the silicidation, which can relieve concerns of high series resistance of ultra shallow junctions. These two applications can be implemented together as well as solely for CMOS device fabrication.
- Silicon-containing materials formed by the deposition processes here may be to deposit silicon-containing films used by Bipolar (e.g., base, emitter, collector, emitter contact), BiCMOS (e.g., base, emitter, collector, emitter contact) and CMOS (e.g., channel, source/drain, source/drain extension, elevated source/drain, substrate, strained silicon, silicon on insulator and contact plug).
- Bipolar e.g., base, emitter, collector, emitter contact
- CMOS e.g., channel, source/drain, source/drain extension, elevated source/drain, substrate, strained silicon, silicon on insulator and contact plug.
- Other uses of the silicon-containing materials films may include gate, base contact, collector contact, emitter contact or elevated source/drain.
- a silicon-containing film is epitaxially grown as a silicon film.
- a substrate e.g., 300 mm OD
- a silicon precursor e.g., silane or dichlorosilane
- a carrier gas e.g., H 2 and/or N 2
- an etchant e.g., HCl
- the flow rate of the silicon precursor is in a range from about 5 standard cubic centimeters per minute (sccm) to about 500 seem, preferably from about 50 seem to about 200 seem.
- the flow rate of the carrier gas is in a range from about 10 standard liters per minute (slm) to about 30 slm.
- the flow rate of the etchant is in a range from about 5 sccm to about 1 ,000 sccm, preferably from about 30 sccm to about 500 sccm.
- the process chamber is maintained with a pressure in a range from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 50 Torr.
- the substrate is heated at a temperature in a range from about 500°C to about 1 ,000°C, preferably from about 600°C to about 900°C, more preferably from about 650°C to about 750°C, for example about 720°C.
- the mixture of reagents is thermally driven to react and epitaxially deposit crystalline silicon.
- the etchant removes any deposited amorphous silicon or polycrystalline silicon from dielectric features on the surface of the substrate.
- the process is conducted to form the deposited silicon-containing film with a thickness in a range from about 10 A to about 3,000 A, for example, from about 40 A to about 100 A.
- the deposited silicon-containing film has a thickness in a range from about 200 A to about 600 A.
- the silicon-containing film has a thickness greater than 500 A, such as about 1 ,000 A.
- Etchants are used to provide select areas of a feature on a substrate surface to be free of deposited silicon-containing materials.
- the etchant removes amorphous silicon or polysilicon growth that forms on the features at a faster rate than the etchant removes crystalline silicon growth from the crystalline surfaces, thus achieving selective epitaxial growth or deposition.
- Etchants that are useful during deposition processes as described herein include HCl, HF, HBr, Si2CI 6 , SiCI , CI 2 SiH 2 , CCU, Cl 2 , derivatives thereof or combinations thereof.
- silicon precursors besides silane and dichlorosilane, which are useful while depositing silicon-containing materials include higher silanes, halogenated silanes and organosilanes.
- Higher silanes include the compounds with the empirical formula Si x H(2 X+2 ), such as disilane (Si 2 He), trisilane (Si 3 H 8 ), and tetrasilane (Si 4 H ⁇ o), as well as others.
- Carrier gases are used throughout the processes and include hydrogen (H 2 ), argon (Ar), nitrogen (N 2 ), helium (He), forming gas (N 2 /H ) or combinations thereof.
- hydrogen is used as a carrier gas.
- nitrogen is used as a carrier gas.
- a carrier gas during an epitaxial deposition process is conducted with neither hydrogen nor atomic hydrogen.
- an inert gas is used as a carrier gas, such as nitrogen, argon, helium or combinations thereof.
- Carrier gases may be combined in various ratios during some embodiments of the process.
- a carrier gas may include nitrogen or argon to maintain available sites on the silicon-containing material film.
- the presence of hydrogen on the silicon-containing material surface limits the number of available sites (i.e., passivates) for silicon or silicon-germanium to grow when an abundance of hydrogen is used as a carrier gas. Consequently, a passivated surface limits the growth rate at a given temperature, particularly at lower temperatures (e.g., ⁇ 650°C). Therefore, a carrier gas of nitrogen and/or argon may be used during a process at lower temperature and reduce the thermal budget without sacrificing growth rate.
- a silicon-containing film is epitaxially grown as a silicon-germanium film.
- a substrate e.g., 300 mm OD
- a silicon precursor e.g., silane or dichlorosilane
- a carrier gas e.g., H 2 and/or N2
- a germanium source e.g., GeH 4
- an etchant e.g., HCl
- the flow rate of the silicon precursor is in a range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm.
- the flow rate of the carrier gas is in a range from about 10 slm to about 30 slm.
- the flow rate of the germanium source is in a range from about 0.1 sccm to about 10 sccm, preferably from about 0.5 sccm to about 5 sccm.
- the flow rate of the etchant is in a range from about 5 sccm to about 1 ,000 sccm, preferably from about 30 sccm to about 500 sccm.
- the process chamber is maintained with a pressure in a range from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr.
- germanium sources or precursors, besides germane, that are useful while depositing silicon-containing materials include higher germanes and organogermanes.
- Higher germanes include the compounds with the empirical formula Ge x H(2 X +2), such as digermane (Ge 2 H 6 ), trigermane (Ge 3 H 8 ) and tetragermane (Ge H ⁇ o), as well as others.
- R methyl, ethyl, propyl or butyl, such as methylgermane ((CH 3 )GeH 3 ), dimethylgermane ((CH 3 ) 2 GeH 2 ), ethylgermane ((CH 3 CH 2 )GeH 3 ), methyldigermane ((
- Germanes and organogermane compounds have been found to be an advantageous germanium sources and carbon sources during embodiments of the present invention to incorporate germanium and carbon in to the deposited silicon-containing materials, namely silicon-germanium and silicon-germanium-carbon materials.
- Germanium sources are often mixed with a carrier gas (e.g., H 2 ) to dilute and therefore better control the germanium doses.
- a germanium source with a flow rate in a range from about 0.5 sccm to about 5 sccm is equivalent to a flow of about 1% germanium source in a carrier gas with a flow rate in a range from about 50 sccm to about 500 sccm.
- the flow rate of germanium source ignores the flow rate of the carrier gas.
- the substrate is heated to a temperature in a range from about 500°C to about 1 ,000°C, preferably from about 700°C to about 900°C.
- the mixture of reagents is thermally driven to react and epitaxially deposit doped silicon films.
- the etchant removes any deposited amorphous silicon or polycrystalline silicon from dielectric features upon the surface of the substrate.
- the process is conducted to form the deposited, doped silicon-containing film with a thickness in a range from about 10 A to about 3,000 A, for example, from about 40 A to about 100 A. In another example, the deposited silicon-containing film has a thickness in a range from about 200 A to about 600 A.
- the silicon-containing film has a thickness greater than 500 A, such as about 1 ,000 A.
- the dopant concentration may be graded within the silicon film, preferably graded with a higher dopant concentration in the lower portion of the silicon film than in the upper portion of the silicon film.
- Dopants provide the deposited silicon-containing materials with various conductive characteristics, such as directional electron flow in a controlled and desired pathway required by the electronic device. Films of the silicon-containing materials are doped with particular dopants to achieve the desired conductive characteristic.
- the silicon-containing material is doped p-type, such as by using diborane to add boron at a concentration in a range from about 10 15 atoms/cm 3 to about 10 21 atoms/cm 3 .
- the p-type dopant has a concentration of at least 5x10 19 atoms/cm 3 .
- the p-type dopant is in a range from about 1 ⁇ 10 20 atoms/cm 3 to about 2.5x10 21 atoms/cm 3 .
- the silicon-containing material is doped n-type, such as with phosphorus and/or arsenic to a concentration in a range from about 10 15 atoms/cm 3 to about 10 21 atoms/cm 3 .
- Alkylboranes may include trimethylborane ((CH 3 ) 3 B), dimethylborane ((CFfefeBH), triethylborane ((CH 3 CH 2 ) 3 B), diethylborane ((CH 3 CH 2 ) 2 BH), derivatives thereof, complexes thereof or combinations thereof.
- Alkylphosphines include trimethylphosphine ((CH 3 ) 3 P), dimethylphosphine ((CH 3 ) 2 PH), triethylphosphine ((CH 3 CH 2 )3P) and diethylphosphine ((CH 3 CH 2 ) 2 PH), derivatives thereof, complexes thereof or combinations thereof.
- Dopants are often mixed with a carrier gas (e.g., H 2 ) to dilute and therefore better control the doping doses.
- a flow rate of dopant in a range from about 0.2 sccm to about 2 sccm is equivalent to a flow of 1% dopant in a carrier gas with a flow rate in a range from about 20 sccm to about 200 sccm.
- the flow rate of dopant precursor ignores the flow rate of the carrier gas.
- a silicon-containing film is epitaxially grown to produce a doped silicon-germanium film.
- a substrate e.g., 300 mm OD
- a silicon precursor e.g., silane or dichlorosilane
- a carrier gas e.g., H 2 and/or N 2
- a germanium source e.g., GeH 4
- a dopant e.g., B 2 H 6
- an etchant e.g., HCl
- the flow rate of the silicon precursor is in a range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm.
- the flow rate of the carrier gas is in a range from about 10 slm to about 30 slm.
- the flow rate of the germanium source is in a range from about 0.1 sccm to about 10 sccm, preferably from about 0.5 sccm to about 5 sccm.
- the flow rate of the dopant precursor is in a range from about 0.01 sccm to about 10 sccm, preferably from about 0.2 sccm to about 3 sccm.
- the flow rate of the etchant is in a range from about 5 sccm to about 1 ,000 sccm, preferably from about 30 sccm to about 500 sccm.
- the process chamber is maintained at a pressure in a range from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr.
- the substrate is heated to a temperature in a range from about 500°C to about 1 ,000°C, preferably from about 700°C to about 900°C.
- the reagent mixture is thermally driven to react and epitaxially deposit a silicon- containing material, namely a silicon germanium film.
- the etchant removes any deposited amorphous silicon-germanium from features upon the surface of the substrate.
- the process is conducted to form the doped silicon-germanium film with a thickness in a range from about 10 A to about 3,000 A, for example, from about 40 A to about 100 A.
- the deposited silicon-containing film has a thickness in a range from about 200 A to about 600 A.
- the silicon-containing film has a thickness greater than 500 A, such as about 1 ,000 A.
- a silicon-containing film is epitaxially grown as a silicon-carbon film.
- a substrate e.g., 300 mm OD
- a silicon precursor e.g., silane or dichlorosilane
- a carrier gas e.g., H 2 and/or N 2
- a carbon source e.g., CHsSiHs
- an etchant e.g., HCl
- the flow rate of the silicon precursor is in a range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm.
- the process is conducted to form the deposited silicon-carbon film with a thickness in a range from about 10 A to about 3,000 A, for example, from about 40 A to about 100 A.
- the deposited silicon-containing film has a thickness in a range from about 200 A to about 600 A.
- the silicon-containing film has a thickness greater than 500 A, such as about 1 ,000 A.
- the carbon concentration may be graded within the silicon-carbon film, preferably graded with a higher carbon concentration in the lower portion of the silicon-carbon film than in the upper portion of the silicon-carbon film.
- the carbon concentration of the silicon-carbon film is in a range from about 200 ppm to about 5 at%, preferably from about 1 at% to about 3 at%, for example 1.5 at%.
- a silicon-containing film is epitaxially grown to produce a doped silicon-carbon film.
- a substrate e.g., 300 mm OD
- a silicon precursor e.g., silane or dichlorosilane
- a carrier gas e.g., H 2 and/or N 2
- a carbon source e.g., CH 3 SiH 3
- a dopant e.g., B 2 H 6
- an etchant e.g., HCl
- the flow rate of the silicon precursor is in a range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm.
- the flow rate of the carrier gas is in a range from about 10 slm to about 30 slm.
- the flow rate of the carbon source is in a range from about 0.1 sccm to about 15 sccm, preferably from about 0.3 sccm to about 5 sccm.
- the flow rate of the dopant precursor is in a range from about 0.01 sccm to about 10 sccm, preferably from about 0.2 sccm to about 3 sccm.
- the flow rate of the etchant is in a range from about 5 sccm to about 1 ,000 sccm, preferably from about 30 sccm to about 500 sccm.
- the process chamber is maintained at a pressure in a range from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr.
- the substrate is heated to a temperature in a range from about 500°C to about 1 ,000°C, preferably from about 700°C to about 900°C.
- the reagent mixture is thermally driven to react and epitaxially deposit a silicon- containing material, namely a doped silicon carbon film.
- the etchant removes any deposited amorphous silicon-carbon from features upon the surface of the substrate.
- a silicon precursor e.g., silane or dichlorosilane
- a carrier gas e.g., H 2 and/or N 2
- a germanium source e.g., GeH
- a carbon source e.g., CHsSiHs
- an etchant e.g., HCl
- the flow rate of the silicon precursor is in a range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm.
- the flow rate of the carrier gas is from about 10 slm to about 30 slm.
- a silicon-containing material film is epitaxially grown as a doped silicon-germanium-carbon film.
- a substrate e.g., 300 mm OD
- a silicon precursor e.g., silane or dichlorosilane
- a carrier gas e.g., H 2 and/or N 2
- a germanium source e.g., GeH 4
- a carbon source e.g., CHsSiHs
- a dopant e.g., B 2 He
- an etchant e.g., HCl
- the flow rate of the silicon precursor is in a range from about 5 sccm to about 500 sccm, preferably from about 50 sccm to about 200 sccm.
- the flow rate of the carrier gas is from about 10 slm to about 30 slm.
- the flow rate of the germanium source is from about 0.1 sccm to about 10 sccm, preferably from about 0.5 sccm to about 5 sccm.
- the flow rate of the carbon source is from about 0.1 sccm to about 50 sccm, preferably from about 0.3 sccm to about 5 sccm.
- the flow rate of the dopant precursor is from about 0.01 sccm to about 10 sccm, preferably from about 0.2 sccm to about 3 sccm.
- the flow rate of the etchant is from about 5 sccm to about 1 ,000 sccm, preferably from about 30 sccm to about 500 sccm.
- the process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably from about 1 Torr to about 5 Torr, for example, about 3 Torr.
- the substrate is heated to a temperature in a range from about 500°C to about 1 ,000°C, preferably from about 500°C to about 700°C.
- the reagent mixture is thermally driven to react and epitaxially deposit a silicon-containing material, namely a doped silicon germanium carbon film.
- the etchant removes any deposited amorphous or polycrystalline silicon-germanium-carbon materials from dielectric features upon the surface of the substrate.
- a second silicon-containing film is epitaxially grown by using dichlorosilane, subsequently to depositing any of the silicon- containing materials aforementioned in the above disclosure.
- a substrate e.g., 300 mm OD
- a silicon precursor e.g., CI 2 SiH 2
- a carrier gas e.g., H 2 and/or N 2
- a germanium source e.g., GeH 4
- an etchant e.g., HCl
- a silicon-containing laminate film may be deposited in sequential layers of silicon-containing material by altering the silicon precursor between silane and dichlorosilane.
- a laminate film of about 2,000 A is formed by depositing four silicon-containing layers (each of about 500 A), such that the first and third layers are deposited using dichlorosilane and the second and fourth layers are deposited using silane.
- the first and third layers are deposited using silane and the second and fourth layers are deposited using dichlorosilane.
- the thickness of each layer is independent from each other; therefore, a laminate film may have various thicknesses of the silicon-containing layers.
- Surfaces or substrates may include wafers, films, layers and materials with dielectric, conductive and barrier properties and include polysilicon, silicon on insulators (SOI), strained and unstrained lattices. Pretreatment processes of surfaces may include a polishing process, an etching process, a reduction process, an oxidation process, a hydroxylation process, an annealing process and a baking process.
- wafers are dipped into a 1 % HF solution, dried and heated within a hydrogen atmosphere at 800°C.
- silicon-containing materials include a germanium concentration within a range from about 0 at% to about 95 at%.
- MOSFET devices formed by processes described herein may contain a PMOS component or a NMOS component.
- the PMOS component, with a p-type channel, has holes that are responsible for channel conduction, while the NMOS component, with a n-type channel, has electrons that are responsible channel conduction. Therefore, for example, a silicon-containing material such as silicon- germanium may be deposited in a recessed area to form a PMOS component. In another example, a silicon-containing film such as silicon-carbon may be deposited in a recessed area to form a NMOS component. Silicon-germanium is used for PMOS application for several reasons. A silicon-germanium material incorporates more boron than silicon alone, thus the junction resistivity may be lowered. Also, the silicon-germanium/silicide layer interface at the substrate surface has a lower Schottky barrier than the silicon/silicide interface.
- the preferred process of the present invention is to use thermal CVD to epitaxially grow or deposit the silicon- containing material, whereas the silicon-containing material includes silicon (Si), silicon-germanium (SiGe), silicon-carbon (SiC), silicon-germanium-carbon (SiGeC), doped variants thereof or combinations thereof.
- Dichlorosilane (100 sccm) and germane (1 % GeH 4 in H 2 , 280 sccm) were added to the chamber at 3 Torr and 725°C.
- hydrogen chloride (190 sccm) and diborane (1 % in H 2 , 150 sccm) were delivered to the chamber.
- the substrate was maintained at 725°C.
- Deposition was conducted for about 5 minutes to form a 500 A silicon-germanium film with a germanium concentration of about 20 at% and the boron concentration of about 1.0 ⁇ 10 20 cm "3 .
- the substrate was removed from the process chamber and exposed to the ambient air.
- the substrate was loaded into a second deposition chamber (Epi Centura ® chamber) and heated to 800°C.
- the substrate was exposed to a process gas containing silane (100 sccm) and hydrogen chloride (250 sccm) for about 10 minutes to selectively deposit a silicon film on the silicon-germanium
- Dichlorosilane (100 sccm) and germane (1% GeH in H 2 , 190 sccm) were added to the chamber at 3 Torr and 725°C.
- hydrogen chloride (160 sccm) and diborane (1% in H 2 , 150 sccm) were delivered to the chamber.
- the substrate was maintained at 725°C.
- Deposition was conducted for 2 minutes to form a 100 A silicon-germanium film with a germanium concentration of 15 at% and the boron concentration of about 5.0x10 19 cm "3 .
- a second silicon- germanium film was deposited to the first silicon-germanium film to form a graded- silicon-germanium film.
- Example 3 SiC/Si stack: A substrate, Si ⁇ 100>, (e.g., 300 mm OD) was employed to investigate selective, monocrystalline film growth by CVD. A dielectric feature existed on the surface of the wafer. The wafer was prepared by subjecting to a 1 % HF dip for 45 seconds. The wafer was loaded into the deposition chamber (Epi Centura ® chamber) and baked in a hydrogen atmosphere at 800°C for 60 seconds to remove native oxide. A flow of carrier gas, hydrogen, was directed towards the substrate and the source compounds were added to the carrier flow.
- Ether ® chamber the deposition chamber
- Dichlorosilane (100 sccm) and methylsilane (1 % CH 3 SiH 3 in H 2 , 100 sccm) were added to the chamber at 3 Torr and 725°C.
- hydrogen chloride (160 sccm) and diborane (1 % in H 2 , 150 sccm) were delivered to the chamber.
- the substrate was maintained at 725°C.
- Deposition was conducted for about 5 minutes to form a 500 A silicon- carbon film with a carbon concentration of about 1.25 at% and the boron concentration of about 1.0 ⁇ 10 20 cm “3 .
- the substrate was removed from the process chamber and exposed to the ambient air.
- the substrate was removed from the process chamber and exposed to the ambient air.
- the substrate was loaded into a second deposition chamber (Epi Centura ® chamber) and heated to 800°C.
- the substrate was exposed to a process gas containing silane (100 sccm) and hydrogen chloride (250 sccm) for about 10 minutes to selectively deposit a silicon film on the silicon-germanium-carbon film.
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| WO2005017963A2 (en) * | 2003-08-04 | 2005-02-24 | Asm America, Inc. | Surface preparation prior to deposition on germanium |
| US7132338B2 (en) | 2003-10-10 | 2006-11-07 | Applied Materials, Inc. | Methods to fabricate MOSFET devices using selective deposition process |
| US7166528B2 (en) * | 2003-10-10 | 2007-01-23 | Applied Materials, Inc. | Methods of selective deposition of heavily doped epitaxial SiGe |
| US20100120235A1 (en) * | 2008-11-13 | 2010-05-13 | Applied Materials, Inc. | Methods for forming silicon germanium layers |
| US8501594B2 (en) * | 2003-10-10 | 2013-08-06 | Applied Materials, Inc. | Methods for forming silicon germanium layers |
| US7354815B2 (en) * | 2003-11-18 | 2008-04-08 | Silicon Genesis Corporation | Method for fabricating semiconductor devices using strained silicon bearing material |
| JP3901696B2 (en) * | 2004-02-19 | 2007-04-04 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
| JP4982355B2 (en) | 2004-02-27 | 2012-07-25 | エーエスエム アメリカ インコーポレイテッド | Method for forming germanium film |
| JP4874527B2 (en) * | 2004-04-01 | 2012-02-15 | トヨタ自動車株式会社 | Silicon carbide semiconductor substrate and method for manufacturing the same |
| KR20070006852A (en) * | 2004-04-23 | 2007-01-11 | 에이에스엠 아메리카, 인코포레이티드 | In-situ doped epitaxial film |
| US20050275018A1 (en) * | 2004-06-10 | 2005-12-15 | Suresh Venkatesan | Semiconductor device with multiple semiconductor layers |
| US7172933B2 (en) * | 2004-06-10 | 2007-02-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Recessed polysilicon gate structure for a strained silicon MOSFET device |
| TWI463526B (en) * | 2004-06-24 | 2014-12-01 | 萬國商業機器公司 | Method for improving stress-induced CMOS components and components prepared by the method |
| DE102004031743B4 (en) * | 2004-06-30 | 2006-10-05 | Advanced Micro Devices, Inc., Sunnyvale | A method of making an epitaxial layer for elevated drain and source regions by removing surface defects of the initial crystal surface |
| US7629270B2 (en) * | 2004-08-27 | 2009-12-08 | Asm America, Inc. | Remote plasma activated nitridation |
| US7132355B2 (en) * | 2004-09-01 | 2006-11-07 | Micron Technology, Inc. | Method of forming a layer comprising epitaxial silicon and a field effect transistor |
| US7531395B2 (en) * | 2004-09-01 | 2009-05-12 | Micron Technology, Inc. | Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors |
| US7144779B2 (en) * | 2004-09-01 | 2006-12-05 | Micron Technology, Inc. | Method of forming epitaxial silicon-comprising material |
| US8673706B2 (en) | 2004-09-01 | 2014-03-18 | Micron Technology, Inc. | Methods of forming layers comprising epitaxial silicon |
| US7253084B2 (en) | 2004-09-03 | 2007-08-07 | Asm America, Inc. | Deposition from liquid sources |
| US7179696B2 (en) * | 2004-09-17 | 2007-02-20 | Texas Instruments Incorporated | Phosphorus activated NMOS using SiC process |
| US7966969B2 (en) * | 2004-09-22 | 2011-06-28 | Asm International N.V. | Deposition of TiN films in a batch reactor |
| US7247535B2 (en) * | 2004-09-30 | 2007-07-24 | Texas Instruments Incorporated | Source/drain extensions having highly activated and extremely abrupt junctions |
| US20060105559A1 (en) * | 2004-11-15 | 2006-05-18 | International Business Machines Corporation | Ultrathin buried insulators in Si or Si-containing material |
| US7312128B2 (en) | 2004-12-01 | 2007-12-25 | Applied Materials, Inc. | Selective epitaxy process with alternating gas supply |
| US7479431B2 (en) | 2004-12-17 | 2009-01-20 | Intel Corporation | Strained NMOS transistor featuring deep carbon doped regions and raised donor doped source and drain |
| US7704896B2 (en) * | 2005-01-21 | 2010-04-27 | Asm International, N.V. | Atomic layer deposition of thin films on germanium |
| US7235492B2 (en) * | 2005-01-31 | 2007-06-26 | Applied Materials, Inc. | Low temperature etchant for treatment of silicon-containing surfaces |
| US7816236B2 (en) * | 2005-02-04 | 2010-10-19 | Asm America Inc. | Selective deposition of silicon-containing films |
| US7629267B2 (en) * | 2005-03-07 | 2009-12-08 | Asm International N.V. | High stress nitride film and method for formation thereof |
| WO2007035660A1 (en) * | 2005-09-20 | 2007-03-29 | Applied Materials, Inc. | Method to form a device on a soi substrate |
| KR100663010B1 (en) * | 2005-09-23 | 2006-12-28 | 동부일렉트로닉스 주식회사 | MOS transistor and its manufacturing method |
| US7439558B2 (en) * | 2005-11-04 | 2008-10-21 | Atmel Corporation | Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement |
| US20090087967A1 (en) * | 2005-11-14 | 2009-04-02 | Todd Michael A | Precursors and processes for low temperature selective epitaxial growth |
| US7939413B2 (en) * | 2005-12-08 | 2011-05-10 | Samsung Electronics Co., Ltd. | Embedded stressor structure and process |
| US7718500B2 (en) * | 2005-12-16 | 2010-05-18 | Chartered Semiconductor Manufacturing, Ltd | Formation of raised source/drain structures in NFET with embedded SiGe in PFET |
| WO2007075369A1 (en) * | 2005-12-16 | 2007-07-05 | Asm International N.V. | Low temperature doped silicon layer formation |
| JP2009521801A (en) * | 2005-12-22 | 2009-06-04 | エーエスエム アメリカ インコーポレイテッド | Epitaxial deposition of doped semiconductor materials. |
| US8900980B2 (en) * | 2006-01-20 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Defect-free SiGe source/drain formation by epitaxy-free process |
| US7709391B2 (en) | 2006-01-20 | 2010-05-04 | Applied Materials, Inc. | Methods for in-situ generation of reactive etch and growth specie in film formation processes |
| US7608515B2 (en) * | 2006-02-14 | 2009-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diffusion layer for stressed semiconductor devices |
| DE102006009225B4 (en) * | 2006-02-28 | 2009-07-16 | Advanced Micro Devices, Inc., Sunnyvale | Preparation of silicide surfaces for silicon / carbon source / drain regions |
| US7901968B2 (en) * | 2006-03-23 | 2011-03-08 | Asm America, Inc. | Heteroepitaxial deposition over an oxidized surface |
| US7410875B2 (en) * | 2006-04-06 | 2008-08-12 | United Microelectronics Corp. | Semiconductor structure and fabrication thereof |
| WO2007117583A2 (en) * | 2006-04-07 | 2007-10-18 | Applied Materials Inc. | Cluster tool for epitaxial film formation |
| CN101460654A (en) * | 2006-05-01 | 2009-06-17 | 应用材料股份有限公司 | Method for forming ultra-shallow junction region by using carbon-containing silicon film |
| US8278176B2 (en) | 2006-06-07 | 2012-10-02 | Asm America, Inc. | Selective epitaxial formation of semiconductor films |
| US7691757B2 (en) | 2006-06-22 | 2010-04-06 | Asm International N.V. | Deposition of complex nitride films |
| US7648853B2 (en) | 2006-07-11 | 2010-01-19 | Asm America, Inc. | Dual channel heterostructure |
| US7494884B2 (en) * | 2006-10-05 | 2009-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | SiGe selective growth without a hard mask |
| US7741200B2 (en) * | 2006-12-01 | 2010-06-22 | Applied Materials, Inc. | Formation and treatment of epitaxial layer containing silicon and carbon |
| US20080132039A1 (en) * | 2006-12-01 | 2008-06-05 | Yonah Cho | Formation and treatment of epitaxial layer containing silicon and carbon |
| US7837790B2 (en) * | 2006-12-01 | 2010-11-23 | Applied Materials, Inc. | Formation and treatment of epitaxial layer containing silicon and carbon |
| US7897495B2 (en) * | 2006-12-12 | 2011-03-01 | Applied Materials, Inc. | Formation of epitaxial layer containing silicon and carbon |
| US8394196B2 (en) * | 2006-12-12 | 2013-03-12 | Applied Materials, Inc. | Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon |
| US7960236B2 (en) * | 2006-12-12 | 2011-06-14 | Applied Materials, Inc. | Phosphorus containing Si epitaxial layers in N-type source/drain junctions |
| US20080138955A1 (en) * | 2006-12-12 | 2008-06-12 | Zhiyuan Ye | Formation of epitaxial layer containing silicon |
| JP5100137B2 (en) * | 2007-01-26 | 2012-12-19 | 株式会社東芝 | Semiconductor device manufacturing method and semiconductor device |
| US9064960B2 (en) * | 2007-01-31 | 2015-06-23 | Applied Materials, Inc. | Selective epitaxy process control |
| KR100825809B1 (en) * | 2007-02-27 | 2008-04-29 | 삼성전자주식회사 | Structure of semiconductor device having strain layer and manufacturing method thereof |
| US20080233722A1 (en) * | 2007-03-23 | 2008-09-25 | United Microelectronics Corp. | Method of forming selective area compound semiconductor epitaxial layer |
| JP4896789B2 (en) * | 2007-03-29 | 2012-03-14 | 株式会社東芝 | Manufacturing method of semiconductor device |
| US20080274626A1 (en) * | 2007-05-04 | 2008-11-06 | Frederique Glowacki | Method for depositing a high quality silicon dielectric film on a germanium substrate with high quality interface |
| US7629256B2 (en) * | 2007-05-14 | 2009-12-08 | Asm International N.V. | In situ silicon and titanium nitride deposition |
| DE102007030053B4 (en) * | 2007-06-29 | 2011-07-21 | Advanced Micro Devices, Inc., Calif. | Reduce pn junction capacitance in a transistor by lowering drain and source regions |
| JP4664950B2 (en) | 2007-08-20 | 2011-04-06 | 株式会社東芝 | Semiconductor device |
| US7759199B2 (en) * | 2007-09-19 | 2010-07-20 | Asm America, Inc. | Stressor for engineered strain on channel |
| US7776698B2 (en) | 2007-10-05 | 2010-08-17 | Applied Materials, Inc. | Selective formation of silicon carbon epitaxial layer |
| US7939447B2 (en) * | 2007-10-26 | 2011-05-10 | Asm America, Inc. | Inhibitors for selective deposition of silicon containing films |
| US7772097B2 (en) * | 2007-11-05 | 2010-08-10 | Asm America, Inc. | Methods of selectively depositing silicon-containing films |
| US20090152590A1 (en) * | 2007-12-13 | 2009-06-18 | International Business Machines Corporation | Method and structure for semiconductor devices with silicon-germanium deposits |
| US7655543B2 (en) * | 2007-12-21 | 2010-02-02 | Asm America, Inc. | Separate injection of reactive species in selective formation of films |
| JP5168287B2 (en) * | 2008-01-25 | 2013-03-21 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
| KR101409374B1 (en) | 2008-04-10 | 2014-06-19 | 삼성전자 주식회사 | Method for manufacturing semiconductor integrated circuit device and semiconductor integrated circuit device manufactured thereby |
| US8293592B2 (en) * | 2008-04-16 | 2012-10-23 | Hitachi Kokusai Electric Inc. | Method of manufacturing semiconductor device and substrate processing apparatus |
| US20100001317A1 (en) * | 2008-07-03 | 2010-01-07 | Yi-Wei Chen | Cmos transistor and the method for manufacturing the same |
| US8343583B2 (en) | 2008-07-10 | 2013-01-01 | Asm International N.V. | Method for vaporizing non-gaseous precursor in a fluidized bed |
| KR101561059B1 (en) * | 2008-11-20 | 2015-10-16 | 삼성전자주식회사 | Semiconductor device and method of forming the same |
| US8012876B2 (en) * | 2008-12-02 | 2011-09-06 | Asm International N.V. | Delivery of vapor precursor from solid source |
| US7833906B2 (en) | 2008-12-11 | 2010-11-16 | Asm International N.V. | Titanium silicon nitride deposition |
| JP5697849B2 (en) * | 2009-01-28 | 2015-04-08 | 株式会社日立国際電気 | Semiconductor device manufacturing method and substrate processing apparatus |
| DE102009006884B4 (en) * | 2009-01-30 | 2011-06-30 | Advanced Micro Devices, Inc., Calif. | A method of fabricating a transistor device having in situ generated drain and source regions with a strain-inducing alloy and a gradually varying dopant profile and corresponding transistor device |
| US8486191B2 (en) * | 2009-04-07 | 2013-07-16 | Asm America, Inc. | Substrate reactor with adjustable injectors for mixing gases within reaction chamber |
| US7994015B2 (en) | 2009-04-21 | 2011-08-09 | Applied Materials, Inc. | NMOS transistor devices and methods for fabricating same |
| JP5287621B2 (en) * | 2009-09-10 | 2013-09-11 | 富士通セミコンダクター株式会社 | Semiconductor device |
| US8367528B2 (en) * | 2009-11-17 | 2013-02-05 | Asm America, Inc. | Cyclical epitaxial deposition and etch |
| TWI416727B (en) * | 2009-12-04 | 2013-11-21 | 華亞科技股份有限公司 | P-type metal oxide layer semiconductor field effect transistor and manufacturing method thereof |
| US8999798B2 (en) * | 2009-12-17 | 2015-04-07 | Applied Materials, Inc. | Methods for forming NMOS EPI layers |
| US8598003B2 (en) * | 2009-12-21 | 2013-12-03 | Intel Corporation | Semiconductor device having doped epitaxial region and its methods of fabrication |
| US9117905B2 (en) * | 2009-12-22 | 2015-08-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for incorporating impurity element in EPI silicon process |
| US8012859B1 (en) | 2010-03-31 | 2011-09-06 | Tokyo Electron Limited | Atomic layer deposition of silicon and silicon-containing films |
| JP5767697B2 (en) * | 2010-05-12 | 2015-08-19 | ボレアリス アーゲーBorealis Ag | Polypropylene for special capacitors containing a specific amount of calcium stearate |
| CN102468326B (en) * | 2010-10-29 | 2015-01-07 | 中国科学院微电子研究所 | Contact electrode manufacturing method and semiconductor device |
| US8993418B2 (en) * | 2010-11-19 | 2015-03-31 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Shallow heavily doped semiconductor layer by cyclic selective epitaxial deposition process |
| EP2461352B1 (en) * | 2010-12-06 | 2013-07-10 | Imec | Method of manufacturing low resistivity contacts on n-type germanium |
| US8466502B2 (en) | 2011-03-24 | 2013-06-18 | United Microelectronics Corp. | Metal-gate CMOS device |
| US8445363B2 (en) | 2011-04-21 | 2013-05-21 | United Microelectronics Corp. | Method of fabricating an epitaxial layer |
| US8324059B2 (en) | 2011-04-25 | 2012-12-04 | United Microelectronics Corp. | Method of fabricating a semiconductor structure |
| US8426284B2 (en) | 2011-05-11 | 2013-04-23 | United Microelectronics Corp. | Manufacturing method for semiconductor structure |
| US8481391B2 (en) | 2011-05-18 | 2013-07-09 | United Microelectronics Corp. | Process for manufacturing stress-providing structure and semiconductor device with such stress-providing structure |
| US9218962B2 (en) * | 2011-05-19 | 2015-12-22 | Globalfoundries Inc. | Low temperature epitaxy of a semiconductor alloy including silicon and germanium employing a high order silane precursor |
| US8809170B2 (en) | 2011-05-19 | 2014-08-19 | Asm America Inc. | High throughput cyclical epitaxial deposition and etch process |
| US8431460B2 (en) | 2011-05-27 | 2013-04-30 | United Microelectronics Corp. | Method for fabricating semiconductor device |
| US8962400B2 (en) * | 2011-07-07 | 2015-02-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | In-situ doping of arsenic for source and drain epitaxy |
| US8716750B2 (en) | 2011-07-25 | 2014-05-06 | United Microelectronics Corp. | Semiconductor device having epitaxial structures |
| US8575043B2 (en) | 2011-07-26 | 2013-11-05 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
| US8647941B2 (en) | 2011-08-17 | 2014-02-11 | United Microelectronics Corp. | Method of forming semiconductor device |
| US8674433B2 (en) | 2011-08-24 | 2014-03-18 | United Microelectronics Corp. | Semiconductor process |
| US8476169B2 (en) | 2011-10-17 | 2013-07-02 | United Microelectronics Corp. | Method of making strained silicon channel semiconductor structure |
| US8691659B2 (en) | 2011-10-26 | 2014-04-08 | United Microelectronics Corp. | Method for forming void-free dielectric layer |
| US8754448B2 (en) | 2011-11-01 | 2014-06-17 | United Microelectronics Corp. | Semiconductor device having epitaxial layer |
| US9660049B2 (en) | 2011-11-03 | 2017-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor transistor device with dopant profile |
| US8647953B2 (en) | 2011-11-17 | 2014-02-11 | United Microelectronics Corp. | Method for fabricating first and second epitaxial cap layers |
| US8709930B2 (en) | 2011-11-25 | 2014-04-29 | United Microelectronics Corp. | Semiconductor process |
| CN103177962B (en) * | 2011-12-20 | 2015-12-09 | 中芯国际集成电路制造(上海)有限公司 | The formation method of transistor |
| CN103187299B (en) * | 2011-12-31 | 2015-08-05 | 中芯国际集成电路制造(上海)有限公司 | The formation method of transistor |
| US9127345B2 (en) | 2012-03-06 | 2015-09-08 | Asm America, Inc. | Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent |
| US8785285B2 (en) | 2012-03-08 | 2014-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor devices and methods of manufacture thereof |
| US9136348B2 (en) | 2012-03-12 | 2015-09-15 | United Microelectronics Corp. | Semiconductor structure and fabrication method thereof |
| US9202914B2 (en) | 2012-03-14 | 2015-12-01 | United Microelectronics Corporation | Semiconductor device and method for fabricating the same |
| US8664069B2 (en) | 2012-04-05 | 2014-03-04 | United Microelectronics Corp. | Semiconductor structure and process thereof |
| US9263345B2 (en) * | 2012-04-20 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | SOI transistors with improved source/drain structures with enhanced strain |
| US8866230B2 (en) | 2012-04-26 | 2014-10-21 | United Microelectronics Corp. | Semiconductor devices |
| US8835243B2 (en) | 2012-05-04 | 2014-09-16 | United Microelectronics Corp. | Semiconductor process |
| US20130344688A1 (en) * | 2012-06-20 | 2013-12-26 | Zhiyuan Ye | Atomic Layer Deposition with Rapid Thermal Treatment |
| US8951876B2 (en) | 2012-06-20 | 2015-02-10 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
| US8796695B2 (en) | 2012-06-22 | 2014-08-05 | United Microelectronics Corp. | Multi-gate field-effect transistor and process thereof |
| CN103531472B (en) * | 2012-07-03 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | A kind of MOSFET device and preparation method thereof |
| US9171715B2 (en) | 2012-09-05 | 2015-10-27 | Asm Ip Holding B.V. | Atomic layer deposition of GeO2 |
| US8710632B2 (en) | 2012-09-07 | 2014-04-29 | United Microelectronics Corp. | Compound semiconductor epitaxial structure and method for fabricating the same |
| JP5488675B2 (en) * | 2012-11-14 | 2014-05-14 | ソニー株式会社 | Manufacturing method of semiconductor device |
| US9117925B2 (en) | 2013-01-31 | 2015-08-25 | United Microelectronics Corp. | Epitaxial process |
| US8753902B1 (en) | 2013-03-13 | 2014-06-17 | United Microelectronics Corp. | Method of controlling etching process for forming epitaxial structure |
| US9034705B2 (en) | 2013-03-26 | 2015-05-19 | United Microelectronics Corp. | Method of forming semiconductor device |
| US9064893B2 (en) | 2013-05-13 | 2015-06-23 | United Microelectronics Corp. | Gradient dopant of strained substrate manufacturing method of semiconductor device |
| US9076652B2 (en) | 2013-05-27 | 2015-07-07 | United Microelectronics Corp. | Semiconductor process for modifying shape of recess |
| US8853060B1 (en) | 2013-05-27 | 2014-10-07 | United Microelectronics Corp. | Epitaxial process |
| US8765546B1 (en) | 2013-06-24 | 2014-07-01 | United Microelectronics Corp. | Method for fabricating fin-shaped field-effect transistor |
| US8895396B1 (en) | 2013-07-11 | 2014-11-25 | United Microelectronics Corp. | Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures |
| US8981487B2 (en) | 2013-07-31 | 2015-03-17 | United Microelectronics Corp. | Fin-shaped field-effect transistor (FinFET) |
| US9224657B2 (en) * | 2013-08-06 | 2015-12-29 | Texas Instruments Incorporated | Hard mask for source/drain epitaxy control |
| CN104347512B (en) * | 2013-08-07 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of CMOS transistor |
| US9218963B2 (en) | 2013-12-19 | 2015-12-22 | Asm Ip Holding B.V. | Cyclical deposition of germanium |
| CN105097694B (en) * | 2014-05-21 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| KR102216511B1 (en) | 2014-07-22 | 2021-02-18 | 삼성전자주식회사 | Semiconductor device |
| CN105448991B (en) * | 2014-09-01 | 2019-05-28 | 中芯国际集成电路制造(上海)有限公司 | Transistor and forming method thereof |
| KR102230198B1 (en) | 2014-09-23 | 2021-03-19 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
| CN105590852A (en) * | 2014-10-21 | 2016-05-18 | 上海华力微电子有限公司 | Method for decreasing dislocation defects of embedded silicon-germanium epitaxial growth |
| US9722045B2 (en) * | 2015-10-23 | 2017-08-01 | Globalfoundries Inc. | Buffer layer for modulating Vt across devices |
| US11011635B2 (en) | 2016-12-12 | 2021-05-18 | Applied Materials, Inc. | Method of forming conformal epitaxial semiconductor cladding material over a fin field effect transistor (FINFET) device |
| US10256322B2 (en) | 2017-04-04 | 2019-04-09 | Applied Materials, Inc. | Co-doping process for n-MOS source drain application |
| US9923081B1 (en) | 2017-04-04 | 2018-03-20 | Applied Materials, Inc. | Selective process for source and drain formation |
| KR102501287B1 (en) | 2018-07-30 | 2023-02-21 | 어플라이드 머티어리얼스, 인코포레이티드 | Selective silicon germanium epitaxy method at low temperatures |
| CN119725082A (en) * | 2018-08-11 | 2025-03-28 | 应用材料公司 | Doping Technology |
| US20200066516A1 (en) * | 2018-08-24 | 2020-02-27 | Micron Technology, Inc. | Semiconductor Structures Which Include Laminates of First and Second Regions, and Methods of Forming Semiconductor Structures |
| US11145504B2 (en) | 2019-01-14 | 2021-10-12 | Applied Materials, Inc. | Method of forming film stacks with reduced defects |
| CN112309843B (en) * | 2019-07-29 | 2026-01-23 | Asmip私人控股有限公司 | Selective deposition method for achieving high dopant incorporation |
| KR20210156219A (en) | 2020-06-16 | 2021-12-24 | 에이에스엠 아이피 홀딩 비.브이. | Method for depositing boron containing silicon germanium layers |
| TWI908816B (en) * | 2020-06-24 | 2025-12-21 | 荷蘭商Asm Ip私人控股有限公司 | Method for forming a layer provided with silicon |
| US20220102200A1 (en) * | 2020-09-30 | 2022-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Patterning material including carbon-containing layer and method for semiconductor device fabrication |
| US12444605B2 (en) | 2022-01-12 | 2025-10-14 | Applied Materials, Inc. | Epitaxial methods including a haloborane formula for growing boron-containing structures having increased boron concentrations |
| US20240035195A1 (en) * | 2022-07-29 | 2024-02-01 | Applied Materials, Inc. | Methods, systems, and apparatus for forming layers having single crystalline structures |
Family Cites Families (80)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5898917A (en) | 1981-12-09 | 1983-06-13 | Seiko Epson Corp | Atomic layer epitaxial device |
| US5693139A (en) | 1984-07-26 | 1997-12-02 | Research Development Corporation Of Japan | Growth of doped semiconductor monolayers |
| US5294286A (en) | 1984-07-26 | 1994-03-15 | Research Development Corporation Of Japan | Process for forming a thin film of silicon |
| JPS62171999A (en) | 1986-01-27 | 1987-07-28 | Nippon Telegr & Teleph Corp <Ntt> | Epitaxy of iii-v compound semiconductor |
| JPS6362313A (en) | 1986-09-03 | 1988-03-18 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0639357B2 (en) | 1986-09-08 | 1994-05-25 | 新技術開発事業団 | Method for growing element semiconductor single crystal thin film |
| US5607511A (en) * | 1992-02-21 | 1997-03-04 | International Business Machines Corporation | Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers |
| JPH01270593A (en) | 1988-04-21 | 1989-10-27 | Fujitsu Ltd | Method for forming compound semiconductor layer |
| US5112439A (en) * | 1988-11-30 | 1992-05-12 | Mcnc | Method for selectively depositing material on substrates |
| JPH02172895A (en) | 1988-12-22 | 1990-07-04 | Nec Corp | Method for growing semiconductor crystal |
| JPH0824191B2 (en) | 1989-03-17 | 1996-03-06 | 富士通株式会社 | Thin film transistor |
| EP0413982B1 (en) | 1989-07-27 | 1997-05-14 | Junichi Nishizawa | Impurity doping method with adsorbed diffusion source |
| JPH03286522A (en) | 1990-04-03 | 1991-12-17 | Nec Corp | Growth method of si crystal |
| JPH0547665A (en) | 1991-08-12 | 1993-02-26 | Fujitsu Ltd | Vapor growth method |
| JP2828152B2 (en) | 1991-08-13 | 1998-11-25 | 富士通 株式会社 | Method of forming thin film, multilayer structure film, and method of forming silicon thin film transistor |
| US5480818A (en) | 1992-02-10 | 1996-01-02 | Fujitsu Limited | Method for forming a film and method for manufacturing a thin film transistor |
| JPH0750690B2 (en) | 1992-08-21 | 1995-05-31 | 日本電気株式会社 | Method and apparatus for epitaxial growth of semiconductor crystal using halide |
| US5273930A (en) * | 1992-09-03 | 1993-12-28 | Motorola, Inc. | Method of forming a non-selective silicon-germanium epitaxial film |
| US5372860A (en) | 1993-07-06 | 1994-12-13 | Corning Incorporated | Silicon device production |
| JPH07109573A (en) | 1993-10-12 | 1995-04-25 | Semiconductor Energy Lab Co Ltd | Glass substrate and heat treatment |
| US5796116A (en) | 1994-07-27 | 1998-08-18 | Sharp Kabushiki Kaisha | Thin-film semiconductor device including a semiconductor film with high field-effect mobility |
| JP3761918B2 (en) * | 1994-09-13 | 2006-03-29 | 株式会社東芝 | Manufacturing method of semiconductor device |
| EP0799495A4 (en) * | 1994-11-10 | 1999-11-03 | Lawrence Semiconductor Researc | SILICON-GERMANIUM-CARBON COMPOSITIONS AND RELATED PROCESSES |
| US5846867A (en) * | 1995-12-20 | 1998-12-08 | Sony Corporation | Method of producing Si-Ge base heterojunction bipolar device |
| AUPO347196A0 (en) | 1996-11-06 | 1996-12-05 | Pacific Solar Pty Limited | Improved method of forming polycrystalline-silicon films on glass |
| US5807792A (en) | 1996-12-18 | 1998-09-15 | Siemens Aktiengesellschaft | Uniform distribution of reactants in a device layer |
| JPH10189459A (en) * | 1996-12-27 | 1998-07-21 | Sony Corp | Method for forming boron-doped silicon-germanium mixed crystal |
| US6335280B1 (en) | 1997-01-13 | 2002-01-01 | Asm America, Inc. | Tungsten silicide deposition process |
| US6118216A (en) | 1997-06-02 | 2000-09-12 | Osram Sylvania Inc. | Lead and arsenic free borosilicate glass and lamp containing same |
| US6042654A (en) * | 1998-01-13 | 2000-03-28 | Applied Materials, Inc. | Method of cleaning CVD cold-wall chamber and exhaust lines |
| US6514880B2 (en) | 1998-02-05 | 2003-02-04 | Asm Japan K.K. | Siloxan polymer film on semiconductor substrate and method for forming same |
| US6383955B1 (en) | 1998-02-05 | 2002-05-07 | Asm Japan K.K. | Silicone polymer insulation film on semiconductor substrate and method for forming the film |
| TW437017B (en) | 1998-02-05 | 2001-05-28 | Asm Japan Kk | Silicone polymer insulation film on semiconductor substrate and method for formation thereof |
| US6159852A (en) * | 1998-02-13 | 2000-12-12 | Micron Technology, Inc. | Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor |
| JP2002503864A (en) * | 1998-02-13 | 2002-02-05 | サムソン アドバンスド インスティトュート オブ テクノロジー | Optical recording media based on thin recording layers |
| US6797558B2 (en) * | 2001-04-24 | 2004-09-28 | Micron Technology, Inc. | Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer |
| KR100652909B1 (en) | 1998-03-06 | 2006-12-01 | 에이에스엠 아메리카, 인코포레이티드 | Silicon Deposition Method With High Step Coverage |
| JP4214585B2 (en) | 1998-04-24 | 2009-01-28 | 富士ゼロックス株式会社 | Semiconductor device, semiconductor device manufacturing method and manufacturing apparatus |
| US6025627A (en) | 1998-05-29 | 2000-02-15 | Micron Technology, Inc. | Alternate method and structure for improved floating gate tunneling devices |
| JP3809035B2 (en) * | 1998-06-29 | 2006-08-16 | 株式会社東芝 | MIS type transistor and manufacturing method thereof |
| KR100287180B1 (en) | 1998-09-17 | 2001-04-16 | 윤종용 | Method for manufacturing semiconductor device including metal interconnection formed using interface control layer |
| DE19845427A1 (en) * | 1998-10-02 | 2000-04-06 | Basf Ag | Fluid applicator, for applying a polymer or adhesive dispersion onto a moving surface, has a separation element between initial and main fluid supply chambers for defining a separation gap with the surface |
| JP2002530864A (en) * | 1998-11-12 | 2002-09-17 | インテル・コーポレーション | Field effect transistor structure having a step source / drain junction |
| US6235568B1 (en) * | 1999-01-22 | 2001-05-22 | Intel Corporation | Semiconductor device having deposited silicon regions and a method of fabrication |
| US6305314B1 (en) * | 1999-03-11 | 2001-10-23 | Genvs, Inc. | Apparatus and concept for minimizing parasitic chemical vapor deposition during atomic layer deposition |
| JP2001024194A (en) * | 1999-05-06 | 2001-01-26 | Toshiba Corp | Semiconductor device manufacturing method and semiconductor device |
| DE60042045D1 (en) * | 1999-06-22 | 2009-06-04 | Panasonic Corp | Heterojunction bipolar transistors and corresponding manufacturing methods |
| KR20010017820A (en) | 1999-08-14 | 2001-03-05 | 윤종용 | Semiconductor device and manufacturing method thereof |
| US6489241B1 (en) * | 1999-09-17 | 2002-12-03 | Applied Materials, Inc. | Apparatus and method for surface finishing a silicon film |
| SG99871A1 (en) | 1999-10-25 | 2003-11-27 | Motorola Inc | Method for fabricating a semiconductor structure including a metal oxide interface with silicon |
| WO2001041544A2 (en) | 1999-12-11 | 2001-06-14 | Asm America, Inc. | Deposition of gate stacks including silicon germanium layers |
| US6291319B1 (en) * | 1999-12-17 | 2001-09-18 | Motorola, Inc. | Method for fabricating a semiconductor structure having a stable crystalline interface with silicon |
| US6348420B1 (en) | 1999-12-23 | 2002-02-19 | Asm America, Inc. | Situ dielectric stacks |
| EP1123991A3 (en) | 2000-02-08 | 2002-11-13 | Asm Japan K.K. | Low dielectric constant materials and processes |
| WO2001071787A1 (en) | 2000-03-17 | 2001-09-27 | Varian Semiconductor Equipment Associates, Inc. | Method of forming ultrashallow junctions by laser annealing and rapid thermal annealing |
| US6458718B1 (en) | 2000-04-28 | 2002-10-01 | Asm Japan K.K. | Fluorine-containing materials and processes |
| JP2001338988A (en) * | 2000-05-25 | 2001-12-07 | Hitachi Ltd | Semiconductor device and manufacturing method thereof |
| JP4882141B2 (en) * | 2000-08-16 | 2012-02-22 | 富士通株式会社 | Hetero bipolar transistor |
| JP2002198525A (en) | 2000-12-27 | 2002-07-12 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| KR100393208B1 (en) | 2001-01-15 | 2003-07-31 | 삼성전자주식회사 | Semiconductor device using doped polycrystalline silicon-germanium layer and method for manufacturing the same |
| US6528374B2 (en) * | 2001-02-05 | 2003-03-04 | International Business Machines Corporation | Method for forming dielectric stack without interfacial layer |
| US7026219B2 (en) | 2001-02-12 | 2006-04-11 | Asm America, Inc. | Integration of high k gate dielectric |
| KR101027485B1 (en) | 2001-02-12 | 2011-04-06 | 에이에스엠 아메리카, 인코포레이티드 | Improved Process for Semiconductor Thin Film Deposition |
| JP3890202B2 (en) | 2001-03-28 | 2007-03-07 | 株式会社日立製作所 | Manufacturing method of semiconductor device |
| US7005372B2 (en) * | 2003-01-21 | 2006-02-28 | Novellus Systems, Inc. | Deposition of tungsten nitride |
| US6905542B2 (en) * | 2001-05-24 | 2005-06-14 | Arkadii V. Samoilov | Waveguides such as SiGeC waveguides and method of fabricating the same |
| WO2002097864A2 (en) | 2001-05-30 | 2002-12-05 | Asm America, Inc | Low temperature load and bake |
| JP4277467B2 (en) * | 2001-10-29 | 2009-06-10 | 株式会社Sumco | Semiconductor substrate, field effect transistor, and manufacturing method thereof |
| US7439191B2 (en) | 2002-04-05 | 2008-10-21 | Applied Materials, Inc. | Deposition of silicon layers for active matrix liquid crystal display (AMLCD) applications |
| US7186630B2 (en) * | 2002-08-14 | 2007-03-06 | Asm America, Inc. | Deposition of amorphous silicon-containing films |
| JP2004079887A (en) * | 2002-08-21 | 2004-03-11 | Renesas Technology Corp | Semiconductor device |
| JP2004095639A (en) * | 2002-08-29 | 2004-03-25 | Fujitsu Ltd | Semiconductor device and manufacturing method thereof |
| US6998305B2 (en) | 2003-01-24 | 2006-02-14 | Asm America, Inc. | Enhanced selectivity for epitaxial deposition |
| US20040226911A1 (en) * | 2003-04-24 | 2004-11-18 | David Dutton | Low-temperature etching environment |
| US6982433B2 (en) * | 2003-06-12 | 2006-01-03 | Intel Corporation | Gate-induced strain for MOS performance improvement |
| US20050007692A1 (en) * | 2003-06-26 | 2005-01-13 | Spectra Logic Corporation | Magazine-Based Data Cartridge Library |
| US6855963B1 (en) | 2003-08-29 | 2005-02-15 | International Business Machines Corporation | Ultra high-speed Si/SiGe modulation-doped field effect transistors on ultra thin SOI/SGOI substrate |
| US7166528B2 (en) * | 2003-10-10 | 2007-01-23 | Applied Materials, Inc. | Methods of selective deposition of heavily doped epitaxial SiGe |
| US7132338B2 (en) | 2003-10-10 | 2006-11-07 | Applied Materials, Inc. | Methods to fabricate MOSFET devices using selective deposition process |
| US7045432B2 (en) | 2004-02-04 | 2006-05-16 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) |
-
2004
- 2004-05-14 US US10/845,984 patent/US7132338B2/en not_active Expired - Lifetime
-
2005
- 2005-05-10 CN CN2009101438065A patent/CN101593680B/en not_active Expired - Lifetime
- 2005-05-10 EP EP05746857A patent/EP1745503A2/en not_active Withdrawn
- 2005-05-10 JP JP2007513252A patent/JP2007537601A/en active Pending
- 2005-05-10 WO PCT/US2005/016160 patent/WO2005112577A2/en not_active Ceased
- 2005-05-10 CN CNB2005800061362A patent/CN100511587C/en not_active Expired - Lifetime
- 2005-05-11 TW TW094115281A patent/TWI442448B/en not_active IP Right Cessation
-
2006
- 2006-10-09 US US11/539,775 patent/US7439142B2/en not_active Expired - Lifetime
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Also Published As
| Publication number | Publication date |
|---|---|
| EP1745503A2 (en) | 2007-01-24 |
| WO2005112577A3 (en) | 2006-05-26 |
| US20050079692A1 (en) | 2005-04-14 |
| US7132338B2 (en) | 2006-11-07 |
| TW200537592A (en) | 2005-11-16 |
| US7439142B2 (en) | 2008-10-21 |
| TWI442448B (en) | 2014-06-21 |
| JP2007537601A (en) | 2007-12-20 |
| CN101593680A (en) | 2009-12-02 |
| CN1926664A (en) | 2007-03-07 |
| CN100511587C (en) | 2009-07-08 |
| CN101593680B (en) | 2011-02-23 |
| US20070082451A1 (en) | 2007-04-12 |
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