WO2006002278A3 - Apparatus and method for improving dynamic refresh in a semiconductor memory device with reduced stanby power - Google Patents

Apparatus and method for improving dynamic refresh in a semiconductor memory device with reduced stanby power Download PDF

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Publication number
WO2006002278A3
WO2006002278A3 PCT/US2005/022144 US2005022144W WO2006002278A3 WO 2006002278 A3 WO2006002278 A3 WO 2006002278A3 US 2005022144 W US2005022144 W US 2005022144W WO 2006002278 A3 WO2006002278 A3 WO 2006002278A3
Authority
WO
WIPO (PCT)
Prior art keywords
time delay
memory device
response
reduced
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/022144
Other languages
French (fr)
Other versions
WO2006002278A2 (en
Inventor
Simon Lovett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to JP2007511730A priority Critical patent/JP2007536684A/en
Priority to EP05771569.0A priority patent/EP1776704B1/en
Priority to KR1020067024960A priority patent/KR101184517B1/en
Publication of WO2006002278A2 publication Critical patent/WO2006002278A2/en
Publication of WO2006002278A3 publication Critical patent/WO2006002278A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

An apparatus and method for generating a control pulse for closing an active wordline in a memory device is provided. A timeout generator circuit having a time delay portion and a reset portion may be used to generate a close signal. The time delay portion may define a predetermined time delay interval. The timeout generator may be used in combination with an address transition detector in a refresh controller for a memory device. A method is given in which a control pulse is generated in response to an active mode signal, a timer measuring a predetermined time delay interval is activated in response to the control pulse, a close signal is produced in response to the expiration of the predetermined time delay interval, and the active wordline is closed in response to the close signal.
PCT/US2005/022144 2004-06-22 2005-06-22 Apparatus and method for improving dynamic refresh in a semiconductor memory device with reduced stanby power Ceased WO2006002278A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2007511730A JP2007536684A (en) 2004-06-22 2005-06-22 Apparatus and method for improving dynamic refresh in a memory device
EP05771569.0A EP1776704B1 (en) 2004-06-22 2005-06-22 Word line control circuit for improving dynamic refresh in a semiconductor memory device with reduced standby power
KR1020067024960A KR101184517B1 (en) 2004-06-22 2005-06-22 Apparatus and Method for Improving Dynamic Refresh in a Memeory Device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/873,968 US7167400B2 (en) 2004-06-22 2004-06-22 Apparatus and method for improving dynamic refresh in a memory device
US10/873,968 2004-06-22

Publications (2)

Publication Number Publication Date
WO2006002278A2 WO2006002278A2 (en) 2006-01-05
WO2006002278A3 true WO2006002278A3 (en) 2006-03-16

Family

ID=35456929

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/022144 Ceased WO2006002278A2 (en) 2004-06-22 2005-06-22 Apparatus and method for improving dynamic refresh in a semiconductor memory device with reduced stanby power

Country Status (6)

Country Link
US (2) US7167400B2 (en)
EP (1) EP1776704B1 (en)
JP (1) JP2007536684A (en)
KR (1) KR101184517B1 (en)
CN (1) CN101218649A (en)
WO (1) WO2006002278A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7142446B2 (en) * 2004-07-29 2006-11-28 Micron Technology, Inc. Apparatus and method to reduce undesirable effects caused by a fault in a memory device
KR100862482B1 (en) 2007-03-21 2008-10-08 삼성전기주식회사 Rotary input device
US8004920B2 (en) 2007-05-29 2011-08-23 Micron Technology, Inc. Power saving memory apparatus, systems, and methods
TWI394156B (en) * 2008-12-09 2013-04-21 Winbond Electronics Corp Refreshing method
KR101932663B1 (en) * 2012-07-12 2018-12-26 삼성전자 주식회사 Semiconductor memory device storing refresh period information and operating method thereof
WO2016118848A1 (en) * 2015-01-22 2016-07-28 Clearstream. Tv, Inc. Video advertising system
US10529401B2 (en) 2018-05-04 2020-01-07 Micron Technology, Inc. Access line management for an array of memory cells
US10896713B2 (en) 2018-05-04 2021-01-19 Micron Technology, Inc. Access line management for an array of memory cells
US10990319B2 (en) 2018-06-18 2021-04-27 Micron Technology, Inc. Adaptive watchdog in a memory device
US10998893B2 (en) * 2018-08-01 2021-05-04 Micron Technology, Inc. Semiconductor device, delay circuit, and related method

Citations (4)

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Publication number Priority date Publication date Assignee Title
US20010026492A1 (en) * 2000-03-29 2001-10-04 Nec Corporation Semiconductor memory device with a refresh function
US20020176302A1 (en) * 2001-05-25 2002-11-28 Tae Hyung Jung Cell data protection circuit in semiconductor memory device and method of driving refresh mode
US20020181301A1 (en) * 1999-12-03 2002-12-05 Hiroyuki Takahashi Semiconductor storage and method for testing the same
US20040076054A1 (en) * 2002-10-11 2004-04-22 Nec Electronics Corporation Semiconductor memory device having mode storing one bit data in two memory cells and method of controlling same

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JPS59104788A (en) * 1982-12-08 1984-06-16 Toshiba Corp Semiconductor memory device
JPH0766660B2 (en) 1985-03-25 1995-07-19 株式会社日立製作所 Dynamic RAM
JPS62180607A (en) * 1986-02-04 1987-08-07 Fujitsu Ltd Semiconductor integrated circuit
JPS63155494A (en) 1986-12-19 1988-06-28 Fujitsu Ltd Pseudo static memory device
JPH06243700A (en) * 1992-12-25 1994-09-02 Sony Corp Semiconductor memory and method of selecting the same
JP3702038B2 (en) * 1996-05-14 2005-10-05 株式会社ルネサステクノロジ Delay circuit
JP3087653B2 (en) * 1996-05-24 2000-09-11 日本電気株式会社 Semiconductor storage device
US5875152A (en) * 1996-11-15 1999-02-23 Macronix International Co., Ltd. Address transition detection circuit for a semiconductor memory capable of detecting narrowly spaced address changes
JP2001052476A (en) * 1999-08-05 2001-02-23 Mitsubishi Electric Corp Semiconductor device
JP2001357670A (en) * 2000-04-14 2001-12-26 Mitsubishi Electric Corp Semiconductor storage device
CN1303610C (en) * 2000-07-07 2007-03-07 睦塞德技术公司 Method and appts. for synchronzation of row and column access operation
JP3967559B2 (en) 2001-04-06 2007-08-29 富士通株式会社 Control circuit and semiconductor memory device
US6452426B1 (en) * 2001-04-16 2002-09-17 Nagesh Tamarapalli Circuit for switching between multiple clocks
US6690606B2 (en) * 2002-03-19 2004-02-10 Micron Technology, Inc. Asynchronous interface circuit and method for a pseudo-static memory device
JP4077337B2 (en) * 2003-02-27 2008-04-16 株式会社東芝 Pulse generation circuit and high side driver circuit using the same
TWI221616B (en) * 2003-08-06 2004-10-01 Ememory Technology Inc Delay circuits and related apparatus for extending delay time by active feedback elements

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020181301A1 (en) * 1999-12-03 2002-12-05 Hiroyuki Takahashi Semiconductor storage and method for testing the same
US20010026492A1 (en) * 2000-03-29 2001-10-04 Nec Corporation Semiconductor memory device with a refresh function
US20020176302A1 (en) * 2001-05-25 2002-11-28 Tae Hyung Jung Cell data protection circuit in semiconductor memory device and method of driving refresh mode
US20040076054A1 (en) * 2002-10-11 2004-04-22 Nec Electronics Corporation Semiconductor memory device having mode storing one bit data in two memory cells and method of controlling same

Also Published As

Publication number Publication date
EP1776704B1 (en) 2014-04-30
US7307901B2 (en) 2007-12-11
KR20070027563A (en) 2007-03-09
CN101218649A (en) 2008-07-09
WO2006002278A2 (en) 2006-01-05
US7167400B2 (en) 2007-01-23
EP1776704A2 (en) 2007-04-25
US20050281099A1 (en) 2005-12-22
JP2007536684A (en) 2007-12-13
KR101184517B1 (en) 2012-09-19
US20070104018A1 (en) 2007-05-10

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