WO2006011851A1 - Reliable contacts - Google Patents

Reliable contacts Download PDF

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Publication number
WO2006011851A1
WO2006011851A1 PCT/SG2004/000220 SG2004000220W WO2006011851A1 WO 2006011851 A1 WO2006011851 A1 WO 2006011851A1 SG 2004000220 W SG2004000220 W SG 2004000220W WO 2006011851 A1 WO2006011851 A1 WO 2006011851A1
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WO
WIPO (PCT)
Prior art keywords
nickel
contact
layer
processing material
germanium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/SG2004/000220
Other languages
French (fr)
Inventor
Dongzhi Chi
Ka Yau Lee
Tek Po Rinus Lee
Siao Li Liew
Hai Biao Yao
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Agency for Science Technology and Research Singapore
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Agency for Science Technology and Research Singapore
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Publication date
Application filed by Agency for Science Technology and Research Singapore filed Critical Agency for Science Technology and Research Singapore
Priority to EP04749242A priority Critical patent/EP1787332A4/en
Priority to PCT/SG2004/000220 priority patent/WO2006011851A1/en
Priority to JP2007523511A priority patent/JP2008508713A/en
Priority to CNA200480043680XA priority patent/CN101032028A/en
Priority to US11/572,632 priority patent/US20070272955A1/en
Priority to TW094124581A priority patent/TW200605307A/en
Publication of WO2006011851A1 publication Critical patent/WO2006011851A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0186—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment

Definitions

  • the invention relates generally to the formation of germanide contacts used in, for example, integrated circuits (ICs) . More particularly, the invention relates to improved formation of nickel-based germanide contacts used in integrated circuits.
  • ICs integrated circuits
  • Fig. 1 shows a portion 100 of a conventional CMOS IC.
  • the portion includes first and second complementary transistors 120 and 140 formed on a silicon substrate 101.
  • the first transistor is an n-MOS transistor formed on a deep p-doped well 121 while the second transistor is a p- MOS transistor formed on a deep n-doped well 141.
  • Beneath the n-MOS transistor is a shallow p-doped well 122 while a shallow n-doped well is located below the p-MOS transistor 142.
  • Shallow trench isolations 160 are used to isolate the transistors.
  • Each transistor includes source (123 or 143) , drain (124 or 144) , and gate (125 or 145) electrodes.
  • the source, drain and gate electrodes are doped with n-type dopants, such as P.
  • the source, drain, and gate electrodes are doped with p-type dopants, such as B.
  • titanium or cobalt suicide is used. Titanium and cobalt suicides are used as contacts 170 due to their good electrical properties and relatively high thermal stability.
  • the metal suicide contacts are formed using self-aligned salicide processes. As part of the self-aligned process, dielectric side-wall spacers (128 and 148) on the sides of the gate electrodes may be used. Salicide processes are described in, for example, Sze, "ULSI Technology", McGraw- Hill (1996) , which is herein incorporated by reference for all purposes.
  • germanium-based substrates are employed, such as germanium or germanium- silicon.
  • Germanium-based substrates are advantageous for high-speed applications due to their high carrier mobility characteristics, which are conducive for large drive currents.
  • metal germanide processes are used.
  • Titanium and cobalt metals which are widely used to form suicide contacts, are incompatible with germanide processes. This is because forming titanium or cobalt contacts with good electrical characteristics (e.g., low resistivity) requires relatively high annealing temperatures which are detrimental to germanium-based applications. For example, high temperatures cause evaporation of germanium or, where intentionally strained materials are used, undesirably relax the strain in such materials.
  • the invention relates generally to fabrication of, for example, integrated circuits.
  • a substrate is provided.
  • the substrate includes an active region comprising germanium.
  • a nickel-based 'contact is formed on the active region.
  • the nickel-based contact comprises a processing material which inhibits agglomeration of nickel during processing. This results in improved electrical characteristics of the nickel-based contact .
  • a nickel layer is deposited over the substrate, covering the active region.
  • a capping layer comprising the processing material is formed over the nickel layer.
  • the nickel layer comprises the processing material, forming a nickel alloy layer.
  • the substrate is then processed by annealing to form the nickel-based contact.
  • the processing material of the capping layer or the contact layer inhibits agglomeration of nickel during anneal to form the nickel- based contact .
  • Fig. 1 shows a portion of a conventional CMOS IC
  • Figs. 2-6 show a process for forming contacts in accordance with one embodiment of the invention.
  • Figs. 2-6 show a process for forming nickel-based contacts in accordance with one embodiment of the invention.
  • the substrate serves to form integrated circuit components.
  • the substrate comprises a multi-layered substrate in which at least the top or surface layer comprises germanium.
  • the multi-layered substrate comprises a germanium- on-insulator substrate.
  • the germanium-on-insulator substrate may include a silicon bulk substrate 203 with a top layer 205 comprising germanium separated by an insulator layer 204, such as silicon oxide.
  • the top layer of the substrate comprises, for example, a single crystalline material, a polycrystalline or amorphous material, or a combination thereof.
  • the germanium layer can be strained or relaxed. Providing a surface comprising germanium over a silicon-germanium bulk layer is also useful .
  • the top or surface layer of the substrate comprises silicon-germanium.
  • the silicon-germanium layer comprises Sii_ x Ge x where x is less than 50 atomic percent.
  • the silicon- germanium layer can be strained or relaxed.
  • the substrate can also include silicon-germanium over silicon-germanium having different percentages of Ge. Providing a single- layered substrate comprising germanium, including silicon- germanium is also useful.
  • at least a portion of the top surface of the substrate comprises germanium, including silicon-germanium.
  • a thin strained layer of silicon provided on top of the germanium layer is also useful.
  • the silicon layer should be sufficiently thin to maintain tensile strain.
  • the thickness of the thin strained silicon layer is less than 100 nm.
  • a portion of the substrate is prepared with doped wells for transistors. As shown, the wells are prepared for a CMOS application. Other types of applications are also useful.
  • active regions 308 and 309 for a p-MOS and n-MOS transistor, respectively, are provided.
  • the active region of the p-MOS transistor includes a deep p-well 321 and shallow n-well 322.
  • the active region of the n-MOS transistor includes a deep n-well 341 and a shallow p-well 342. Separating the active regions are shallow trench isolations (STIs) 360.
  • STIs shallow trench isolations
  • the process continues by forming p-MOS and n-MOS transistors 420 and 440 in active regions 308 and 309.
  • the transistors each includes first and second diffusion regions (423-424 or 443-444) and a gate (425 or 445) .
  • the diffusion regions of the p-MOS transistor comprise p-type dopants while the diffusion regions of the n-MOS transistor comprise n-type dopants.
  • the gates of the transistors comprise germanium.
  • the gate comprises polycrystalline germanium. Other types of materials, such as silicon or silicon- germanium, are also useful.
  • the gates are doped with dopants.
  • the gates of the transistors are doped with p-type dopants. Doping the gates with other dopants is also useful. It may also be useful to dope the gates of the p-MOS and n-MOS transistors with different types of dopants.
  • Beneath the gate is a gate oxide layer.
  • the gate oxide layer comprises, for example, thermally grown silicon oxide. Other types of gate oxide materials are also useful.
  • insulating sidewall spacers 428 and 448 are provided on the sides of the p-MOS and n-MOS gates.
  • a nickel layer 571 is deposited on the substrate.
  • Various techniques can be used to form the nickel layer, such as sputtering, including magnetron sputtering.
  • the nickel layer is sputtered, for example, at a pressure of about 5X10 "7 Torr at about room temperature. Other techniques or parameters for forming the nickel layer are also useful .
  • the thickness of the nickel layer is about 5-100 nm. Preferably, the thickness of the nickel layer is less than about 50 nm. Other thicknesses may also be useful .
  • a capping layer 572 is formed over the nickel layer.
  • the capping layer in one embodiment, comprises a material which inhibits the agglomeration of the nickel germanide layer.
  • the material of the capping layer is insoluble in the nickel-based contact.
  • the capping layer comprises Mo, Ta, Ti, W, Zr or a combination thereof. Other materials that can inhibit agglomeration of nickel germanide at processing temperatures are also useful.
  • the capping layer comprises a material which is soluble in the nickel-based contact, such as Pd and/or Pt. The use of a combination of soluble and insoluble materials in the nickel-based contact to form the capping layer is also useful .
  • the capping layer can be formed using sputtering, including magnetron sputtering.
  • the sputtering in one embodiment, is performed at room temperature.
  • Other techniques or parameters for forming the capping layer such as thermal and electron-beam evaporation are also useful.
  • the thickness of the capping layer should be sufficient to inhibit agglomeration in the layer at temperatures greater than about 500 0 C.
  • the thickness of the capping layer should be sufficient to inhibit agglomeration in the layer at least up to temperatures of about 700 0 C.
  • the thickness of the capping layer should be sufficient to inhibit agglomeration in the layer at temperatures from about 500-700 0 C.
  • the thickness of the capping layer for example, is less than or equal to about 50 nm.
  • the thickness of the capping layer is about 5 nm.
  • the substrate is annealed to form the contacts.
  • the annealing causes the materials of the contact layers and substrate to react, forming nickel-based germanide or nickel-based germanosilicide contacts in substrate areas comprising germanium.
  • nickel-based monogermanide contacts are formed while nickel-based germanosilicide contacts are formed for silicon germanium underlying layers.
  • the annealing comprises a rapid thermal anneal (RTP) .
  • RTP rapid thermal anneal
  • Other types of annealing are also useful.
  • the RTP is performed at a temperature of about 200 0 C to at least about 700 0 C for about 1-100 seconds.
  • the RTP is performed at a temperature of about 280 0 C to at least about 500 0 C.
  • the ambient of the RTP is, for example, nitrogen.
  • Other types of ambients, such as vacuum, He, Ar are also useful .
  • Other types of inert gases can also be used.
  • the contact layers are patterned to leave portions of the contact layers in areas where contacts are formed.
  • materials of the contact layers are removed from areas 690 and 691 above the STIs and sidewall spacers, leaving the contact layers over the surface of the diffusion regions and gates.
  • the contact layers are patterned by, for example, conventional mask and etch techniques. For example, a photoresist layer is deposited and patterned to expose portions of the layers to be removed, followed by an etch process to remove the layers unprotected by the photoresist layer.
  • the contact layers are patterned prior to the annealing process for forming the contacts.
  • a contact layer comprising nickel-based alloy is deposited over the substrate prepared with the transistors, as described in, for example, Fig. 4.
  • the nickel-based alloy comprises NiY, where Y comprises a material selected from a material which inhibits agglomeration of the contact layer.
  • Y comprises a material which is insoluble in nickel-based contact.
  • Y comprises Mo, Ta, Ti, Mo, W, Zr or a combination thereof. Other materials which are insoluble in the nickel-based contact are also useful.
  • Y comprises a material which is soluble in the nickel-based contact, such as Pd and/or Pt. Providing Y comprising a combination of both soluble and insoluble materials in the nickel-based contact is also useful.
  • the thickness of the nickel-based alloy layer is, for example, about 5-100nm. Preferably, the thickness of the nickel-based alloy layer is less than 50nm.
  • the percentage of Y should be sufficient to inhibit agglomeration in the layer at temperatures greater than about 500 0 C.
  • the percentage of Y should be sufficient to inhibit agglomeration in the layer at least up to temperatures of about 700 0 C. More preferably, the percentage of Y should be sufficient to inhibit agglomeration in the layer at temperatures from about 500-700 0 C.
  • the percentage of Y for example, is about 0.1 to 50 atomic percent.
  • the percentage of Y is less than about 20 atomic percent .
  • Contacts are formed in regions comprising nickel and germanium. In areas where germanium is absent (e.g., above the STI) , no reaction occurs. Unreacted portions of the nickel layer are selectively removed using, for example, a wet etch selective to the reacted portions of the nickel layer. As a result, self-aligned nickel germanide or nickel germanosilicide contacts are formed.

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  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Contacts (AREA)
  • Conductive Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A nickel-based germanide contact includes a processing material that inhibits agglomeration of nickel-based germanide during processing to form the contact as well as during post-germanidation processes. The processing material is either in the form of a capping layer over the nickel layer or integrated into the nickel layer used to form the nickel-based contact. Reducing agglomeration improves electrical characteristics of the contact.

Description

RELIABLE CONTACTS
FIELD OF THE INVENTION
The invention relates generally to the formation of germanide contacts used in, for example, integrated circuits (ICs) . More particularly, the invention relates to improved formation of nickel-based germanide contacts used in integrated circuits.
BACKGROUND OF THE INVENTION
Fig. 1 shows a portion 100 of a conventional CMOS IC. The portion includes first and second complementary transistors 120 and 140 formed on a silicon substrate 101. The first transistor is an n-MOS transistor formed on a deep p-doped well 121 while the second transistor is a p- MOS transistor formed on a deep n-doped well 141. Beneath the n-MOS transistor is a shallow p-doped well 122 while a shallow n-doped well is located below the p-MOS transistor 142. Shallow trench isolations 160 are used to isolate the transistors. Each transistor includes source (123 or 143) , drain (124 or 144) , and gate (125 or 145) electrodes. For an n-MOS transistor, the source, drain and gate electrodes are doped with n-type dopants, such as P. As for the p-MOS transistor, the source, drain, and gate electrodes are doped with p-type dopants, such as B.
To reduce contact resistance in, for example, the source, drain, and gate electrodes of transistors, titanium or cobalt suicide is used. Titanium and cobalt suicides are used as contacts 170 due to their good electrical properties and relatively high thermal stability. The metal suicide contacts are formed using self-aligned salicide processes. As part of the self-aligned process, dielectric side-wall spacers (128 and 148) on the sides of the gate electrodes may be used. Salicide processes are described in, for example, Sze, "ULSI Technology", McGraw- Hill (1996) , which is herein incorporated by reference for all purposes.
For high-speed applications, germanium-based substrates are employed, such as germanium or germanium- silicon. Germanium-based substrates are advantageous for high-speed applications due to their high carrier mobility characteristics, which are conducive for large drive currents. To form contacts for source, drain, and gate electrodes in germanium-based substrates, metal germanide processes are used.
Titanium and cobalt metals, which are widely used to form suicide contacts, are incompatible with germanide processes. This is because forming titanium or cobalt contacts with good electrical characteristics (e.g., low resistivity) requires relatively high annealing temperatures which are detrimental to germanium-based applications. For example, high temperatures cause evaporation of germanium or, where intentionally strained materials are used, undesirably relax the strain in such materials.
From the foregoing discussion, it is desirable to provide an improved germanide contact for use in ICs.
SUMMARY OF THE INVENTION
The invention relates generally to fabrication of, for example, integrated circuits. In one embodiment, a substrate is provided. The substrate includes an active region comprising germanium. A nickel-based 'contact is formed on the active region. The nickel-based contact comprises a processing material which inhibits agglomeration of nickel during processing. This results in improved electrical characteristics of the nickel-based contact . In one embodiment, a nickel layer is deposited over the substrate, covering the active region. A capping layer comprising the processing material is formed over the nickel layer. In another embodiment, the nickel layer comprises the processing material, forming a nickel alloy layer. The substrate is then processed by annealing to form the nickel-based contact. The processing material of the capping layer or the contact layer inhibits agglomeration of nickel during anneal to form the nickel- based contact .
BRIEF DESCRIPTION OF DRAWINGS
Fig. 1 shows a portion of a conventional CMOS IC; and Figs. 2-6 show a process for forming contacts in accordance with one embodiment of the invention.
DETAILED DESCRIPTION OF THE INVENTION
Figs. 2-6 show a process for forming nickel-based contacts in accordance with one embodiment of the invention. Referring to Fig. 2, a cross-section of a portion of a substrate 201 is shown. The substrate serves to form integrated circuit components. In one embodiment, the substrate comprises a multi-layered substrate in which at least the top or surface layer comprises germanium. For example, the multi-layered substrate comprises a germanium- on-insulator substrate. The germanium-on-insulator substrate may include a silicon bulk substrate 203 with a top layer 205 comprising germanium separated by an insulator layer 204, such as silicon oxide. The top layer of the substrate comprises, for example, a single crystalline material, a polycrystalline or amorphous material, or a combination thereof. The germanium layer can be strained or relaxed. Providing a surface comprising germanium over a silicon-germanium bulk layer is also useful .
In another embodiment, at least the top or surface layer of the substrate comprises silicon-germanium. Preferably, the silicon-germanium layer comprises Sii_xGex where x is less than 50 atomic percent. The silicon- germanium layer can be strained or relaxed. The substrate can also include silicon-germanium over silicon-germanium having different percentages of Ge. Providing a single- layered substrate comprising germanium, including silicon- germanium is also useful. In yet another embodiment, at least a portion of the top surface of the substrate comprises germanium, including silicon-germanium.
Alternatively, a thin strained layer of silicon provided on top of the germanium layer is also useful. The silicon layer should be sufficiently thin to maintain tensile strain. Typically, the thickness of the thin strained silicon layer is less than 100 nm.
Referring to Fig. 3, a portion of the substrate is prepared with doped wells for transistors. As shown, the wells are prepared for a CMOS application. Other types of applications are also useful. In one embodiment, active regions 308 and 309 for a p-MOS and n-MOS transistor, respectively, are provided. The active region of the p-MOS transistor includes a deep p-well 321 and shallow n-well 322. The active region of the n-MOS transistor includes a deep n-well 341 and a shallow p-well 342. Separating the active regions are shallow trench isolations (STIs) 360.
As shown in Fig. 4, the process continues by forming p-MOS and n-MOS transistors 420 and 440 in active regions 308 and 309. The transistors each includes first and second diffusion regions (423-424 or 443-444) and a gate (425 or 445) . The diffusion regions of the p-MOS transistor comprise p-type dopants while the diffusion regions of the n-MOS transistor comprise n-type dopants. The gates of the transistors comprise germanium.
Typically, the gate comprises polycrystalline germanium. Other types of materials, such as silicon or silicon- germanium, are also useful. Preferably, the gates are doped with dopants. In one embodiment, the gates of the transistors are doped with p-type dopants. Doping the gates with other dopants is also useful. It may also be useful to dope the gates of the p-MOS and n-MOS transistors with different types of dopants. Beneath the gate is a gate oxide layer. The gate oxide layer comprises, for example, thermally grown silicon oxide. Other types of gate oxide materials are also useful. In one embodiment, insulating sidewall spacers 428 and 448 are provided on the sides of the p-MOS and n-MOS gates.
Referring to Fig. 5, the process continues by depositing materials for forming nickel-based germanide contacts on the diffusion regions and gates. In one embodiment, a nickel layer 571 is deposited on the substrate. Various techniques can be used to form the nickel layer, such as sputtering, including magnetron sputtering. The nickel layer is sputtered, for example, at a pressure of about 5X10"7 Torr at about room temperature. Other techniques or parameters for forming the nickel layer are also useful . The thickness of the nickel layer is about 5-100 nm. Preferably, the thickness of the nickel layer is less than about 50 nm. Other thicknesses may also be useful . A capping layer 572 is formed over the nickel layer. The capping layer, in one embodiment, comprises a material which inhibits the agglomeration of the nickel germanide layer. In one embodiment, the material of the capping layer is insoluble in the nickel-based contact. In one embodiment, the capping layer comprises Mo, Ta, Ti, W, Zr or a combination thereof. Other materials that can inhibit agglomeration of nickel germanide at processing temperatures are also useful. In another embodiment, the capping layer comprises a material which is soluble in the nickel-based contact, such as Pd and/or Pt. The use of a combination of soluble and insoluble materials in the nickel-based contact to form the capping layer is also useful .
Various techniques can be used to form the capping layer, such as sputtering, including magnetron sputtering. The sputtering, in one embodiment, is performed at room temperature. Other techniques or parameters for forming the capping layer such as thermal and electron-beam evaporation are also useful. The thickness of the capping layer should be sufficient to inhibit agglomeration in the layer at temperatures greater than about 5000C. Preferably, the thickness of the capping layer should be sufficient to inhibit agglomeration in the layer at least up to temperatures of about 7000C. In one embodiment, the thickness of the capping layer should be sufficient to inhibit agglomeration in the layer at temperatures from about 500-7000C. The thickness of the capping layer, for example, is less than or equal to about 50 nm. Preferably, the thickness of the capping layer is about 5 nm.
After the contact layers are formed, the substrate is annealed to form the contacts. The annealing causes the materials of the contact layers and substrate to react, forming nickel-based germanide or nickel-based germanosilicide contacts in substrate areas comprising germanium. For underlying layer of germanium for the contact layers, nickel-based monogermanide contacts are formed while nickel-based germanosilicide contacts are formed for silicon germanium underlying layers. In one embodiment, the annealing comprises a rapid thermal anneal (RTP) . Other types of annealing are also useful. The RTP is performed at a temperature of about 2000C to at least about 7000C for about 1-100 seconds. Preferably, the RTP is performed at a temperature of about 2800C to at least about 5000C. The ambient of the RTP is, for example, nitrogen. Other types of ambients, such as vacuum, He, Ar are also useful . Other types of inert gases can also be used.
Referring to Fig. 6, the contact layers are patterned to leave portions of the contact layers in areas where contacts are formed. In one embodiment, materials of the contact layers are removed from areas 690 and 691 above the STIs and sidewall spacers, leaving the contact layers over the surface of the diffusion regions and gates. The contact layers are patterned by, for example, conventional mask and etch techniques. For example, a photoresist layer is deposited and patterned to expose portions of the layers to be removed, followed by an etch process to remove the layers unprotected by the photoresist layer. In another embodiment, the contact layers are patterned prior to the annealing process for forming the contacts.
In an alternative embodiment, a contact layer comprising nickel-based alloy is deposited over the substrate prepared with the transistors, as described in, for example, Fig. 4. The nickel-based alloy comprises NiY, where Y comprises a material selected from a material which inhibits agglomeration of the contact layer. In one embodiment, Y comprises a material which is insoluble in nickel-based contact. In one embodiment, Y comprises Mo, Ta, Ti, Mo, W, Zr or a combination thereof. Other materials which are insoluble in the nickel-based contact are also useful. In another embodiment, Y comprises a material which is soluble in the nickel-based contact, such as Pd and/or Pt. Providing Y comprising a combination of both soluble and insoluble materials in the nickel-based contact is also useful. The thickness of the nickel-based alloy layer is, for example, about 5-100nm. Preferably, the thickness of the nickel-based alloy layer is less than 50nm.
In one embodiment, the percentage of Y should be sufficient to inhibit agglomeration in the layer at temperatures greater than about 5000C. Preferably, the percentage of Y should be sufficient to inhibit agglomeration in the layer at least up to temperatures of about 7000C. More preferably, the percentage of Y should be sufficient to inhibit agglomeration in the layer at temperatures from about 500-7000C. The percentage of Y, for example, is about 0.1 to 50 atomic percent. Preferably, the percentage of Y is less than about 20 atomic percent . After the nickel-based alloy layer is formed, the process continues to form the contacts by annealing the contact layer. The annealing process, for example, comprises RTP as previously described. Contacts are formed in regions comprising nickel and germanium. In areas where germanium is absent (e.g., above the STI) , no reaction occurs. Unreacted portions of the nickel layer are selectively removed using, for example, a wet etch selective to the reacted portions of the nickel layer. As a result, self-aligned nickel germanide or nickel germanosilicide contacts are formed.
While the invention has been particularly shown and described with reference to various embodiments, it will be recognized by those skilled in the art that modifications and changes may be made to the present invention without departing from the spirit and scope thereof. The scope of the invention should therefore be determined not with reference to the above description but with reference to the appended claims along with their full scope of equivalents.

Claims

What is claimed is:
1. A method of fabricating a contact, the method comprising: providing a substrate comprising at least an active region comprising germanium; depositing a contact layer comprising nickel on the active region; providing a processing material to the contact layer; and processing the substrate to form a nickel-based contact, the processing includes annealing the substrate to cause a reaction to form the nickel-based contact, wherein the processing material inhibits agglomeration of the contact layer during processing.
2. The method of claim 1 wherein the substrate comprises a multi-layered substrate in which a top surface layer comprises germanium or silicon-germanium.
3. The method of claim 1 wherein the substrate comprises germanium or silicon-germanium.
4. The method of any of claims 1-3 wherein the processing material is insoluble in nickel-based contact.
5. The method of claim 4 wherein the processing material comprises Ta, Ti, Mo, W, Zr or a combination thereof.
6. The method of any of claims 1-5 wherein the providing the processing material comprises forming a capping layer over the contact layer.
7. The method of claim 6 wherein the thickness of the capping layer is sufficient to inhibit agglomeration at temperatures of greater than or equal to about 5000C.
8. The method of claim 6 wherein the thickness of the capping layer is sufficient to inhibit agglomeration at temperatures of at least up to about 7000C.
9. The method of claim 6 wherein the thickness of the capping layer is less than or equal to about 50 nm.
10. The method of any of claims 1-5 wherein the providing the processing material comprises integrating the processing material into the step of depositing the contact layer to form a nickel-based alloy contact layer comprising nickel and the processing material.
11. The method of claim 10 wherein the processing material in the nickel-based alloy is less than about 50 atomic percent .
12. The method of claim 10 wherein a percentage of the processing material in the contact layer is sufficient to inhibit agglomeration during processing at temperatures of greater than or equal to about 5000C.
13. The method of claim 10 wherein a percentage of the processing material in the contact layer is sufficient to inhibit agglomeration during processing at temperatures of at least up to about 7000C.
14. The method of any of claims 1-3 wherein the processing material comprises a combination of materials which are soluble and insoluble in the nickel-based contact.
15. The method of any of claims 1-3 wherein the processing material comprises Pt and/or Pd.
16. An integrated circuit comprising: a substrate having at least an active region comprising germanium; a contact coupled to the active region, the contact comprising nickel; and a processing material in contact with the contact, wherein the processing material inhibits agglomeration of the nickel in the contact during processing to form the contact .
PCT/SG2004/000220 2004-07-27 2004-07-27 Reliable contacts Ceased WO2006011851A1 (en)

Priority Applications (6)

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EP04749242A EP1787332A4 (en) 2004-07-27 2004-07-27 RELIABLE CONTACTS
PCT/SG2004/000220 WO2006011851A1 (en) 2004-07-27 2004-07-27 Reliable contacts
JP2007523511A JP2008508713A (en) 2004-07-27 2004-07-27 Reliable contact
CNA200480043680XA CN101032028A (en) 2004-07-27 2004-07-27 reliable contact
US11/572,632 US20070272955A1 (en) 2004-07-27 2004-07-27 Reliable Contacts
TW094124581A TW200605307A (en) 2004-07-27 2005-07-20 Reliable contacts

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214481A (en) * 2006-02-13 2007-08-23 Toshiba Corp Semiconductor device
JP2009060110A (en) * 2007-08-31 2009-03-19 Interuniv Micro Electronica Centrum Vzw Improved method of germanide growth and device obtained thereby
JP2009081159A (en) * 2007-09-25 2009-04-16 Univ Nagoya Germanide thin film, method for producing germanide thin film, germanium structure with germanide thin film
US8354344B2 (en) 2007-08-31 2013-01-15 Imec Methods for forming metal-germanide layers and devices obtained thereby

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101635262B (en) * 2009-08-07 2012-05-30 北京大学 Preparation method of germanium-base schottky transistor
EP2704199B1 (en) 2012-09-03 2020-01-01 IMEC vzw Method of manufacturing a semiconductor device
CN103594518B (en) * 2013-11-08 2016-09-21 清华大学 Metal source-drain structure and forming method thereof

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05326438A (en) * 1992-05-20 1993-12-10 Sony Corp Electrode forming method
US20020042197A1 (en) * 2000-03-06 2002-04-11 International Business Machines Corporation Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
JP2002261044A (en) * 2001-03-06 2002-09-13 Sony Corp Semiconductor device manufacturing method and semiconductor device
US20020168809A1 (en) * 2001-05-08 2002-11-14 Boutros Karim S. Semiconductor circuits and devices on germanium substrates
WO2003012876A1 (en) * 2001-07-31 2003-02-13 Institute Of Materials Research And Engineering Gate electrodes and the formation thereof
US6703291B1 (en) * 2002-12-17 2004-03-09 Intel Corporation Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions
US20040061191A1 (en) * 2002-09-30 2004-04-01 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods for their formation
EP1422755A2 (en) * 2002-11-21 2004-05-26 Texas Instruments Incorporated Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound
US20040123922A1 (en) 2002-12-31 2004-07-01 Cyril Cabral Retarding agglomeration of Ni monosilicide using Ni alloys

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4310570A (en) * 1979-12-20 1982-01-12 Eaton Corporation Field-effect transistors with micron and submicron gate lengths
SG97821A1 (en) * 1999-11-17 2003-08-20 Inst Materials Research & Eng A method of fabricating semiconductor structures and a semiconductor structure formed thereby
US6214679B1 (en) * 1999-12-30 2001-04-10 Intel Corporation Cobalt salicidation method on a silicon germanium film
US6506637B2 (en) * 2001-03-23 2003-01-14 Sharp Laboratories Of America, Inc. Method to form thermally stable nickel germanosilicide on SiGe
US20090004850A1 (en) * 2001-07-25 2009-01-01 Seshadri Ganguli Process for forming cobalt and cobalt silicide materials in tungsten contact applications
US6746967B2 (en) * 2002-09-30 2004-06-08 Intel Corporation Etching metal using sonication
KR100870176B1 (en) * 2003-06-27 2008-11-25 삼성전자주식회사 Nickel alloy salicide process, method for manufacturing a semiconductor device using the same, nickel alloy silicide film formed thereby and a semiconductor device manufactured using the same
US6909186B2 (en) * 2003-05-01 2005-06-21 International Business Machines Corporation High performance FET devices and methods therefor
US7449782B2 (en) * 2004-05-04 2008-11-11 International Business Machines Corporation Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby
US7053400B2 (en) * 2004-05-05 2006-05-30 Advanced Micro Devices, Inc. Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05326438A (en) * 1992-05-20 1993-12-10 Sony Corp Electrode forming method
US20020042197A1 (en) * 2000-03-06 2002-04-11 International Business Machines Corporation Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy
JP2002261044A (en) * 2001-03-06 2002-09-13 Sony Corp Semiconductor device manufacturing method and semiconductor device
US20020168809A1 (en) * 2001-05-08 2002-11-14 Boutros Karim S. Semiconductor circuits and devices on germanium substrates
WO2003012876A1 (en) * 2001-07-31 2003-02-13 Institute Of Materials Research And Engineering Gate electrodes and the formation thereof
US20040061191A1 (en) * 2002-09-30 2004-04-01 Advanced Micro Devices, Inc. Mosfets incorporating nickel germanosilicided gate and methods for their formation
EP1422755A2 (en) * 2002-11-21 2004-05-26 Texas Instruments Incorporated Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound
US6703291B1 (en) * 2002-12-17 2004-03-09 Intel Corporation Selective NiGe wet etch for transistors with Ge body and/or Ge source/drain extensions
US20040123922A1 (en) 2002-12-31 2004-07-01 Cyril Cabral Retarding agglomeration of Ni monosilicide using Ni alloys

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN *
See also references of EP1787332A4

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214481A (en) * 2006-02-13 2007-08-23 Toshiba Corp Semiconductor device
JP2009060110A (en) * 2007-08-31 2009-03-19 Interuniv Micro Electronica Centrum Vzw Improved method of germanide growth and device obtained thereby
EP2031644A3 (en) * 2007-08-31 2012-01-25 Imec Method for improving germanide growth and devices obtained thereof
US8354344B2 (en) 2007-08-31 2013-01-15 Imec Methods for forming metal-germanide layers and devices obtained thereby
JP2009081159A (en) * 2007-09-25 2009-04-16 Univ Nagoya Germanide thin film, method for producing germanide thin film, germanium structure with germanide thin film

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US20070272955A1 (en) 2007-11-29
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TW200605307A (en) 2006-02-01
JP2008508713A (en) 2008-03-21
CN101032028A (en) 2007-09-05

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