WO2006067280A1 - Conductive pattern, circuit board and their production method - Google Patents

Conductive pattern, circuit board and their production method Download PDF

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Publication number
WO2006067280A1
WO2006067280A1 PCT/FI2005/050466 FI2005050466W WO2006067280A1 WO 2006067280 A1 WO2006067280 A1 WO 2006067280A1 FI 2005050466 W FI2005050466 W FI 2005050466W WO 2006067280 A1 WO2006067280 A1 WO 2006067280A1
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WO
WIPO (PCT)
Prior art keywords
layer
conductive pattern
circuit board
forming
auxiliary substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/FI2005/050466
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French (fr)
Inventor
Juha Hagberg
Seppo LEPPÄVUORI
Teija Kekonen
Janne Mettovaara
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Aspocomp Technology Oy
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Aspocomp Technology Oy
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Publication of WO2006067280A1 publication Critical patent/WO2006067280A1/en
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Ceased legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0284Details of three-dimensional rigid printed circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H05K1/186Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H05K1/187Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards manufactured by mounting on or connecting to patterned circuits before or during embedding the patterned circuits being prefabricated circuits, which are not yet attached to a permanent insulating substrate, e.g. on a temporary carrier
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09009Substrate related
    • H05K2201/09118Moulded substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Definitions

  • the invention relates to a conductive pattern, a circuit board and to a method of producing them for electronic circuits.
  • Circuit boards provided with either rigid or flexible copper laminate are employed in electronics.
  • the copper film of a copper laminate can be formed using electrodeposition or rolling, and the copper laminate can be formed by attaching the copper film to a suitable insulating circuit board mate- rial.
  • a circuit board is produced in two steps: in the first step, a copper laminate is produced, and in the second step, conductors are patterned on the copper surface of the circuit board.
  • the actual production of the conductive pattern on the circuit board surface can be carried out as follows, for example.
  • a copper film is coated with a photosensitive material, which is generally called a photoresist.
  • the conductive pattern to be produced is exposed on the surface of the photoresist.
  • a protective layer of the photoresist remains in the areas where conductors are to be formed, and the photoresist is removed from the other areas.
  • the copper laminate patterned with the photoresist is immersed in a suitable copper etchant. In that case, the unprotected copper is etched, and only the conductive pattern protected with the photoresist remains on the circuit board surface. Finally, the used photoresist is also removed.
  • pattern plating is frequently also used as a sub-process, where the surface patterned with a resist is coated, i.e. pattern plated, electrolytically with copper.
  • conductive patterns are formed on the circuit board surface by pattern plating, the conductive pattern will vary in height. This results from deposition geometry: the current density varies in different parts of the pattern.
  • electrolytic metallization of through holes and vias is often very difficult, if not impossible altogether, because there is no uniform metal film on the circuit board surface that could be used for supplying electric current to metallize a through-hole.
  • transfer methods do not allow the use of a copper film as an auxiliary substrate.
  • Prob- lems are also posed by the recyclability, environment friendliness and health hazards of the materials used.
  • An advantage of copper electrodeposition over chemical (electroless) deposition is its quickness and good quality of metals.
  • An object of the invention is to provide an improved produc- tion method and an improved circuit board. This is achieved by a method of producing a conduction pattern.
  • the method comprises forming a separating layer on an auxiliary substrate, where at least the surface is conductive, forming a patterned resist layer on the separating layer, electrodepositing a patterned resist layer on the separating layer, electrodepositing a conductive pat- tern on the separating layer in openings in the patterns of the resist layer, at least the auxiliary substrate being removable from the layer structure formed.
  • the invention also relates to a method of producing a conductive pattern.
  • the method comprises forming a patterned resist layer on an auxiliary substrate, where at least the surface is conductive, forming a separat- ing layer on the auxiliary substrate in openings in the patterns of the resist layer, electrodepositing a conductive pattern on the separating layer in the openings in the patterns of the resist layer, at least the auxiliary substrate being removable from the layer structure formed.
  • the invention also relates to a method of producing a circuit board.
  • the method employs at least one auxiliary substrate with a conductive surface, the method comprising forming at least one separating layer on each auxiliary substrate, forming a patterned resist layer on each separating layer, electrodepositing a conductive pattern on each separating layer in openings in the patterns of the resist layer, embedding and attaching the at least one con- ductive pattern to electricity insulating material, and removing at least the auxiliary substrate from the rest of the layer structure.
  • the invention also relates to a method of producing a circuit board.
  • the method employs at least one auxiliary substrate with a conductive surface, the method comprising forming a patterned resist layer on each auxil- iary substrate, forming at least one separating layer on each auxiliary substrate in openings in the patterns of the resist layer, electrodepositing a conductive pattern on each separating layer in the openings in the patterns of the resist layer, embedding and attaching the at least one conductive pattern to electricity insulating material, and removing at least the auxiliary substrate from the rest of the layer structure.
  • the invention also relates to a circuit board.
  • the circuit board has a layered structure and the circuit board has been formed using in the production at least one auxiliary substrate with a conductive surface, on which at least one separating layer has been formed, and the circuit board comprises at least one conductive pattern produced by forming a patterned resist layer on each separating layer, by electrodepositing a conductive pattern on each separating layer in openings in the patterns of the resist layer, and the circuit board has been formed by embedding and attaching the at least one conductive pattern to electricity insulating material and by removing at least the auxiliary sub- strate from the rest of the layer structure.
  • the invention also relates to a circuit board.
  • the circuit board has a layered structure and the circuit board has been formed using in the production at least one auxiliary substrate with a conductive surface, and the conductive pattern has been produced by forming a patterned resist layer on each auxiliary substrate, by forming at least one separating layer in openings in the patterns of the resist layer, by electrodepositing a conductive pattern on each separating layer in the openings in the patterns of the resist layer, and the circuit board has been formed by embedding and attaching the at least one conductive pattern to electricity insulating material and by removing at least each auxiliary substrate from the rest of the layer structure.
  • the invention also relates to a conductive pattern.
  • the conductive pattern has been formed by using in the production at least one auxiliary substrate with a conductive surface, on which at least one separating layer has been formed, and each circuit board comprises at least one conductive pattern produced by forming and patterning a resist layer on the separating layer, by electrodepositing a conductive pattern on the separating layer in openings in the patterns of the resist layer, each auxiliary substrate being removable from the layer structure formed.
  • the invention also relates to a conductive pattern.
  • the conductive pattern has been formed by using in the production at least one auxil- iary substrate with a conductive surface, on which a patterned resist layer has been formed, and the conductive pattern has been produced by forming a separating layer on each auxiliary substrate in openings in the patterns of the resist layer, by electrodepositing growing a conductive pattern on the separating layer in the openings in the patterns of the resist layer, each auxiliary sub- strate being removable from the layer structure formed.
  • the method and system according to the invention provide several advantages.
  • the conductor cross section is rectangular and no lateral under etching occurs. Consequently, conductors and spaces between conductors can be provided with a high dimensional accuracy.
  • Copper or copper-coated plastic can be used as the auxiliary substrate and intermediate layer, both copper and plastic being easily recycla- ble materials.
  • the production process requires less corroding materials and materials that are poisonous and hazardous to the environment and humans, which reduces the need for post-processing of these materials and the costs resulting from post-processing. LIST OF FIGURES
  • Figure 1A illustrates a layer structure comprising a temporary auxiliary substrate, a separating layer and a conductive pattern
  • Figure 1 B illustrates another kind of layer structure comprising a temporary auxiliary substrate, a separating layer and a conductive pattern
  • Figure 2A illustrates a pre-form for a one-sided circuit board
  • Figure 2B illustrates a one-sided circuit board
  • Figure 2C illustrates attachment of circuit board material to a conductive pattern as a continuous process
  • Figure 3 illustrates a two-sided circuit board provided with through- holes
  • Figure 4 illustrates an "any layer microvia" circuit board
  • Figures 5A and 5B illustrate a two-sided 2.5D circuit board, where the upper side and the lower side have been connected to each other electrically by a fold in the circuit board,
  • Figure 6 illustrates an L-shaped 2.5D circuit board
  • Figure 7A illustrates production of a 3D circuit board between the jaws of a hot press
  • Figure 7B illustrates production of a 3D circuit board in a mould
  • Figure 7C illustrates a 3D circuit board
  • Figures 8A to 8C illustrate embedding of a deposited/printed com- ponent in a circuit board
  • Figures 9A to 9E illustrate embedding of a component in a circuit board
  • Figures 10A to 10E illustrate embedding of a component in a circuit board
  • Figure 1 1 illustrates production of a conductive pattern as a continuous process
  • Figure 12 illustrates a production method of a conductive pattern as a flowchart
  • Figure 13 illustrates a production method of a conductive pattern as a flowchart
  • Figure 14 illustrates a production method of a circuit board as a flow chart
  • Figure 15 illustrates a production method of a circuit board as a flow chart.
  • Figure 1A illustrates a conductive pattern 100 on an intermediate layer 102.
  • the conductive pattern 100 can be deposited on a separating layer 101 included in the layer structure.
  • the separating layer 101 may comprise both an intermediate layer 102 and a release layer 104, but the separating layer 101 may also be a mere release layer 104.
  • the layer structure further comprises an auxiliary substrate 106.
  • the separating layer 101 is coated with a patterned resist 108. In that case, either the intermediate layer 102 or the release layer 104 is coated with a resist.
  • the conductive pattern is electrodeposited in openings in the resist 108.
  • the conductive pattern 100 together with the optional intermediate layer 102 can be removed from the auxiliary substrate 106 by means of the release layer 104.
  • Figure 1 B illustrates an alternative way of producing a con- ductive pattern.
  • a patterned resist layer 108 is formed on the auxiliary substrate 106, where at least the surface is conductive.
  • the release layer 104 is formed on the auxiliary substrate 106 in openings in the patterns of the resist layer 108.
  • the conductive pattern 100 is electrodeposited on the release layer 104 in the openings in the patterns of the resist layer 108.
  • at least the auxiliary substrate 106 is removable from the layer structure formed.
  • the intermediate layer 102 between layers 100 and 104) can be used to level out any non-homogeneities in the auxiliary substrate.
  • the temporary auxiliary substrate 106 may be totally conductive or only its surface. Even though the intermediate layer 102 is not necessarily needed in the solution described, the intermediate layer 102 may be employed to level out any non-homogeneity in the auxiliary substrate, to function as a current transmission layer in the metallization of vias and/or to facilitate the removal of the auxiliary substrate 106 and/or any bonded components.
  • the intermediate layer 102 can be omitted, for example, in a case where the adhesion of the circuit board material to be attached to the auxiliary substrate or to the auxiliary substrate 106 coated with a release layer 104 is so small that the circuit board material and the auxiliary substrate 106 can be reliably removed from each other.
  • the auxiliary substrate 106 may be made of metal, such as stainless steel, titan, nickel, aluminium or copper or of their combination in the form of a rigid plate, a three-dimensional shape, or a film-like or rollable ribbon.
  • a metal-coated plastic board or film, such as a copper-coated plastic film in the form of a rollable ribbon, may also be used as the auxiliary substrate 106 since the auxiliary substrate needs to be conductive.
  • PET polyethylene terephtha- late
  • the thickness of the auxiliary substrate 106 may range from less than 15 ⁇ m to several millimetres.
  • the lower limit is restricted by the mechanical processability of the auxil- iary substrate 106 and the upper limit by processability and cost factors.
  • the auxiliary substrate may be used several times or it may be disposable.
  • a disposable auxiliary substrate 106 may be made of copper ribbon or copper- coated plastic film, both of which are easily recyclable materials.
  • the release layer 104 between the auxiliary substrate 106 and the intermediate layer 102 or between the auxiliary substrate 106 and the conductive pattern 100 may be made of metals or other organic substances without being limited to these.
  • the metal in the release layer 104 may be nickel and/or chrome, for example, with which the auxiliary substrate 106 is coated electrolytically.
  • the thickness of a metal release layer 104 is typically 1 to 100 nm. If a very thin release layer 104 is used, release cannot be performed reliably. The use of a very thick release layer 104, on the other hand, is not reasonable in the economic sense or in view of recycling.
  • An organic release layer 104 may be made of carboxyben- zotriazole, for instance.
  • the substance of the release layer may be dissolved into water or solvent, where the auxiliary substrate 106 is kept for a certain time.
  • a typical thickness of the organic release layer 104 is approximately 1 to 100 nm.
  • An intermediate layer 102 may be electrodeposited on the release layer 104.
  • the intermediate layer 102 may be made of copper, for ex- ample, having a typical thickness of 0.5 to 7 ⁇ m. The thinner the intermediate layer 102 used, the easier its removal usually is.
  • the separating layer 101 is coated with a patterned resist 108. In the patterning, it is feasible to use a patterned photoresist, for example. The patterning of a resist 108 is known per se. The patterned resist 108 can also be layered onto an underlying layer by printing. The surface of the inter- mediate layer 102 or auxiliary substrate 106 can be roughened to improve adhesion to the resist 108.
  • Conductive patterns 100 with a desired thickness, typically 3 to 50 ⁇ m, are deposited on the separating layer 101 in the openings in the resist 108. Also thinner or thicker conductors can be deposited.
  • the conductors 100 can be roughened by known techniques to provide a better adhesion to the insulating circuit board material.
  • the conductors need not be deposited from one material but they may consist of several different metal layers. For example, gold can be deposited as the lowest layer, on top of which nickel and copper layers are deposited. In a completed circuit board having this kind of layer structure, compo- nents may be contacted to the gold layer, which is often necessary with respect to contacting.
  • Figure 2A illustrates a one-sided circuit board pre-form, which may be produced by attaching electricity insulating circuit board material 200 to the layer structure.
  • the layer structure comprises as superimposed layers a temporary auxiliary substrate 106, a separating layer 101 and a conductive pattern 100, which is optionally treated with adhesive.
  • the layer structure may also include a resist 108, but this is not necessary.
  • the electricity insulat- ing material 200 may be, for example, hardening epoxy, thermoplastic plastic or disposable plastic. Typical circuit board epoxy is curdled and hardened by increasing the temperature to a suitable temperature at a certain speed. Thermoplastic plastic softens when it is heated and hardens when cooled.
  • the circuit board material 200 may be nearly any electricity insulating material that can be provided with a sufficiently fluid form for embedding conductive patterns in it. Furthermore, the circuit board material 200 has to re-harden after this. Inside the circuit board material 200, it is feasible to use structures and additives that stiffen the circuit board, affect the thermal properties and/or electric properties, such as mats or fibres made of glass fibre or Teflon, or ceramic powder, or their combinations. [0034] After the layer structure, which comprises a temporary auxiliary substrate 106, a release layer 104, an optional intermediate layer 102 and a conductive pattern 100 (and possibly also a resist 108), has been attached to the circuit board material 200, the auxiliary substrate 106 is removed from the separating layer 101.
  • Circuit board ribbon 222 is fed from a circuit board roll 220 into a laminator 224, into which conductive pattern ribbons 230, 232 are also fed from two conductive pattern rolls 226, 228, the ribbons comprising an auxiliary substrate, a separating layer and a conductive pattern.
  • the laminator 224 which may comprise two rolls 234, 236, for example, presses the conductive pattern ribbons 230, 232 onto different sides of the circuit board ribbon 222 by means of increased temperature, for example, if the circuit board ribbon 222 is made of thermoplastic material.
  • the two- sided circuit board pre-form 238 can be rolled up into a roll 240.
  • a two-sided circuit board may be produced in the same manner as the one-sided circuit board.
  • a layer structure is attached to both sides of insulating circuit board material 200 so that the conductive pattern 100 faces the insulating circuit board material 200.
  • Conductive patterns 100 on both sides of the board can be connected to each other through through-holes or microvias 300.
  • Vias can be formed by laser drilling and using circuit board processes known per se to metallize a via and optionally fill it.
  • an intermediate layer may be employed in the transfer of electricity.
  • FIG 4 illustrates a multi-layer circuit board.
  • Multi-layer cir- cuit boards may be produced by connecting two or more one-sided or two- sided circuit boards produced by the process according to the presented solu- tion or by piling circuit boards one on top of another or by combining both of these methods.
  • it is also feasible to produce "any layer microvia" circuit boards where the micro through-hole 300 may go through the circuit board material 400 to 404 in any layer and micro through-holes may be superimposed.
  • Figures 5A and 5B illustrate a two-sided circuit board which may be produced by folding a layer structure comprising a temporary auxiliary substrate 106, a separating layer 101 and a conductive pattern 100 (optionally with resists 108) to cover both sides of the insulating circuit board material 200.
  • the conductive pattern 100 may be adhesion treated.
  • the upper and lower sides of the circuit board are contacted to each other by a fold 500.
  • the fold may be on one or several sides of the circuit board 200.
  • the presented solution enables production of two-and-half- dimensional or three-dimensional conductive patterns (2.5D or 3D conductive patterns).
  • a 2.5D conductive pattern may be formed on a 2D circuit board, as illustrated in Figures 5A and 5B.
  • the 2.5D shape refers to a shape achieved by folding a planar pattern.
  • Structures having the 2.5 shape are easy to produce by providing the circuit board 200 with an L-shaped cross section, for example, as illustrated in Figure 6.
  • the conductive pattern 100 is on the inner surface of the circuit board 200, but it may naturally also be arranged on the outer surface or alternatively on both surfaces, which are optionally connected by a fold extending across the circuit board edge or by through-holes.
  • a circuit board with a three-dimensional shape may be produced as follows, for example.
  • the layer structure may be provided with the 3D shape using pressure and heat or other known shaping methods, such as hot pressing, pressure shaping or high speed shaping. These shaping meth- ods are material-dependent.
  • the conductive patterns may be adhesion treated to improve adhesion to the electricity insulating material where the conductive pattern is embedded.
  • Figures 7A to 7C illustrate solutions where the layer structure 716 has been folded into a spherical calotte.
  • the layer structure 716 can be placed in a hot press together with the insulating material 200 to be attached thereto.
  • the jaws 702, 704 of the hot press have been provided with the same 3D shape.
  • the insulating material 200 is attached to the conductive pattern on the auxiliary substrate by pressing them between the jaws 702, 704 of the hot press.
  • the circuit board material functioning as the insulating material may also be provided with the 3D shape before hot pressing.
  • Figure 7B illustrates a layer structure 716 folded into the shape of a spherical calotte in the casting space 712 of an injection moulding die.
  • the layer structure 716 provided with the 3D shape forms part of the die.
  • Injection moulding can be performed through a casting conduit 714.
  • the conductive pattern on the layer structure attaches onto one or both surfaces of the injection moulded product.
  • pre-forming of the 3D shape is not always necessary, but forming may be carried out during pressing or casting.
  • Figure 7C illustrates a cross section of a final 3D circuit board 710 with the shape of a spherical calotte.
  • Components may be embedded in a circuit board together with conductive patterns by attaching components onto the conductive pattern or by forming components onto the intermediate layer before the conductive pattern is produced or after the conductive pattern has been produced.
  • conductive patterns by attaching components onto the conductive pattern or by forming components onto the intermediate layer before the conductive pattern is produced or after the conductive pattern has been produced.
  • different ways of forming a component and a conductive pattern and of embedding them in a circuit board will be described in greater detail.
  • Figures 8A to 8C illustrate examples of solutions where components are formed onto the conductive pattern (or under the conductive pattern).
  • Figure 8A illustrates a solution where at least one component 800, such as a resistor, may be electrodeposited on the conductive pattern 100 and the intermediate layer 102 in the openings in the resist pattern 108 (broken line). Alternatively, the component may be pressed onto the conductive pattern 100 and separating layer 101 by a screen printing method, for example, in which case no resist pattern is needed.
  • a component 800 such as a resistor
  • Figure 8B illustrates a production method where a component 800, such as a resistor, is first printed onto the separating layer 101 by a screen printing, for example. Thereafter, a conductive pattern 100 is formed on the component 800 and the separating layer 101 in the openings in the resist pattern.
  • the component can be first formed by electrodepositing it on the separating layer 101 in the openings in the resist pattern (broken line), after which the resist pattern can be removed. Thereafter, the conductive pattern 100 may be electrodeposited on the component 800 and the separating layer 101 in the openings in the resist pattern 108.
  • Figure 8C illustrates a final circuit board 850 where the component 800 has been embedded.
  • the component can be printed onto the conductive pattern 100 in the separating layer 101 or the component may be electrodeposited on the conductive pattern 100 and the separating layer 101 in the openings in the resist pattern. After insulating material 200 has been attached, the auxiliary substrate is removed and the intermediate layer etched.
  • leaded or bumped components and semiconductor chips attached to a conductive pattern are embeddable.
  • a connection may be made conductive using conductive adhesive or a solder joint in attachment.
  • the component may be, for example, a leaded surface mounting component, a leaded or a bumbed module or a flip chip.
  • it may be necessary to provide the circuit board material with a cavity or an opening at the component before attaching the circuit board material.
  • the component may also be protected with plastic encapsulation before attachment of the circuit board material.
  • Figure 9A illustrates a bumped component 900 whose bumps 902 are attached to the conductive pattern 100 functioning as the uppermost layer in the layer structure comprising the auxiliary substrate 106 and the separating layer 101 using an adhesive or a solder joint 904. Thereafter, the lower side of the component may be filled with an "underfill agent" 906, as shown in Figure 9B. This provides the final circuit board with an even surface. The component together with the conductive pattern 100 and any underfill agent 906 is attached to the circuit board material 200 as in Figure 9C.
  • the component 900 area in the circuit board material 200 may be provided with an opening 908, which may be filled with another material 910, as illustrated in Figure 9D.
  • the opening may be filled, for example, with plastic which has been hardened chemically, by heat or ultraviolet.
  • Attachment of the component 900 may be carried out by electrodepositing copper on the conductive pattern 100 over the component 900 leg or bonding area, as illustrated in Figures 10A to 10E, where the layer 1 14 may comprise either a release layer 104 or an intermediate layer 102.
  • the layer 114 may also comprise both a release layer 104 and an intermediate layer 102 or sections of them.
  • a component or a semiconductor chip 900 ac- cording to Figure 10 A is attached by adhesive 910 to the conductive pattern 100, which is provided with openings 912 at the bonding areas of the component or the semiconductor chip 900.
  • the adhesive may be conductive.
  • the lower side of the component 900 may be filled with an "underfill agent" 906, which provides the final circuit board with an even surface.
  • the same substance may be used both as the adhesive 910 and as the underfill agent 906, in which case the adhesion of the semiconductor chip and the underfill process can be performed in one and the same process step.
  • the circuit board material 200 may be provided with an opening, which may be filled with another material in the same way as described above in connection with Figure 9D.
  • the component 900 may be attached to the circuit board material 200 together with the conductive pattern 100 and any underfill agent 906.
  • the auxiliary substrate is removed and openings 920 are formed in the layer 1 14 by laser machining, for example, at the bonding areas, bumps or legs 950 of the component. Remaining adhesive can also be removed by laser machining. Then an electric contact is formed between the component 900 leg 950 and the conductive pattern 100 using, for example, chemical or electrolytic coppering or their combination.
  • the intermediate layer 102 may, before contacting, be covered with a patterned resist 922 to avoid depositing copper 924 on the whole sample area.
  • a completed circuit board 1000 which may be a printed circuit board, with embedded components is obtained when any resist is removed and the layer 1 14 etched, as illustrated in Figure 10E.
  • the component/components and/or semiconductor chips may naturally be embedded in a single-layer circuit board or in different layers of a multi-layer circuit board.
  • the component/components and/or semiconductor chips may naturally also be embedded in 2.5D and 3D structures.
  • FIG 11 illustrates a "from a roll to a roll” process where a layer structure including a conductive pattern can be produced as a continuous process.
  • auxiliary substrate ribbon is fed from a roll 1100 to another roll 1102.
  • a release layer 104 is formed on a conductive auxiliary sub- strate 106 by means 1104 for producing a release layer.
  • the conductive auxiliary substrate may be made of copper or provided with a copper surface.
  • An intermediate layer 102 is formed on the release layer 104 by means 1106 for producing an intermediate layer.
  • Resist spreading means 1108 are used for forming a patterned resist layer 108 on the intermediate layer 102.
  • a conduc- five pattern 100 is electrodeposited on the intermediate layer 102 in openings in the resist layer 108 by means 1110 for producing a conductive pattern.
  • Figure 12 is a flow chart illustrating a method of producing a conductive pattern.
  • a separating layer 101 is formed on an auxiliary substrate 106, where at least the surface is conductive.
  • a patterned resist layer 108 is formed on the separating layer 101.
  • a conductive pattern 100 is electrodeposited on the separating layer 101 in openings in the patterns of the resist layer 108.
  • Figure 13 is also a flow chart illustrating a method of producing a conductive pattern.
  • a patterned resist layer 108 is formed , on an auxiliary substrate 106, where at least the surface is conductive.
  • a separating layer 101 is formed on the auxiliary substrate 106 in openings in the patterns of the resist layer 108.
  • a conductive pattern 100 is electrodeposited on the separating layer 101 in the openings in the pattern of the resist layer 108.
  • Figure 14 illustrates a production method of a circuit board.
  • the method employs at least one auxiliary substrate 106 with a conductive surface.
  • step 1400 at least one separating layer 101 is formed on each aux- iliary substrate 106.
  • step 1402 a patterned resist layer 108 is formed on each separating layer 101.
  • step 1404 a conductive pattern 100 is electro- deposited on each separating layer 101 in openings in the patterns of the resist layer 108.
  • step 1406 the at least one conductive pattern is embedded and attached to electricity insulating material 200.
  • the auxiliary substrate 106 is mechanically removed from the rest of the layer structure.
  • Figure 15 also illustrates a production method of a circuit board. The method employs at least one auxiliary substrate 106 with a conductive surface.
  • a patterned resist layer 108 is formed on each auxiliary substrate 106.
  • at least one separating layer 101 is formed on each auxiliary substrate 106 in openings in the patterns of the resist layer 108.
  • a conductive pattern 100 is electrodeposited on each separating layer 101 in the openings in the patterns of the resist layer 108.
  • the at least one conductive pattern 100 is embedded and attached to electricity insulating material 200.
  • the auxiliary substrate 106 is mechanically removed from the rest of the layer structure.
  • a copper film with a thickness of 100 ⁇ m is coated in an electrolytic bath with a release layer having a thickness of 20 nm using the Atotech Trichrome plus electrolysis bath. Thereafter, the sample is rinsed and an intermediate layer of copper is deposited on it using the Atotech Cupracid BL-CT bath with a current density of 1.5 A/dm 2 . The average thickness of the deposited layer may be 3.5 ⁇ m. Thereafter, the surface of the deposited thin copper layer may be microetched and coated with a negative dry film resist with a thickness of 38 ⁇ m, which is patterned with the desired pattern.
  • a conductive pattern may be deposited in the openings in the resist pattern using the Atotech Cuparic Acid BL-CT bath with a current density of 1.5 A/dm 2 .
  • the average thickness of the conductive pattern may be 25 ⁇ m.
  • the upper surface of the conductive pattern may be roughened in an acid micro- etch and the resist removed.
  • the conductive pattern thus produced can be pressed together with Hitachi GEA 67 b-state epoxy in a vacuum press at a pressure of 15 bar by increasing the temperature 6°C/min up to 19O 0 C, which final temperature may be maintained for one hour. After the sample has cooled down, the copper film used as a temporary deposition substrate can be re- moved from the sample surface by pulling.
  • the chrome film which is seen as a layer darker than the copper layer, is removed with the temporary deposition substrate. Thereafter, the thin copper intermediate layer on the sample surface can be etched off.
  • the final result will be a one-sided circuit board whose surface is in one plane and where the conductors are embedded in the circuit board material.
  • a copper film with a thickness of 100 ⁇ m is coated in an electrolytic bath with a release layer having a thickness of 20 nm using the Atotech Trichrome plus electrolysis bath. Thereafter, the sam- pie is rinsed and an intermediate layer of copper is deposited on it using the Atotech Cupracid BL-CT bath with a current density of 1.5 A/dm 2 . The average thickness of the deposited layer may be 1 ⁇ m. Thereafter, an AZ4562 resist may be spread on the thin copper layer and patterned with the desired pattern. A conductive pattern may be deposited in the openings in the resist pattern using the Atotech Cuparic Acid BL-CT bath with a current density of 1.5 A/dm 2 .
  • This provides a conductive pattern with an average thickness of 9 ⁇ m.
  • the upper surface of the conductive pattern may be roughened in an acid micro- etch and the resist removed.
  • the conductive pattern thus produced can be pressed together with Hitachi GEA 67 b-state epoxy in a vacuum press at a pressure of 15 bar by increasing the temperature 6°C/min up to 19O 0 C, which final temperature may be maintained for one hour.
  • the copper film used as a temporary deposition substrate can be removed from the sample surface by pulling. It can also be visually noted that the chrome film, which is seen as a layer darker than the copper layer, is removed with the temporary deposition substrate. Thereafter, the thin copper intermediate layer on the sample surface can be etched.
  • the final result will be a onesided circuit board whose surface is in one plane and where the conductors are embedded in the circuit board material. Even narrow conductors and conductor spaces (for example 6 ⁇ m) can be formed reliably. [0065] Material combinations other than the ones used in the examples described may also be employed.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

A conductive pattern (100) is electrodeposited on a separating layer (101 ) in openings in a patterned photoresist (108). The conductive pattern (100) is removable from an auxiliary substrate (106) by means of the separating layer (101 ). The conductive pattern (100) may be used in producing a circuit board, and components may be embedded in the circuit board.

Description

CONDUCTIVE PATTERN, CIRCUIT BOARD AND THEIR PRODUCTION METHOD
FIELD
[0001] The invention relates to a conductive pattern, a circuit board and to a method of producing them for electronic circuits.
BACKGROUND
[0002] Circuit boards provided with either rigid or flexible copper laminate are employed in electronics. The copper film of a copper laminate can be formed using electrodeposition or rolling, and the copper laminate can be formed by attaching the copper film to a suitable insulating circuit board mate- rial.
[0003] Conventionally, a circuit board is produced in two steps: in the first step, a copper laminate is produced, and in the second step, conductors are patterned on the copper surface of the circuit board.
[0004] The actual production of the conductive pattern on the circuit board surface can be carried out as follows, for example. A copper film is coated with a photosensitive material, which is generally called a photoresist. The conductive pattern to be produced is exposed on the surface of the photoresist. After the exposure and development have been performed, a protective layer of the photoresist remains in the areas where conductors are to be formed, and the photoresist is removed from the other areas. Then the copper laminate patterned with the photoresist is immersed in a suitable copper etchant. In that case, the unprotected copper is etched, and only the conductive pattern protected with the photoresist remains on the circuit board surface. Finally, the used photoresist is also removed. [0005] In the production of a circuit board, pattern plating is frequently also used as a sub-process, where the surface patterned with a resist is coated, i.e. pattern plated, electrolytically with copper.
[0006] Electronic components and flip chips are usually assembled onto the circuit board surface and attached thereto electrically by a solder or adhesive joint.
[0007] As the packaging density has increased, components are more and more frequently embedded inside circuit boards. Several prior art methods are known for embedding ceramic or polymeric thick-film resistors, deposited or "pattern-etched" thin-film resistors, or semiconductor chips inside a circuit board. [0008] Pattern transfer methods are also known where a conductive pattern is first deposited or etched on the surface of a temporary auxiliary substrate, from which the conductive pattern is transferred onto the final circuit board material. [0009] The prior art methods involve several disadvantages. If circuit board conductors are produced by etching, the copper film patterned with the resist limits the accuracy of the resulting conductive pattern, known as "lateral under etching", because etching also proceeds in the horizontal direction when wet etching is used. For this reason, the cross section of the etched con- ductor will be a trapezoid. This shape restricts resolution and hinders the use of high frequencies, for instance.
[0010] If conductive patterns are formed on the circuit board surface by pattern plating, the conductive pattern will vary in height. This results from deposition geometry: the current density varies in different parts of the pattern. [0011] In transfer methods, electrolytic metallization of through holes and vias is often very difficult, if not impossible altogether, because there is no uniform metal film on the circuit board surface that could be used for supplying electric current to metallize a through-hole. Furthermore, many transfer methods do not allow the use of a copper film as an auxiliary substrate. Prob- lems are also posed by the recyclability, environment friendliness and health hazards of the materials used. An advantage of copper electrodeposition over chemical (electroless) deposition is its quickness and good quality of metals.
BRIEF DESCRIPTION
[0012] An object of the invention is to provide an improved produc- tion method and an improved circuit board. This is achieved by a method of producing a conduction pattern. The method comprises forming a separating layer on an auxiliary substrate, where at least the surface is conductive, forming a patterned resist layer on the separating layer, electrodepositing a patterned resist layer on the separating layer, electrodepositing a conductive pat- tern on the separating layer in openings in the patterns of the resist layer, at least the auxiliary substrate being removable from the layer structure formed.
[0013] The invention also relates to a method of producing a conductive pattern. The method comprises forming a patterned resist layer on an auxiliary substrate, where at least the surface is conductive, forming a separat- ing layer on the auxiliary substrate in openings in the patterns of the resist layer, electrodepositing a conductive pattern on the separating layer in the openings in the patterns of the resist layer, at least the auxiliary substrate being removable from the layer structure formed.
[0014] The invention also relates to a method of producing a circuit board. The method employs at least one auxiliary substrate with a conductive surface, the method comprising forming at least one separating layer on each auxiliary substrate, forming a patterned resist layer on each separating layer, electrodepositing a conductive pattern on each separating layer in openings in the patterns of the resist layer, embedding and attaching the at least one con- ductive pattern to electricity insulating material, and removing at least the auxiliary substrate from the rest of the layer structure.
[0015] The invention also relates to a method of producing a circuit board. The method employs at least one auxiliary substrate with a conductive surface, the method comprising forming a patterned resist layer on each auxil- iary substrate, forming at least one separating layer on each auxiliary substrate in openings in the patterns of the resist layer, electrodepositing a conductive pattern on each separating layer in the openings in the patterns of the resist layer, embedding and attaching the at least one conductive pattern to electricity insulating material, and removing at least the auxiliary substrate from the rest of the layer structure.
[0016] The invention also relates to a circuit board. The circuit board has a layered structure and the circuit board has been formed using in the production at least one auxiliary substrate with a conductive surface, on which at least one separating layer has been formed, and the circuit board comprises at least one conductive pattern produced by forming a patterned resist layer on each separating layer, by electrodepositing a conductive pattern on each separating layer in openings in the patterns of the resist layer, and the circuit board has been formed by embedding and attaching the at least one conductive pattern to electricity insulating material and by removing at least the auxiliary sub- strate from the rest of the layer structure.
[0017] The invention also relates to a circuit board. The circuit board has a layered structure and the circuit board has been formed using in the production at least one auxiliary substrate with a conductive surface, and the conductive pattern has been produced by forming a patterned resist layer on each auxiliary substrate, by forming at least one separating layer in openings in the patterns of the resist layer, by electrodepositing a conductive pattern on each separating layer in the openings in the patterns of the resist layer, and the circuit board has been formed by embedding and attaching the at least one conductive pattern to electricity insulating material and by removing at least each auxiliary substrate from the rest of the layer structure. [0018] The invention also relates to a conductive pattern. The conductive pattern has been formed by using in the production at least one auxiliary substrate with a conductive surface, on which at least one separating layer has been formed, and each circuit board comprises at least one conductive pattern produced by forming and patterning a resist layer on the separating layer, by electrodepositing a conductive pattern on the separating layer in openings in the patterns of the resist layer, each auxiliary substrate being removable from the layer structure formed.
[0019] The invention also relates to a conductive pattern. The conductive pattern has been formed by using in the production at least one auxil- iary substrate with a conductive surface, on which a patterned resist layer has been formed, and the conductive pattern has been produced by forming a separating layer on each auxiliary substrate in openings in the patterns of the resist layer, by electrodepositing growing a conductive pattern on the separating layer in the openings in the patterns of the resist layer, each auxiliary sub- strate being removable from the layer structure formed.
[0020] Preferred embodiments of the invention are described in the dependent claims.
[0021] The method and system according to the invention provide several advantages. The conductor cross section is rectangular and no lateral under etching occurs. Consequently, conductors and spaces between conductors can be provided with a high dimensional accuracy. There are fewer different production process steps than in etching methods and the production costs are low. Copper or copper-coated plastic can be used as the auxiliary substrate and intermediate layer, both copper and plastic being easily recycla- ble materials. The production process requires less corroding materials and materials that are poisonous and hazardous to the environment and humans, which reduces the need for post-processing of these materials and the costs resulting from post-processing. LIST OF FIGURES
[0022] The invention will now be described in greater detail by means of the presented embodiments, with reference to the accompanying drawings, in which Figure 1A illustrates a layer structure comprising a temporary auxiliary substrate, a separating layer and a conductive pattern,
Figure 1 B illustrates another kind of layer structure comprising a temporary auxiliary substrate, a separating layer and a conductive pattern,
Figure 2A illustrates a pre-form for a one-sided circuit board, Figure 2B illustrates a one-sided circuit board,
Figure 2C illustrates attachment of circuit board material to a conductive pattern as a continuous process,
Figure 3 illustrates a two-sided circuit board provided with through- holes, Figure 4 illustrates an "any layer microvia" circuit board,
Figures 5A and 5B illustrate a two-sided 2.5D circuit board, where the upper side and the lower side have been connected to each other electrically by a fold in the circuit board,
Figure 6 illustrates an L-shaped 2.5D circuit board, Figure 7A illustrates production of a 3D circuit board between the jaws of a hot press,
Figure 7B illustrates production of a 3D circuit board in a mould, Figure 7C illustrates a 3D circuit board,
Figures 8A to 8C illustrate embedding of a deposited/printed com- ponent in a circuit board,
Figures 9A to 9E illustrate embedding of a component in a circuit board,
Figures 10A to 10E illustrate embedding of a component in a circuit board, Figure 1 1 illustrates production of a conductive pattern as a continuous process,
Figure 12 illustrates a production method of a conductive pattern as a flowchart,
Figure 13 illustrates a production method of a conductive pattern as a flowchart, Figure 14 illustrates a production method of a circuit board as a flow chart, and
Figure 15 illustrates a production method of a circuit board as a flow chart.
DESCRIPTION OF EMBODIMENTS
[0023] Production of a conductive pattern will be examined first. Figure 1A illustrates a conductive pattern 100 on an intermediate layer 102. In the solution described, the conductive pattern 100 can be deposited on a separating layer 101 included in the layer structure. The separating layer 101 may comprise both an intermediate layer 102 and a release layer 104, but the separating layer 101 may also be a mere release layer 104. The layer structure further comprises an auxiliary substrate 106. Before depositing the conductive pattern 100, the separating layer 101 is coated with a patterned resist 108. In that case, either the intermediate layer 102 or the release layer 104 is coated with a resist. The conductive pattern is electrodeposited in openings in the resist 108. The conductive pattern 100 together with the optional intermediate layer 102 can be removed from the auxiliary substrate 106 by means of the release layer 104.
[0024] Figure 1 B illustrates an alternative way of producing a con- ductive pattern. In this solution, a patterned resist layer 108 is formed on the auxiliary substrate 106, where at least the surface is conductive. The release layer 104 is formed on the auxiliary substrate 106 in openings in the patterns of the resist layer 108. The conductive pattern 100 is electrodeposited on the release layer 104 in the openings in the patterns of the resist layer 108. Thus less release layer material is required. Also in this solution, at least the auxiliary substrate 106 is removable from the layer structure formed. Both in the case of Figure 1A and in the case of Figure 1B, the intermediate layer 102 (between layers 100 and 104) can be used to level out any non-homogeneities in the auxiliary substrate. [0025] The temporary auxiliary substrate 106 may be totally conductive or only its surface. Even though the intermediate layer 102 is not necessarily needed in the solution described, the intermediate layer 102 may be employed to level out any non-homogeneity in the auxiliary substrate, to function as a current transmission layer in the metallization of vias and/or to facilitate the removal of the auxiliary substrate 106 and/or any bonded components. The intermediate layer 102 can be omitted, for example, in a case where the adhesion of the circuit board material to be attached to the auxiliary substrate or to the auxiliary substrate 106 coated with a release layer 104 is so small that the circuit board material and the auxiliary substrate 106 can be reliably removed from each other.
[0026] The auxiliary substrate 106 may be made of metal, such as stainless steel, titan, nickel, aluminium or copper or of their combination in the form of a rigid plate, a three-dimensional shape, or a film-like or rollable ribbon. A metal-coated plastic board or film, such as a copper-coated plastic film in the form of a rollable ribbon, may also be used as the auxiliary substrate 106 since the auxiliary substrate needs to be conductive. PET (polyethylene terephtha- late), for example, may be used as the plastic film. In practice, the thickness of the auxiliary substrate 106 may range from less than 15 μm to several millimetres. The lower limit is restricted by the mechanical processability of the auxil- iary substrate 106 and the upper limit by processability and cost factors. The auxiliary substrate may be used several times or it may be disposable. A disposable auxiliary substrate 106 may be made of copper ribbon or copper- coated plastic film, both of which are easily recyclable materials.
[0027] The release layer 104 between the auxiliary substrate 106 and the intermediate layer 102 or between the auxiliary substrate 106 and the conductive pattern 100 may be made of metals or other organic substances without being limited to these. The metal in the release layer 104 may be nickel and/or chrome, for example, with which the auxiliary substrate 106 is coated electrolytically. The thickness of a metal release layer 104 is typically 1 to 100 nm. If a very thin release layer 104 is used, release cannot be performed reliably. The use of a very thick release layer 104, on the other hand, is not reasonable in the economic sense or in view of recycling.
[0028] An organic release layer 104 may be made of carboxyben- zotriazole, for instance. The substance of the release layer may be dissolved into water or solvent, where the auxiliary substrate 106 is kept for a certain time. A typical thickness of the organic release layer 104 is approximately 1 to 100 nm.
[0029] An intermediate layer 102 may be electrodeposited on the release layer 104. The intermediate layer 102 may be made of copper, for ex- ample, having a typical thickness of 0.5 to 7 μm. The thinner the intermediate layer 102 used, the easier its removal usually is. [0030] The separating layer 101 is coated with a patterned resist 108. In the patterning, it is feasible to use a patterned photoresist, for example. The patterning of a resist 108 is known per se. The patterned resist 108 can also be layered onto an underlying layer by printing. The surface of the inter- mediate layer 102 or auxiliary substrate 106 can be roughened to improve adhesion to the resist 108. Conductive patterns 100 with a desired thickness, typically 3 to 50 μm, are deposited on the separating layer 101 in the openings in the resist 108. Also thinner or thicker conductors can be deposited.
[0031] After deposition, the conductors 100 can be roughened by known techniques to provide a better adhesion to the insulating circuit board material. The conductors need not be deposited from one material but they may consist of several different metal layers. For example, gold can be deposited as the lowest layer, on top of which nickel and copper layers are deposited. In a completed circuit board having this kind of layer structure, compo- nents may be contacted to the gold layer, which is often necessary with respect to contacting.
[0032] It may not be necessary to remove the resist 108, but the resist can be left in its place, and thus it will be part of the final circuit board.
[0033] Figure 2A illustrates a one-sided circuit board pre-form, which may be produced by attaching electricity insulating circuit board material 200 to the layer structure. The layer structure comprises as superimposed layers a temporary auxiliary substrate 106, a separating layer 101 and a conductive pattern 100, which is optionally treated with adhesive. The layer structure may also include a resist 108, but this is not necessary. The electricity insulat- ing material 200 may be, for example, hardening epoxy, thermoplastic plastic or disposable plastic. Typical circuit board epoxy is curdled and hardened by increasing the temperature to a suitable temperature at a certain speed. Thermoplastic plastic softens when it is heated and hardens when cooled. The circuit board material 200 may be nearly any electricity insulating material that can be provided with a sufficiently fluid form for embedding conductive patterns in it. Furthermore, the circuit board material 200 has to re-harden after this. Inside the circuit board material 200, it is feasible to use structures and additives that stiffen the circuit board, affect the thermal properties and/or electric properties, such as mats or fibres made of glass fibre or Teflon, or ceramic powder, or their combinations. [0034] After the layer structure, which comprises a temporary auxiliary substrate 106, a release layer 104, an optional intermediate layer 102 and a conductive pattern 100 (and possibly also a resist 108), has been attached to the circuit board material 200, the auxiliary substrate 106 is removed from the separating layer 101. When the release layer 104 has been properly produced, mechanical removal is easy to carry out without removing the optional intermediate layer 102 and the conductive pattern 100 from the circuit board material 200. In a preferred embodiment, adhesion should be within a range of approximately 0.001 to 0.2 N/mm, depending on the case and materials. [0035] The optional intermediate layer 102 and any remains of the release layer 104 attached thereto can be removed by etching, for example. The result will be a one-sided circuit board 202 similar to the one illustrated in Figure 2B, where conductive patterns 100 have been pressed inside the circuit board and thus its surface is in one level. [0036] Figure 2C illustrates attachment of circuit board material to a conductive pattern as a continuous process. Circuit board ribbon 222 is fed from a circuit board roll 220 into a laminator 224, into which conductive pattern ribbons 230, 232 are also fed from two conductive pattern rolls 226, 228, the ribbons comprising an auxiliary substrate, a separating layer and a conductive pattern. The laminator 224, which may comprise two rolls 234, 236, for example, presses the conductive pattern ribbons 230, 232 onto different sides of the circuit board ribbon 222 by means of increased temperature, for example, if the circuit board ribbon 222 is made of thermoplastic material. Finally, the two- sided circuit board pre-form 238 can be rolled up into a roll 240. [0037] A two-sided circuit board may be produced in the same manner as the one-sided circuit board. As shown in Figure 3, a layer structure is attached to both sides of insulating circuit board material 200 so that the conductive pattern 100 faces the insulating circuit board material 200. Conductive patterns 100 on both sides of the board can be connected to each other through through-holes or microvias 300. Vias can be formed by laser drilling and using circuit board processes known per se to metallize a via and optionally fill it. In the metallization of a via, an intermediate layer may be employed in the transfer of electricity.
[0038] Figure 4 illustrates a multi-layer circuit board. Multi-layer cir- cuit boards may be produced by connecting two or more one-sided or two- sided circuit boards produced by the process according to the presented solu- tion or by piling circuit boards one on top of another or by combining both of these methods. As shown in Figure 4, it is also feasible to produce "any layer microvia" circuit boards where the micro through-hole 300 may go through the circuit board material 400 to 404 in any layer and micro through-holes may be superimposed.
[0039] Figures 5A and 5B illustrate a two-sided circuit board which may be produced by folding a layer structure comprising a temporary auxiliary substrate 106, a separating layer 101 and a conductive pattern 100 (optionally with resists 108) to cover both sides of the insulating circuit board material 200. The conductive pattern 100 may be adhesion treated. The upper and lower sides of the circuit board are contacted to each other by a fold 500. The fold may be on one or several sides of the circuit board 200.
[0040] In addition to the fact that the conductive pattern and circuit board may be produced as a planar two-dimensional structure (2D conductive pattern), the presented solution enables production of two-and-half- dimensional or three-dimensional conductive patterns (2.5D or 3D conductive patterns). Thus a 2.5D conductive pattern may be formed on a 2D circuit board, as illustrated in Figures 5A and 5B. Here the 2.5D shape refers to a shape achieved by folding a planar pattern. [0041] Structures having the 2.5 shape are easy to produce by providing the circuit board 200 with an L-shaped cross section, for example, as illustrated in Figure 6. In Figure 6, the conductive pattern 100 is on the inner surface of the circuit board 200, but it may naturally also be arranged on the outer surface or alternatively on both surfaces, which are optionally connected by a fold extending across the circuit board edge or by through-holes.
[0042] A circuit board with a three-dimensional shape may be produced as follows, for example. The layer structure may be provided with the 3D shape using pressure and heat or other known shaping methods, such as hot pressing, pressure shaping or high speed shaping. These shaping meth- ods are material-dependent. The conductive patterns may be adhesion treated to improve adhesion to the electricity insulating material where the conductive pattern is embedded.
[0043] Figures 7A to 7C illustrate solutions where the layer structure 716 has been folded into a spherical calotte. After the conductive pattern on the upper surface of the auxiliary substrate has been provided with the 3D shape in accordance with Figure 7A, the layer structure 716 can be placed in a hot press together with the insulating material 200 to be attached thereto. The jaws 702, 704 of the hot press have been provided with the same 3D shape. The insulating material 200 is attached to the conductive pattern on the auxiliary substrate by pressing them between the jaws 702, 704 of the hot press. The circuit board material functioning as the insulating material may also be provided with the 3D shape before hot pressing.
[0044] Figure 7B illustrates a layer structure 716 folded into the shape of a spherical calotte in the casting space 712 of an injection moulding die. The layer structure 716 provided with the 3D shape forms part of the die. Injection moulding can be performed through a casting conduit 714. The conductive pattern on the layer structure attaches onto one or both surfaces of the injection moulded product. In the case of Figures 7A and 7B, pre-forming of the 3D shape is not always necessary, but forming may be carried out during pressing or casting. Figure 7C illustrates a cross section of a final 3D circuit board 710 with the shape of a spherical calotte.
[0045] Now we will examine embedding of components in a circuit board. Components may be embedded in a circuit board together with conductive patterns by attaching components onto the conductive pattern or by forming components onto the intermediate layer before the conductive pattern is produced or after the conductive pattern has been produced. In the following, different ways of forming a component and a conductive pattern and of embedding them in a circuit board will be described in greater detail.
[0046] Figures 8A to 8C illustrate examples of solutions where components are formed onto the conductive pattern (or under the conductive pattern).
[0047] Figure 8A illustrates a solution where at least one component 800, such as a resistor, may be electrodeposited on the conductive pattern 100 and the intermediate layer 102 in the openings in the resist pattern 108 (broken line). Alternatively, the component may be pressed onto the conductive pattern 100 and separating layer 101 by a screen printing method, for example, in which case no resist pattern is needed.
[0048] Figure 8B illustrates a production method where a component 800, such as a resistor, is first printed onto the separating layer 101 by a screen printing, for example. Thereafter, a conductive pattern 100 is formed on the component 800 and the separating layer 101 in the openings in the resist pattern. Alternatively, the component can be first formed by electrodepositing it on the separating layer 101 in the openings in the resist pattern (broken line), after which the resist pattern can be removed. Thereafter, the conductive pattern 100 may be electrodeposited on the component 800 and the separating layer 101 in the openings in the resist pattern 108. [0049] Figure 8C illustrates a final circuit board 850 where the component 800 has been embedded. The component can be printed onto the conductive pattern 100 in the separating layer 101 or the component may be electrodeposited on the conductive pattern 100 and the separating layer 101 in the openings in the resist pattern. After insulating material 200 has been attached, the auxiliary substrate is removed and the intermediate layer etched.
[0050] Also leaded or bumped components and semiconductor chips attached to a conductive pattern are embeddable. A connection may be made conductive using conductive adhesive or a solder joint in attachment. The component may be, for example, a leaded surface mounting component, a leaded or a bumbed module or a flip chip. Depending on the material, it may be necessary to provide the circuit board material with a cavity or an opening at the component before attaching the circuit board material. The component may also be protected with plastic encapsulation before attachment of the circuit board material. [0051] Figure 9A illustrates a bumped component 900 whose bumps 902 are attached to the conductive pattern 100 functioning as the uppermost layer in the layer structure comprising the auxiliary substrate 106 and the separating layer 101 using an adhesive or a solder joint 904. Thereafter, the lower side of the component may be filled with an "underfill agent" 906, as shown in Figure 9B. This provides the final circuit board with an even surface. The component together with the conductive pattern 100 and any underfill agent 906 is attached to the circuit board material 200 as in Figure 9C.
[0052] Alternatively, the component 900 area in the circuit board material 200 may be provided with an opening 908, which may be filled with another material 910, as illustrated in Figure 9D. The opening may be filled, for example, with plastic which has been hardened chemically, by heat or ultraviolet. An advantage of this arrangement is that any stress to which the component may be subjected during the attachment of the conductive pattern to the circuit board material can be avoided. Furthermore, the filling material may be a material which stabilizes tensions caused by differences in the temperature expansion coefficient as the temperature between the component and the cir- cuit board material varies. Finally, the auxiliary substrate is removed and any intermediate layer is etched, and thus a circuit board is obtained, as illustrated in Figure 9E.
[0053] Attachment of the component 900 may be carried out by electrodepositing copper on the conductive pattern 100 over the component 900 leg or bonding area, as illustrated in Figures 10A to 10E, where the layer 1 14 may comprise either a release layer 104 or an intermediate layer 102. The layer 114 may also comprise both a release layer 104 and an intermediate layer 102 or sections of them. A component or a semiconductor chip 900 ac- cording to Figure 10 A is attached by adhesive 910 to the conductive pattern 100, which is provided with openings 912 at the bonding areas of the component or the semiconductor chip 900. The adhesive may be conductive. Alternatively, it is feasible to use a component or a semiconductor chip provided with bumps or legs 950. Thereafter, in accordance with Figure 10B, the lower side of the component 900 may be filled with an "underfill agent" 906, which provides the final circuit board with an even surface. The same substance may be used both as the adhesive 910 and as the underfill agent 906, in which case the adhesion of the semiconductor chip and the underfill process can be performed in one and the same process step. [0054] At the component 900, the circuit board material 200 may be provided with an opening, which may be filled with another material in the same way as described above in connection with Figure 9D. In accordance with Figure 10C, the component 900 may be attached to the circuit board material 200 together with the conductive pattern 100 and any underfill agent 906. The auxiliary substrate is removed and openings 920 are formed in the layer 1 14 by laser machining, for example, at the bonding areas, bumps or legs 950 of the component. Remaining adhesive can also be removed by laser machining. Then an electric contact is formed between the component 900 leg 950 and the conductive pattern 100 using, for example, chemical or electrolytic coppering or their combination. In accordance with Figure 10D, the intermediate layer 102 may, before contacting, be covered with a patterned resist 922 to avoid depositing copper 924 on the whole sample area. A completed circuit board 1000, which may be a printed circuit board, with embedded components is obtained when any resist is removed and the layer 1 14 etched, as illustrated in Figure 10E. [0055] The component/components and/or semiconductor chips may naturally be embedded in a single-layer circuit board or in different layers of a multi-layer circuit board.
[0056] The component/components and/or semiconductor chips may naturally also be embedded in 2.5D and 3D structures.
[0057] Figure 11 illustrates a "from a roll to a roll" process where a layer structure including a conductive pattern can be produced as a continuous process. In this solution, auxiliary substrate ribbon is fed from a roll 1100 to another roll 1102. A release layer 104 is formed on a conductive auxiliary sub- strate 106 by means 1104 for producing a release layer. The conductive auxiliary substrate may be made of copper or provided with a copper surface. An intermediate layer 102 is formed on the release layer 104 by means 1106 for producing an intermediate layer. Resist spreading means 1108 are used for forming a patterned resist layer 108 on the intermediate layer 102. A conduc- five pattern 100 is electrodeposited on the intermediate layer 102 in openings in the resist layer 108 by means 1110 for producing a conductive pattern.
[0058] Figure 12 is a flow chart illustrating a method of producing a conductive pattern. In step 1200, a separating layer 101 is formed on an auxiliary substrate 106, where at least the surface is conductive. In step 1202, a patterned resist layer 108 is formed on the separating layer 101. In step 1204, a conductive pattern 100 is electrodeposited on the separating layer 101 in openings in the patterns of the resist layer 108.
[0059] Figure 13 is also a flow chart illustrating a method of producing a conductive pattern. In step 1300, a patterned resist layer 108 is formed , on an auxiliary substrate 106, where at least the surface is conductive. In step 1302, a separating layer 101 is formed on the auxiliary substrate 106 in openings in the patterns of the resist layer 108. In step 1304, a conductive pattern 100 is electrodeposited on the separating layer 101 in the openings in the pattern of the resist layer 108. Both in the case according to Figure 12 and in the case according to Figure 13, at least the auxiliary substrate 106 is removable from the layer structure thus formed.
[0060] Figure 14 illustrates a production method of a circuit board.
The method employs at least one auxiliary substrate 106 with a conductive surface. In step 1400, at least one separating layer 101 is formed on each aux- iliary substrate 106. In step 1402, a patterned resist layer 108 is formed on each separating layer 101. In step 1404, a conductive pattern 100 is electro- deposited on each separating layer 101 in openings in the patterns of the resist layer 108. In step 1406, the at least one conductive pattern is embedded and attached to electricity insulating material 200. In step 1408, the auxiliary substrate 106 is mechanically removed from the rest of the layer structure. [0061] Figure 15 also illustrates a production method of a circuit board. The method employs at least one auxiliary substrate 106 with a conductive surface. In step 1500, a patterned resist layer 108 is formed on each auxiliary substrate 106. In step 1502, at least one separating layer 101 is formed on each auxiliary substrate 106 in openings in the patterns of the resist layer 108. In step 1504, a conductive pattern 100 is electrodeposited on each separating layer 101 in the openings in the patterns of the resist layer 108. In step 1506, the at least one conductive pattern 100 is embedded and attached to electricity insulating material 200. In step 1508, the auxiliary substrate 106 is mechanically removed from the rest of the layer structure. [0062] A general advantage of the solution described is that there are no adverse local variations in height in the surface of a completed circuit board. A further advantage of the solution described is that both rigid and flexible circuit boards can be produced.
[0063] In the following, two examples illustrating the solution de- scribed will be examined. For example, a copper film with a thickness of 100 μm is coated in an electrolytic bath with a release layer having a thickness of 20 nm using the Atotech Trichrome plus electrolysis bath. Thereafter, the sample is rinsed and an intermediate layer of copper is deposited on it using the Atotech Cupracid BL-CT bath with a current density of 1.5 A/dm2. The average thickness of the deposited layer may be 3.5 μm. Thereafter, the surface of the deposited thin copper layer may be microetched and coated with a negative dry film resist with a thickness of 38 μm, which is patterned with the desired pattern. A conductive pattern may be deposited in the openings in the resist pattern using the Atotech Cuparic Acid BL-CT bath with a current density of 1.5 A/dm2. The average thickness of the conductive pattern may be 25 μm. The upper surface of the conductive pattern may be roughened in an acid micro- etch and the resist removed. The conductive pattern thus produced can be pressed together with Hitachi GEA 67 b-state epoxy in a vacuum press at a pressure of 15 bar by increasing the temperature 6°C/min up to 19O0C, which final temperature may be maintained for one hour. After the sample has cooled down, the copper film used as a temporary deposition substrate can be re- moved from the sample surface by pulling. It can also be visually noted that the chrome film, which is seen as a layer darker than the copper layer, is removed with the temporary deposition substrate. Thereafter, the thin copper intermediate layer on the sample surface can be etched off. The final result will be a one-sided circuit board whose surface is in one plane and where the conductors are embedded in the circuit board material.
[0064] In the second example, a copper film with a thickness of 100 μm is coated in an electrolytic bath with a release layer having a thickness of 20 nm using the Atotech Trichrome plus electrolysis bath. Thereafter, the sam- pie is rinsed and an intermediate layer of copper is deposited on it using the Atotech Cupracid BL-CT bath with a current density of 1.5 A/dm2. The average thickness of the deposited layer may be 1 μm. Thereafter, an AZ4562 resist may be spread on the thin copper layer and patterned with the desired pattern. A conductive pattern may be deposited in the openings in the resist pattern using the Atotech Cuparic Acid BL-CT bath with a current density of 1.5 A/dm2. This provides a conductive pattern with an average thickness of 9 μm. The upper surface of the conductive pattern may be roughened in an acid micro- etch and the resist removed. The conductive pattern thus produced can be pressed together with Hitachi GEA 67 b-state epoxy in a vacuum press at a pressure of 15 bar by increasing the temperature 6°C/min up to 19O0C, which final temperature may be maintained for one hour. After the sample has cooled down, the copper film used as a temporary deposition substrate can be removed from the sample surface by pulling. It can also be visually noted that the chrome film, which is seen as a layer darker than the copper layer, is removed with the temporary deposition substrate. Thereafter, the thin copper intermediate layer on the sample surface can be etched. The final result will be a onesided circuit board whose surface is in one plane and where the conductors are embedded in the circuit board material. Even narrow conductors and conductor spaces (for example 6 μm) can be formed reliably. [0065] Material combinations other than the ones used in the examples described may also be employed.
[0066] Even though the invention was described with reference to examples according to the accompanying drawings, it is clear that the invention is not limited thereto but it may be modified in various ways within the scope of the appended claims.

Claims

1. A method of producing a conductive pattern, characterized by forming (1200) a separating layer (101 ) on an auxiliary substrate (106), where at least the surface is conductive, forming (1202) a patterned resist layer (108) on the separating layer (101 ), electrodepositing a conductive pattern (100) on the separating layer (101 ) in openings in the patterns of the resist layer (108), at least the auxiliary substrate (106) being mechanically removable from the layer structure formed.
2. A method according to claim 1 , ch aracterized by forming the separating layer (101 ) by forming a release layer (104) on the auxiliary substrate (106) and by forming an intermediate layer (102) on the release layer (104).
3. A method according to claim 1 , characterized by forming the separating layer (101 ) by forming a release layer (104) on the auxiliary substrate (106).
4. A method according to claim 1 , ch aracterized by forming a temporary auxiliary substrate (106) where at least the surface is made of cop- per.
5. A method according to claim 1 , characte rized in that the conductive pattern (100) comprises a plurality of layers made of different metals.
6. A method according to claim 1 , ch aracterized in that the aux- iliary substrate (106) is made of flexible copper ribbon.
7. A method according to claim 1 , characterized by forming the release layer (104) of metal having a thickness less than 1 μm.
8. A method according to claim 1 , characterized by forming the release layer (104) of electrolytically coated chrome or nickel.
9. A method according to claim 1 , characterized by forming the release layer (104) of organic material.
10. A method according to claim 1 , characterized by electrode- positing the intermediate layer (102) of copper.
1 1. A method according to claim 1 , characterized by forming the conductive pattern (100) as a continuous process by a "from a roll to a roll" method.
12. A method according to claim 1 , ch aracterized by using a photoresist as the resist (108).
13. A method according to claim 1 , characterized by pressing the resist (108) in the patterned form on the separating layer (101 ).
14. A method according to claim 1 , characterized by roughening the intermediate layer (102) chemically before spreading the resist (108) to improve adhesion.
15. A method according to claim 1 , ch aracterized by roughening the surface of the conductive pattern (100) to increase adhesion for attachment to the circuit board material (200).
16. A method according to claim 1 , characterized by forming the conductive pattern so that it has more than 2 dimensions.
17. A method of producing a conductive pattern, characterized by forming (1300) a patterned resist layer (108) on an auxiliary substrate (106), where at least the surface is conductive, forming (1302) a separating layer (101 ) on the auxiliary substrate in openings in the patterns of the resist layer (108), electrodepositing (1304) a conductive pattern (100) on the separating layer (101 ) in the openings in the patterns of the resist layer (108), at least the auxiliary substrate (106) being mechanically removable from the layer structure formed.
18. A method of producing a circuit board, ch aracterized by the method employing at least one auxiliary substrate (106) with a conductive surface, forming (1400) at least one separating layer (101 ) on each auxiliary substrate (106), forming (1402) a patterned resist layer (108) on each separating layer (101 ), electrodepositing (1404) a conductive pattern (100) on each separating layer (101 ) in openings in the patterns of the resist layer (108), embedding and attaching (1406) the at least one conductive pattern
(100) to electricity insulating material (200), and removing (1406) at least the auxiliary substrate (106) from the rest of the layer structure mechanically.
19. A method according to claim 18, characterized by forming the separating layer (101 ) by forming a release layer (104) on the auxiliary substrate (106) and by forming an intermediate layer (102) on the release layer (104).
20. A method according to claim 18, characterized by forming the separating layer (101 ) by forming a release layer (104) on the auxiliary substrate (106).
21. A method according to claim 18, characterized by forming a multi-layer auxiliary substrate where conductive patterns (100) are at least in two layers and connecting different conductive patterns electrically to each other.
22. A method according to claim 18, characterized by removing the resist layer (108) before embedding and attaching the conductive pattern
(100) to the electricity insulating material (200).
23. A method according to claim 18, characterized by forming a multi-layer circuit board by folding a layer structure comprising a temporary auxiliary substrate (106), a separating layer (101 ) and a conductive pattern (100) to cover at least part of the both sides of the insulating material (200).
24. A method according to claim 18, characterized by connecting at least two conductive patterns (100) in different layers electrically to each other by electrodepositing metal.
25. A method according to claim 18, characterized by forming at least one component (800, 900) which is to be connected to the conductive pattern and embedded in the circuit board material (200) by electrodepositing each component (800) at an opening in the resist (108) in the intermediate layer (102).
26. A method according to claim 18, characterized by forming at least one component (800) at a desired point in the intermediate layer (102) by pressing and embedding the component in the circuit board material (200).
27. A method according to claim 18, characterized by forming the conductive pattern so that it has more than 2 dimensions.
28. A method according to claim 18, characterized by attaching at least one component (900) to the conductive pattern (100) and embedding the component in the circuit board.
29. A method according to claim 28, ch aracterized by connecting the at least one component to the conductive pattern (100) by conductive adhesive or by soldering.
30. A method according to claim 28, characterized by using a flip chip as the component (900).
31. A method according to claim 28, characterized by using a bumped component as the component (900).
32. A method according to claim 18, characterized by electrically contacting at least one component (900) to the conductive pattern (100) by means of electrolytic metallization and embedding the component in the circuit board.
33. A method according to claim 28, 29, 30, 31 or 32, characterized by using more than one material in the same layer as the circuit board material by leaving a hole in the first connecting board material (200) at at least one embedded component (900) and filling the hole with another material (908).
34. A method of producing a circuit board, ch aracterized by the method employing at least one auxiliary substrate (106) with a conductive surface, forming (1500) a patterned resist layer (108) on each auxiliary substrate (106), forming (1502) at least one separating layer (101 ) on each auxiliary substrate (106) in openings in the pattern of the resist layer (108), electrodepositing (1504) a conductive pattern (100) on each sepa- rating layer (101 ) in the openings in the patterns of the resist layer (108), embedding and attaching (1506) the at least one conductive pattern (100) to electricity insulating material, and removing (1508) at least the auxiliary substrate from the rest of the layer structure mechanically.
35. A circuit board, characterized in that the circuit board has a layered structure and the circuit board has been formed using in the production at least one auxiliary substrate (106) with a conductive surface, on which at least one separating layer (101 ) has been formed, and the circuit board comprises at least one conductive pattern (100) produced by forming a patterned resist layer (108) on each separating layer
(101 ), electrodepositing a conductive pattern (100) on each separating layer (101 ) in openings in the patterns of the resist layer (108), and the circuit board has been formed by embedding and attaching the at least one conductive pattern (100) to electricity insulating material, and removing at least the auxiliary substrate (106) from the rest of the layer structure mechanically.
36. A circuit board according to claim 35, characterized in that the conductive pattern (100) comprises a plurality of layers made of different metals.
37. A circuit board according to claim 35, characterized in that the resist layer (108) has been removed before embedding and attaching the conductive pattern (100) to the electricity insulating material (200).
38. A circuit board according to claim 35, characterized in that at least one component (800, 900) has been formed in the conductive pattern and electrically contacted to it and the component is embedded in the electricity insulating material (200) of the circuit board.
39. A circuit board, characterized in that the circuit board has a layered structure and the circuit board has been formed using in the production at least one auxiliary substrate (106) with a conductive surface, and the conductive pattern is produced by forming a patterned resist layer (108) on each auxiliary substrate (106), forming at least one separating layer (101) on each auxiliary sub- strate (106) in openings in the patterns of the resist layer (108), electrodepositing a conductive pattern (108) on each separating layer (101) in the openings in the patterns of the resist layer (108), and the circuit board has been formed by embedding and attaching the at least one conductive pattern (100) to electricity insulating material (200), and removing at least each auxiliary substrate (106) from the rest of the layer structure mechanically.
40. A conductive pattern, characterized in that the conductive pattern has been formed by using in the production at least one auxiliary sub- strate (106) with a conductive surface, on which at least one separating layer (101) has been formed, and each circuit board (106) comprises at least one conductive pattern (100) produced by forming and patterning a resist layer (108) on the separating layer (101 ), electrodepositing a conductive pattern (100) on the separating layer
(101) in openings in the patterns of the resist layer (108), each auxiliary substrate being mechanically removable from the layer structure formed.
41. A conductive pattern, characterized in that the conductive pattern has been formed using in the production at least one auxiliary sub- strate (106) with a conductive surface, on which a patterned resist layer (108) has been formed, and the conductive pattern has been produced by forming a separating layer (101 ) on each auxiliary substrate (106) in openings in the patterns of the resist layer (108), electrodepositing a conductive pattern (100) on the separating layer (104) in the openings in the patterns of the resist layer (108), each auxiliary substrate (106) being mechanically removable from the layer structure formed.
PCT/FI2005/050466 2004-12-23 2005-12-20 Conductive pattern, circuit board and their production method Ceased WO2006067280A1 (en)

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FI20045501A FI20045501A7 (en) 2004-12-23 2004-12-23 Conductor pattern, connection pad and method of manufacturing conductor pattern and connection pad
FI20045501 2004-12-23

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2240005A1 (en) 2009-04-09 2010-10-13 ATOTECH Deutschland GmbH A method of manufacturing a circuit carrier layer and a use of said method for manufacturing a circuit carrier
CN101636041B (en) * 2008-07-24 2011-05-11 富葵精密组件(深圳)有限公司 Substrate plane planarization system and method thereof
US8687369B2 (en) 2012-02-20 2014-04-01 Apple Inc. Apparatus for creating resistive pathways
CN107484334A (en) * 2016-06-07 2017-12-15 鹏鼎控股(深圳)股份有限公司 Circuit board and circuit board manufacturing method
US20180007799A1 (en) * 2015-06-08 2018-01-04 Lg Chem, Ltd. Laminated body comprising metal wire layer, and manufacturing method therefor
TWI622335B (en) * 2012-11-07 2018-04-21 印可得股份有限公司 Metal printed circuit board manufacturing method

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB792920A (en) * 1954-06-25 1958-04-09 Philips Electrical Ind Ltd Improvements in or relating to methods of manufacturing an electrically conductive pattern on an insulating support
US3024151A (en) * 1957-09-30 1962-03-06 Automated Circuits Inc Printed electrical circuits and method of making the same
US4604160A (en) * 1984-01-11 1986-08-05 Hitachi, Ltd. Method for manufacture of printed wiring board
US4606787A (en) * 1982-03-04 1986-08-19 Etd Technology, Inc. Method and apparatus for manufacturing multi layer printed circuit boards
US4790902A (en) * 1986-02-21 1988-12-13 Meiko Electronics Co., Ltd. Method of producing conductor circuit boards
JPH0964514A (en) * 1995-08-29 1997-03-07 Matsushita Electric Works Ltd Production of printed wiring board
US20010023779A1 (en) * 2000-02-09 2001-09-27 Yasuhiro Sugaya Transfer material, method for producing the same and wiring substrate produced by using the same
US20030219608A1 (en) * 2002-05-23 2003-11-27 Hitoshi Ishizaka Metal transfer sheet, producing method thereof, and producing method of ceramic condenser
WO2004014114A1 (en) * 2002-07-31 2004-02-12 Sony Corporation Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board
US20040078969A1 (en) * 2002-08-06 2004-04-29 Hideo Kanzawa Method of manufacturing circuit board and communication appliance

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB792920A (en) * 1954-06-25 1958-04-09 Philips Electrical Ind Ltd Improvements in or relating to methods of manufacturing an electrically conductive pattern on an insulating support
US3024151A (en) * 1957-09-30 1962-03-06 Automated Circuits Inc Printed electrical circuits and method of making the same
US4606787A (en) * 1982-03-04 1986-08-19 Etd Technology, Inc. Method and apparatus for manufacturing multi layer printed circuit boards
US4604160A (en) * 1984-01-11 1986-08-05 Hitachi, Ltd. Method for manufacture of printed wiring board
US4790902A (en) * 1986-02-21 1988-12-13 Meiko Electronics Co., Ltd. Method of producing conductor circuit boards
JPH0964514A (en) * 1995-08-29 1997-03-07 Matsushita Electric Works Ltd Production of printed wiring board
US20010023779A1 (en) * 2000-02-09 2001-09-27 Yasuhiro Sugaya Transfer material, method for producing the same and wiring substrate produced by using the same
US20030219608A1 (en) * 2002-05-23 2003-11-27 Hitoshi Ishizaka Metal transfer sheet, producing method thereof, and producing method of ceramic condenser
WO2004014114A1 (en) * 2002-07-31 2004-02-12 Sony Corporation Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board
EP1542519A1 (en) * 2002-07-31 2005-06-15 Sony Corporation Method for manufacturing board with built-in device and board with built-in device, and method for manufacturing printed wiring board and printed wiring board
US20040078969A1 (en) * 2002-08-06 2004-04-29 Hideo Kanzawa Method of manufacturing circuit board and communication appliance

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DATABASE WPI Week 199720, Derwent World Patents Index; AN 1997-219135 *
PATENT ABSTRACTS OF JAPAN *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101636041B (en) * 2008-07-24 2011-05-11 富葵精密组件(深圳)有限公司 Substrate plane planarization system and method thereof
EP2240005A1 (en) 2009-04-09 2010-10-13 ATOTECH Deutschland GmbH A method of manufacturing a circuit carrier layer and a use of said method for manufacturing a circuit carrier
WO2010115774A1 (en) 2009-04-09 2010-10-14 Atotech Deutschland Gmbh A method of manufacturing a circuit carrier layer and a use of said method for manufacturing a circuit carrier
CN102388683A (en) * 2009-04-09 2012-03-21 埃托特克德国有限公司 Method of manufacturing a circuit carrier layer and a use of said method for manufacturing a circuit carrier
US20120118753A1 (en) * 2009-04-09 2012-05-17 Atotech Deutschland Gmbh Method of Manufacturing a Circuit Carrier Layer and a Use of Said Method for Manufacturing a Circuit Carrier
US8687369B2 (en) 2012-02-20 2014-04-01 Apple Inc. Apparatus for creating resistive pathways
TWI622335B (en) * 2012-11-07 2018-04-21 印可得股份有限公司 Metal printed circuit board manufacturing method
US20180007799A1 (en) * 2015-06-08 2018-01-04 Lg Chem, Ltd. Laminated body comprising metal wire layer, and manufacturing method therefor
US10512171B2 (en) * 2015-06-08 2019-12-17 Lg Chem, Ltd. Laminated body comprising metal wire layer, and manufacturing method therefor
CN107484334A (en) * 2016-06-07 2017-12-15 鹏鼎控股(深圳)股份有限公司 Circuit board and circuit board manufacturing method

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