WO2006072841A3 - Efficient switching between prioritized tasks - Google Patents

Efficient switching between prioritized tasks Download PDF

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Publication number
WO2006072841A3
WO2006072841A3 PCT/IB2005/053897 IB2005053897W WO2006072841A3 WO 2006072841 A3 WO2006072841 A3 WO 2006072841A3 IB 2005053897 W IB2005053897 W IB 2005053897W WO 2006072841 A3 WO2006072841 A3 WO 2006072841A3
Authority
WO
WIPO (PCT)
Prior art keywords
tasks
switching
memory stack
efficient switching
prioritized tasks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2005/053897
Other languages
French (fr)
Other versions
WO2006072841A2 (en
Inventor
Marcus J M Heijligers
Eleonora Juhasz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to US11/719,964 priority Critical patent/US20080098398A1/en
Priority to DE602005009398T priority patent/DE602005009398D1/en
Priority to JP2007542478A priority patent/JP2008522277A/en
Priority to EP05826687A priority patent/EP1820100B1/en
Publication of WO2006072841A2 publication Critical patent/WO2006072841A2/en
Publication of WO2006072841A3 publication Critical patent/WO2006072841A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/451—Code distribution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Devices For Executing Special Programs (AREA)
  • Power Steering Mechanism (AREA)
  • Vehicle Body Suspensions (AREA)
  • Steering Control In Accordance With Driving Conditions (AREA)

Abstract

The present invention relates to a processor device, task scheduling method and computer program product, wherein tasks of a program routine are selectively stored in at least two memory stack mechanisms (62, 64) of different priorities based on the allocated priorities. Switching of tasks executed at at least two processor means (20, 30) is controlled by accessing the at least two memory stack mechanisms (62, 64) in response to synchronization instructions inserted to the program routine. Thereby, efficient zero-cycle task switching between prioritized tasks can be achieved.
PCT/IB2005/053897 2004-11-30 2005-11-24 Efficient switching between prioritized tasks Ceased WO2006072841A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11/719,964 US20080098398A1 (en) 2004-11-30 2005-11-24 Efficient Switching Between Prioritized Tasks
DE602005009398T DE602005009398D1 (en) 2004-11-30 2005-11-24 EFFICIENT SWITCHING BETWEEN PRIORIZED TASKS
JP2007542478A JP2008522277A (en) 2004-11-30 2005-11-24 Efficient switching between prioritized tasks
EP05826687A EP1820100B1 (en) 2004-11-30 2005-11-24 Efficient switching between prioritized tasks

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP04106190.4 2004-11-30
EP04106190 2004-11-30

Publications (2)

Publication Number Publication Date
WO2006072841A2 WO2006072841A2 (en) 2006-07-13
WO2006072841A3 true WO2006072841A3 (en) 2006-10-12

Family

ID=36228556

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/053897 Ceased WO2006072841A2 (en) 2004-11-30 2005-11-24 Efficient switching between prioritized tasks

Country Status (7)

Country Link
US (1) US20080098398A1 (en)
EP (1) EP1820100B1 (en)
JP (1) JP2008522277A (en)
CN (1) CN100535862C (en)
AT (1) ATE406613T1 (en)
DE (1) DE602005009398D1 (en)
WO (1) WO2006072841A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007026095A (en) * 2005-07-15 2007-02-01 Matsushita Electric Ind Co Ltd Parallel computing device
US8032889B2 (en) * 2006-04-05 2011-10-04 Maxwell Technologies, Inc. Methods and apparatus for managing and controlling power consumption and heat generation in computer systems
US8276132B1 (en) * 2007-11-12 2012-09-25 Nvidia Corporation System and method for representing and managing a multi-architecture co-processor application program
US8281294B1 (en) * 2007-11-12 2012-10-02 Nvidia Corporation System and method for representing and managing a multi-architecture co-processor application program
JP5155336B2 (en) * 2008-01-15 2013-03-06 カーネロンシリコン株式会社 Task processing device
CN101290591B (en) * 2008-06-03 2011-10-12 北京中星微电子有限公司 Embedded operating system task switching method and unit
CN101290590B (en) * 2008-06-03 2012-01-11 北京中星微电子有限公司 Embedded operating system task switching method and unit
FR2942556B1 (en) * 2009-02-24 2011-03-25 Commissariat Energie Atomique ALLOCATION AND CONTROL UNIT
US20120192147A1 (en) * 2011-01-25 2012-07-26 Argen Wong Develop real time software without an RTOS

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0706126A1 (en) * 1994-10-07 1996-04-10 International Business Machines Corporation Multi-priority level scheduler
EP1031924A2 (en) * 1999-02-19 2000-08-30 Hitachi, Ltd. Computer executing multiple operating system

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4286322A (en) * 1979-07-03 1981-08-25 International Business Machines Corporation Task handling apparatus
US4435780A (en) * 1981-06-16 1984-03-06 International Business Machines Corporation Separate stack areas for plural processes
GB2191612A (en) * 1986-06-11 1987-12-16 Ibm Display terminal
JPH02271435A (en) * 1989-04-13 1990-11-06 Mitsubishi Electric Corp Task tracing device
US5161226A (en) * 1991-05-10 1992-11-03 Jmi Software Consultants Inc. Microprocessor inverse processor state usage
WO1997005550A1 (en) * 1995-07-27 1997-02-13 Intel Corporation Protocol for arbitrating access to a shared memory area using historical state information
US6128728A (en) * 1997-08-01 2000-10-03 Micron Technology, Inc. Virtual shadow registers and virtual register windows
US6243735B1 (en) * 1997-09-01 2001-06-05 Matsushita Electric Industrial Co., Ltd. Microcontroller, data processing system and task switching control method
US6157989A (en) * 1998-06-03 2000-12-05 Motorola, Inc. Dynamic bus arbitration priority and task switching based on shared memory fullness in a multi-processor system
US6993018B1 (en) * 1999-08-03 2006-01-31 Telefonaktiebolaget Lm Ericsson (Publ) Priority signaling for cell switching
FR2799081B1 (en) * 1999-09-27 2002-02-22 Cit Alcatel METHOD AND DEVICE FOR MANAGING TRANSMISSION CIRCUITS OF A NETWORK
JP3641997B2 (en) * 2000-03-30 2005-04-27 日本電気株式会社 Program conversion apparatus and method, and recording medium
US6822959B2 (en) * 2000-07-31 2004-11-23 Mindspeed Technologies, Inc. Enhancing performance by pre-fetching and caching data directly in a communication processor's register set
US6751711B1 (en) * 2000-10-27 2004-06-15 Nortel Networks Limited Methods and systems for process rollback in a shared memory parallel processor computing environment
GB2369464B (en) * 2000-11-27 2005-01-05 Advanced Risc Mach Ltd A data processing apparatus and method for saving return state
US20030014474A1 (en) * 2001-05-30 2003-01-16 Mckaig Ray S. Alternate zero overhead task change circuit
EP1391820A3 (en) * 2002-07-31 2007-12-19 Texas Instruments Incorporated Concurrent task execution in a multi-processor, single operating system environment
US20050015768A1 (en) * 2002-12-31 2005-01-20 Moore Mark Justin System and method for providing hardware-assisted task scheduling
WO2004072852A1 (en) * 2003-02-11 2004-08-26 Thomson Licensing S.A. Asynchronous communications technique
US7487502B2 (en) * 2003-02-19 2009-02-03 Intel Corporation Programmable event driven yield mechanism which may activate other threads
DE10353267B3 (en) * 2003-11-14 2005-07-28 Infineon Technologies Ag Multithread processor architecture for triggered thread switching without cycle time loss and without switching program command
US7904905B2 (en) * 2003-11-14 2011-03-08 Stmicroelectronics, Inc. System and method for efficiently executing single program multiple data (SPMD) programs

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0706126A1 (en) * 1994-10-07 1996-04-10 International Business Machines Corporation Multi-priority level scheduler
EP1031924A2 (en) * 1999-02-19 2000-08-30 Hitachi, Ltd. Computer executing multiple operating system

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHAMSI ET AL.: "The SANDRA project: cooperative architecture/compiler technology for embedded real-time streaming applications", RAPPORT DE RECHERCHE NO 4773, March 2003 (2003-03-01), Le Chesnay, France, XP002380285, Retrieved from the Internet <URL:ftp://ftp.inria.fr/INRIA/publication/publi-pdf/RR/RR-4773.pdf> [retrieved on 20060510] *
MARC DURANTON: "From SANDRA project to CAT-IP: Architectures for pixel processing", 20 November 2003 (2003-11-20), XP002380286, Retrieved from the Internet <URL:http://ce.et.tudelft.nl/cecoll/slides/delft_031120s.ppt> [retrieved on 20050510] *
RAVINDRA JEJURIKAR AND RAJESH GUPTA: "Dual Mode Algorithm for Energy Aware Fixed Priority Scheduling with Task Synchronization", IN PROC. OF WORKSHOP ON COMPILERS AND OPERATING SYSTEMS FOR LOW POWER (COLP), September 2003 (2003-09-01), XP002385916, Retrieved from the Internet <URL:http://mesl.ucsd.edu//pubs/jerjurikar_colp03.pdf> [retrieved on 20060505] *

Also Published As

Publication number Publication date
US20080098398A1 (en) 2008-04-24
EP1820100B1 (en) 2008-08-27
WO2006072841A2 (en) 2006-07-13
DE602005009398D1 (en) 2008-10-09
CN100535862C (en) 2009-09-02
ATE406613T1 (en) 2008-09-15
CN101065728A (en) 2007-10-31
EP1820100A2 (en) 2007-08-22
JP2008522277A (en) 2008-06-26

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