WO2006076276A3 - Configurable dedicated logic cells in programmable logic and routing blocks with dedicated lines and local connections - Google Patents

Configurable dedicated logic cells in programmable logic and routing blocks with dedicated lines and local connections Download PDF

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Publication number
WO2006076276A3
WO2006076276A3 PCT/US2006/000640 US2006000640W WO2006076276A3 WO 2006076276 A3 WO2006076276 A3 WO 2006076276A3 US 2006000640 W US2006000640 W US 2006000640W WO 2006076276 A3 WO2006076276 A3 WO 2006076276A3
Authority
WO
WIPO (PCT)
Prior art keywords
logic
routing block
dedicated
routing
dedicated lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/000640
Other languages
French (fr)
Other versions
WO2006076276A2 (en
Inventor
Hare K Verma
Ashok Vittal
Ravi Sunkavalli
Chandra Mulpuri
Sudip Nag
Conrad Kong
Bo Hu
Manoj Gunwani
Elliott Delaye
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Velogix Inc
Original Assignee
Velogix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/036,109 external-priority patent/US7176717B2/en
Priority claimed from US11/044,386 external-priority patent/US7605605B2/en
Priority claimed from US11/066,336 external-priority patent/US7358765B2/en
Priority claimed from US11/065,019 external-priority patent/US7368941B2/en
Application filed by Velogix Inc filed Critical Velogix Inc
Priority to EP06717800A priority Critical patent/EP2052459A2/en
Publication of WO2006076276A2 publication Critical patent/WO2006076276A2/en
Publication of WO2006076276A3 publication Critical patent/WO2006076276A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)

Abstract

A programmable logic structure is disclosed that has a set of dedicated lines (212, 222) which extends internally throughout different dedicated logic cells (210, 260) within a logic and routing block, extends from a previous logic routing block (260) to the present logic and routing block, or extends from the present logic and routing block to the next logic and routing block (270). One set of dedicated lines (212) from a first logic and routing block can be stitched to another set of dedicated lines of a second logic and routing block for extending the reach as well as bypassing a logic and routing block, or bypassing a dedicated logic cell in the same logic and routing block. The dedicated lines between logic and routing blocks allow a logic and routing block to receive more inputs from its own switch box or to drive more outputs than provided by the logic and routing block as specified by a given function.
PCT/US2006/000640 2005-01-14 2006-01-10 Configurable dedicated logic cells in programmable logic and routing blocks with dedicated lines and local connections Ceased WO2006076276A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP06717800A EP2052459A2 (en) 2005-01-14 2006-01-10 Configurable dedicated logic cells in programmable logic and routing blocks with dedicated lines and local connections

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US11/036,109 US7176717B2 (en) 2005-01-14 2005-01-14 Programmable logic and routing blocks with dedicated lines
US11/036,109 2005-01-14
US11/044,386 2005-01-27
US11/044,386 US7605605B2 (en) 2005-01-27 2005-01-27 Programmable logic cells with local connections
US11/065,019 2005-02-23
US11/066,336 US7358765B2 (en) 2005-02-23 2005-02-23 Dedicated logic cells employing configurable logic and dedicated logic functions
US11/065,019 US7368941B2 (en) 2005-02-23 2005-02-23 Dedicated logic cells employing sequential logic and control logic functions
US11/066,336 2005-02-23

Publications (2)

Publication Number Publication Date
WO2006076276A2 WO2006076276A2 (en) 2006-07-20
WO2006076276A3 true WO2006076276A3 (en) 2007-05-31

Family

ID=36678109

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/000640 Ceased WO2006076276A2 (en) 2005-01-14 2006-01-10 Configurable dedicated logic cells in programmable logic and routing blocks with dedicated lines and local connections

Country Status (2)

Country Link
EP (1) EP2052459A2 (en)
WO (1) WO2006076276A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7970979B1 (en) * 2007-09-19 2011-06-28 Agate Logic, Inc. System and method of configurable bus-based dedicated connection circuits
US8131909B1 (en) 2007-09-19 2012-03-06 Agate Logic, Inc. System and method of signal processing engines with programmable logic fabric
US8805916B2 (en) * 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335634B1 (en) * 1997-10-16 2002-01-01 Srinivas T. Reddy Circuitry and methods for internal interconnection of programmable logic devices
US6833730B1 (en) * 2002-08-30 2004-12-21 Xilinx, Inc. PLD configurable logic block enabling the rapid calculation of sum-of-products functions
US6897680B2 (en) * 1999-03-04 2005-05-24 Altera Corporation Interconnection resources for programmable logic integrated circuit devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335634B1 (en) * 1997-10-16 2002-01-01 Srinivas T. Reddy Circuitry and methods for internal interconnection of programmable logic devices
US6897680B2 (en) * 1999-03-04 2005-05-24 Altera Corporation Interconnection resources for programmable logic integrated circuit devices
US6833730B1 (en) * 2002-08-30 2004-12-21 Xilinx, Inc. PLD configurable logic block enabling the rapid calculation of sum-of-products functions

Also Published As

Publication number Publication date
WO2006076276A2 (en) 2006-07-20
EP2052459A2 (en) 2009-04-29

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