WO2006085251A2 - Block interleaving with memory table of reduced size - Google Patents
Block interleaving with memory table of reduced size Download PDFInfo
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- WO2006085251A2 WO2006085251A2 PCT/IB2006/050365 IB2006050365W WO2006085251A2 WO 2006085251 A2 WO2006085251 A2 WO 2006085251A2 IB 2006050365 W IB2006050365 W IB 2006050365W WO 2006085251 A2 WO2006085251 A2 WO 2006085251A2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/2707—Simple row-column interleaver, i.e. pure block interleaving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2782—Interleaver implementations, which reduce the amount of required interleaving memory
Definitions
- the invention relates to a method of deinterleaving, and to a corresponding method of interleaving.
- the invention further relates to a deinterleaver and to a corresponding interleaver.
- Interleaving is used in some digital communication systems to improve the robustness of the communication.
- Several schemes of interleaving and deinterleaving, which is the inverse operation of interleaving, are known: for example the so-called block interleaving, according to which a sequence of symbols to be transmitted is divided into blocks, and for each block the symbols belonging to that block are shuffled within that block prior to transmission.
- each element of the table or cell can contain one symbol: the symbols of each bock, which is a blocks of R x C symbol, are shuffled by storing them in the table on a row by row order and read out on a column by column order, or vice versa.
- the symbols can be for example bit strings of a fixed length.
- a variant of this scheme of block interleaving is used for example in Blu-ray Disc (BD) systems, according to which a block, called ECC cluster, of 248 rows and 304 columns is used.
- ECC cluster a block, called ECC cluster
- the operation of interleaving/deinterleaving can be carried out by using a memory in the form of a table of 248 rows and 304 columns.
- a buffer memory In the operation of deinterleaving in particular, bytes of an ECC block retrieved from a disc are initially stored in the table in a row by row order; subsequently, the bytes stored in the table are read out in a column by column order, and stored, in the same order in which they are read, in a different memory, often referred to as a buffer memory.
- This buffer memory typically has a rather large size, for example in the order of some Mbytes, and is usually consisting of SDRAM memory type.
- the buffer memory serves as an interface between a device for accessing a BD, often referred to as drive, and a host device such as a Personal Computer.
- This table of R rows x C columns bytes needs to be suitable for a fully random access, since the order in which elements of the table are written is different from the order in which said elements of the table are read, e.g. row by row vs. column by column.
- This consideration points to the use of SRAM memory, where each byte can be individually addressed.
- a major drawback of the use of SRAM for the table is that this type of memory is space consuming and, for the required amount of memory, that is 248 x 304 bytes, leads to a remarkable area in encoder/decoder IC allocated only for the table.
- the first object is achieved by a method of deinterleaving as claimed in claim 1 and by a corresponding method of interleaving as claimed in claim 6.
- the deinterleaving of the symbols belonging to the block of R x C symbols is effected without the use of a table of R rows and C columns, but instead with a smaller table of N rows and C columns.
- the rearrangement of the symbols according to the rearranged order is accomplished in the buffer memory due to the combination of the use of the table and the order with which the symbols taken from each column of the table are stored in the buffer memory.
- the rearrangement of the symbols according to the rearranged order is accomplished due to the combination of the use of the table and the order with which the symbols taken from the buffer memory are stored in the columns of the table.
- Such a deinterleaving method involves however a major drawback: accesses to the SDRAM buffer memory are made very slow and inefficient.
- an SDRAM memory has some entries, individually addressable, consisting of a few bytes, e.g. 8 or 16 bytes, and the access to the SDRAM memory takes place with the best efficiency if entries are accessed at once.
- This reflects the fact the SDRAM memories are well suited for accesses where the transfer of a relatively large package of data is involved.
- loss in efficiency derives, which loss in efficiency is sometimes referred to as loss in bandwidth or bandwidth penalty. It is clear that the worst situation for loss in bandwidth is in place when individual bytes are accessed in a non-sequential order.
- accesses to the buffer memory are kept relatively efficient if compared to the known method, since symbols are written therein in groups of N and not individually.
- N can in principle be arbitrarily selected, it will appear clear that the best efficiency is achieved when N is exactly equal to M, M being the number of symbols that can be stored in each entry of the buffer memory, which is typically a power of 2. A good efficiency can be achieved also when N is selected as a sub-multiple of M, like for example M/2 or M/4, in the event that M is a power of 2. A choice of N not being M or a divider thereof is impractical because it involves a lower efficiency.
- N is also a divider of R, so that the block of R x C symbols is partitioned into R/N sub-blocks of N x C symbols: in this event accesses to the buffer memory can take place according to a relatively simple scheme.
- N it is also possible for N not to be a divider of R, in which case the last sub-block contains less than N x C symbols, namely (R MOD N) x C, and consequently in the last iteration of the method the table is not filled completely.
- claims 1 and 6 can be applied respectively for the deinterleaving and the interleaving according to Blu-Ray Disc.
- the block is an ECC cluster
- R is equal to 248
- C is equal to 304.
- N can be advantageously selected as equal to 16.
- the table used for the shuffling consists of 16 x 304 bytes instead of 248 x 304, therefor allowing for a reduction of more than 90% of the memory size, with consequent reductions in required area and cost.
- Fig. 1 shows a digital communication system
- Fig. 2 shows a system for the read-out of an information carrier
- Fig. 3 shows how symbols of a block are deinterleaved in a method of deinterleaving according to the invention
- Fig. 4 shows a device for deinterleaving symbols of a block according to the invention
- Fig. 5 shows an ECC cluster
- Figs. 6a, 6b and 6c show how symbols of a block are deinterleaved in a further embodiment of the method of deinterleaving according to the invention
- Figs. 7a - 7k show how symbols of a block are deinterleaved in a yet further embodiment of the method of deinterleaving according to the invention
- Fig. 8 shows how symbols of an ECC cluster are deinterleaved according to the embodiment of the method of deinterleaving explained with reference to Figs. 7a - 7k.
- Fig. 1 shows a digital communication system, comprising a transmitter 11, a receiver 12 and a channel, through which data 10, in the form of a sequence of symbols, are transmitted from the transmitter 11 to the receiver 12.
- the channel can be represented also by an information carrier 13, as shown in the Figure, as it is known from the Theory of Communications.
- the transmitter 11, or recorder comprises an encoder 14, which encodes data 10 in a form so as to be less sensitive to noise, and a modulator 15, for generating an analog signal 18 upon the data encoded, which analog signal 18 is recorded on the information carrier 13 by appropriate recording means, not shown in the Figure.
- the receiver 12, or reader comprises a demodulator 15' for demodulating a regenerated analog signal 18', regenerated from the information carrier 13 by appropriate read-out means, also not shown in the Figure, so as to reconstruct the data encoded, and a decoder 14', for decoding the data encoded reconstructed so as to obtain a replica of data 10'.
- the encoder 14 comprises an Error Correction Code (ECC) generator 16 and an interleaver 17; similarly the decoder 14' comprises a deinterleaver 17' and an error correction unit 16', for using and eventually suppressing the ECC.
- ECC Error Correction Code
- the interleaver 17 and the deinterleaver 17' perform inverse operations.
- the ECC is some redundant information, e.g. parity bytes, which can be used by the error correction unit 16' to verify the correctness of the encoded data reconstructed, and, should any symbol be found to have been corrupted, to perform a correction if possible.
- the correction of corrupted symbols is possible on condition that not too many symbols close to each other are corrupted.
- Corruption of symbols due to white noise present in the transmission channel, i.e. a noise randomly and evenly likely to corrupt any symbol of a sequence transmitted, irrespectively one of another, can in general be remedied by use of the ECC; in contrast the ECC alone is generally not a remedy to burst errors, i.e. the corruption of a plurality of symbols adjacent in the sequence transmitted.
- the error correction needs to be combined with interleaving/deinterleaving.
- the operation of interleaving changes the original order of the sequence of symbols so as to obtain that adjacent symbols according to the original order are well apart in the sequence transmitted over the channel, and vice versa, while the inverse operation of deinterleaving, which takes place at the receiver side, reestablishes the original order.
- the symbols of a sub-sequence of symbols which might be corrupted by a burst errors during the transmission are spread apart by the deinterleaving, i.e. re-establishing the original order, allowing the usual error correction measures to be effective also in this circumstance.
- Fig. 2 shows a system for the read-out of an information carrier, comprising an accessing unit 20 and a host device 24, connected to each other by a bus 23.
- the accessing unit 20, often referred to as "drive”, is capable of retrieving the data recorded on the information carrier 13 and storing them on a buffer memory 22, where they are available to the host device 24 for rendering.
- the buffer memory 22 and a receiver 12 are parts of the accessing unit 20.
- the host device 24 may be a PC; as an alternative the accessing unit 20 and a host device 24 may be integrated in a consumer electronic apparatus such as a disc player.
- the presence of the buffer memory 22 allows decoupling the retrieval of the data recorded on the information carrier 13 from the rendering. In fact the retrieval typically takes place at a relatively low but steady rate, while the rendering can advantageously take place by means of "transfer packages", i.e. periods of relatively high data transfer, interleaved by periods in which the bus 23 is idle.
- a readout signal 18' is generated by readout means, not shown in the Figure, from the information carrier 13.
- This readout signal 18' is converted by the demodulator 15' into a sequence, or stream, of symbols 21, which stream of symbols 21 is fed to the deinterleaver 17'.
- a scheme of interleaving/deinterleaving is defined in the order of the symbols during transmission, i.e. the rearranged order, in contrast to the original order of the same symbols. According to a possible scheme of interleaving/deinterleaving, and to a known method of deinterleaving therefore, in the deinterleaver 17' blocks of R x C symbols of the stream of symbols 21 are rearranged by using a memory table of R rows and C columns.
- the symbols are temporarily stored in the table, in the same order as they are provided in the stream of symbols 21 produced by the demodulator 15', in a row by row order; when a whole block has been stored and the table is full, the symbols stored in the table are fetched, or read out, on a column by column order: the groups of symbols fetched in the columns are stored in the buffer memory 22 in the same order as they are read from the table.
- Fig. 3 shows how symbols of a block are deinterleaved in a method of deinterleaving according to the invention.
- the symbols are numbered from 0 to 47, according to the order with which they are received for example from the demodulator 15', i.e. the number associated to each symbol is the position index i.
- i c x R + r
- r j DIV C
- a first sub-block 32 of N x C symbols, that is 12 symbols, of the block of symbols 30 is stored in the table 31 in a row by row order, that is first the 0 th row, and subsequently the 1 st row, the 2 nd row and the 3 rd row; after having been completely filled, the table 31 is read in a column by column order, that is first the 0 th column, and subsequently the 1 st column, and the 2 nd column; the groups of N, in this case 4, symbols read from each column are stored in the buffer memory 22, at locations having a distance of R symbols from one another, so as to leave a gap for R-N, in this case 12, symbols between a group and another.
- the groups of 4 symbols read from each column are stored in the buffer memory 22 for example in the entries n, n+4 and n+8.
- a second sub-block 33 of N x C symbols are stored in the table 31 in a row by row order; then the table 31 is read in a column by column order, the groups of N symbols read from each column are stored in the buffer memory 22, at subsequent locations in respect with the groups of N symbols of the first sub-block, that is in the entries n+1, n+5 and n+9.
- a third sub-block 34, and a fourth and last sub-block 35 are dealt with similarly so as to obtain the entire block of symbols 30 reordered in the buffer memory 22.
- Fig. 4 shows a schematic view of a device for deinterleaving or deinterleaver according to the invention.
- the deinterleaver 17' is connected to a buffer memory 22 and comprises: a table 31 of N rows and C columns, - a front-end logic unit 40 for storing sub-blocks of N x C symbols of the block in the table 31 in a row by row order, and a rearrangement logic unit 41 for fetching in a column by column order groups of N symbols from in the columns of the table 31, and storing them in the buffer memory 22, so that they appear in the buffer memory 22 according to the rearranged order.
- a device is preferably implemented as an Integrated Circuit or as a part of an Integrated Circuit responsible for the whole decoding, that is comprising also the demodulation and error correction.
- Such a device can be comprised in an apparatus for accessing an information carrier 13. Further, such a deinterleaver, and the corresponding interleaver can be implemented as integral and sharing the same resources, particularly the same table or tables.
- the rearrangement logic can be implemented as a combination of wired logic and IC firmware and/or software.
- the front-end logic is preferably implemented with wired logic only. It has to be outlined that as table 31 it is essentially intended a bi-dimensional memory structure, wherein each element of the table is identified by two indexes. It is absolutely irrelevant which of the two indexes is associated to the rows and which is associated to the columns: therefore the methods and devices according to the invention can also be described by swapping the references to rows and columns.
- Fig. 5 shows an ECC cluster, according to the BD standard.
- the ECC cluster consists of 248 x 304 bytes, and can be represented as a table of 248 rows x 304 columns.
- the first 216 rows contain data bytes whereas the remaining 32 rows contain parity bytes.
- the ECC cluster comprises 32 Data Frames 50 of 2052 bytes each, that is nine and a half columns each.
- the data frames 50 are the data structures used by an application running on a host device 24.
- N is selected equal to 16: this implies the use of two tables of 16 x 304 bytes instead, allowing for a reduction of the memory size by a factor 15 approximately.
- N that is 16, is not a divider of R, that is 248, the last sub- block fills incompletely the table, that is only 8 rows: care has to be taken when transferring the content of the rows to the buffer memory 22.
- this situation can be handled by copying the entire rows in adequate entries of the buffer memory 22, allowing for the presence of 8 non-meaningful or dummy bytes to be copied in the buffer memory 22.
- An application residing on the host device 24 needs to be adapted to ignore said dummy bytes when accessing the deinterleaved bytes in the buffer memory.
- the method according to the invention can be applied for the storage in the buffer memory of the 216 rows of data bytes only, while 32 rows of parity byte can be stored in a different memory or can be handled directly for the error correction.
- the deinterleaving of symbols received as part of a continuously incoming stream of symbols is accomplished with a single table.
- the N rows ofthe table are partitioned into P N groups
- the C columns ofthe table are assigned to Pc groups
- the incoming symbols are stored in the table like in a circular buffer, that is after having filled the last row, the first row is filled again
- the stored symbols are fetched from the table like from a circular buffer, that is after having read the last column, the first column is read again, after a group of rows has been filled, a corresponding group of columns, and, possibly, the columns subsequent to the columns ofthe corresponding group of columns are read, entirely or partly, and the symbols fetched are stored at
- the columns ofthe first group are columns 0, 1 and 2
- the columns ofthe second group are columns 3, 4 and 5,
- the rows ofthe first group are rows 0, 1, 2 and 3, the rows ofthe second group are rows 4, 5, 6 and 7.
- the first group of rows is written; subsequently the first group of columns is read and the content is transferred to the buffer memory 22.
- the situation after completion of the first step is shown in Fig. 6a.
- the barred symbols are to indicate symbols that have been copied to the buffer memory 22 at the time when the first step is completed.
- a second step the second group of rows is written; subsequently the second group of columns is read and the content is transferred to the buffer memory 22.
- the situation after completion of the second step is shown in Fig. 6b.
- the barred symbols are to indicate symbols that have been copied to the buffer memory 22 at the time when the second step is completed.
- a third step since the table has been completely filled in the previous step, the first group of rows is overwritten, subsequently the first group of columns is read and the content is transferred to the buffer memory 22.
- the situation after completion of the third step is shown in Fig. 6c. It is clear how the method is continued to obtain the deinterleaving of a block and various subsequent blocks.
- the access to the buffer memory 22 has been less efficient since entries of the buffer memory have been written only partly and groups of N symbols have been written in some cases across two entries. This loss in efficiency however can be accepted in certain situations if compared to the benefit of further reduction in memory size.
- M the number of symbols per entry of the buffer memory 22, is also 4,
- N 4
- S 2
- the columns of the first group are columns 1 and 3
- the columns of the second group are columns 0 and 2
- the rows of the first group are rows 0, and 1
- the rows of the second group are rows 2 and 3
- the rows of the extension table form a third group of rows, and are herein labeled as rows 4 and 5.
- FIG. 7a shows the sequence of 40 symbols 70, the full-scale table 71 of 10 rows by 4 columns to be used for deinterleaving, and a buffer memory 22 where the symbols are stored in the deinterleaved order.
- a table 72 of (N + S) x C, that is 6 rows x 4 columns is used.
- a first step the first group of rows is written, bringing the table 72 in the situation shown in Fig 7b. Subsequently the symbols present in rows 0 and 1 of the first group of columns are read and transferred to the buffer memory 22: the situation after completion of the first step is shown in Fig. 7c, where the barred symbols in the table 72 are to indicate symbols that have been copied to the buffer memory 22.
- a second step the second group of rows is written, bringing the table 72 in the situation shown in Fig 7d. Subsequently the symbols present in rows 0 to 3 of the second group of columns are read and transferred to the buffer memory 22: the situation after completion of the second step is shown in Fig. 7e.
- a third step rows 4 and 5 are written, bringing the table 72 in the situation shown in Fig 7f. Subsequently the symbols present in rows 2 to 5 of the first group of columns are read and transferred to the buffer memory 22: the situation after completion of the third step is shown in Fig. 7g.
- a fourth step since the table 72 has been completely filled in the previous step, the first group of rows is overwritten, bringing the table 72 in the situation shown in Fig 7h. Subsequently the symbols present in rows 4, 5, 0 and 1 of the second group of columns are read and transferred to the buffer memory 22: the situation after completion of the fourth step is shown in Fig. 7i.
- a fifth step the second group of rows is written, bringing the table 72 in the situation shown in Fig 7j. Subsequently the symbols present in rows 0 to 3 of the first group of columns are read and transferred to the buffer memory 22: the situation after completion of the fifth step is shown in Fig. 7k.
- a sixth and conclusive step the symbols present in rows 2 and 3 of the second group of columns are read and transferred to the buffer memory 22, thereby accomplishing the desired deinterleaving as shown in Fig. 7a.
- an extension table has been used to facilitate the fetching of groups of 4 symbols, however it has to be outlined that the use of an extension table can be dispensed with.
- S can advantageously be chosen as N / P N , or a multiple thereof.
- the rows of the first group are rows 0 to 3
- the rows of the second group are rows 4 to 7
- the rows of the third group are rows 8 to 11
- the rows of the fourth group are rows 12 to 15,
- the rows of the extension table form a fifth group and are herein labeled rows 16 to 19,
- the columns of the first group, named group A are all columns for which column nr MOD 19 is equal to 10,12,14,16,18, column nr being the column index, varying between 0 and 303
- the columns of the second group, named group B are all columns for which column nr MOD 19 is equal to 1, 3, 5, 7, 9* the columns of the third group, named group C, are all columns for which column nr MOD 19 is equal to 9*,11, 13, 15, 17
- the columns of the fourth group, named group D are all columns for which column nr MOD 19 is equal to 0, 2, 4, 6, 8
- FIG. 8 an ECC cluster is shown, where columns are marked as A, B, C or D, according to the group to which they belong.
- the first four rows, rows 0 - 3, at the beginning of the cluster are stored in rows 0 - 3 in the table; then the bytes in these four rows of the table that belong to column subset A are read column by column from the table and sent to the memory buffer, where they are stored in the adequate locations, i.e. according to the deinterleaved order to be achieved. Since these groups only comprise 4 bytes, instead of 16, some extra dummy bytes are added, like any other time a group smaller that 16 bytes is transferred to the memory buffer. These dummy bytes however are not effectively written to the buffer: a mask can be used to prevent that they are written to the buffer. Then the next four rows of the ECC cluster, rows 4 -7, are stored in rows 4 - 7 of the table; then the bytes in rows 0 - 8 of the table that belong to column subset B are transferred to the memory buffer.
- rows 8 - 11 are stored in rows 8 -
- rows 12 - 15 are stored in rows
- fetching symbols from a group of columns, corresponding to a group or rows already written takes place at the same time when the subsequent group of rows is written. For example while the bytes in rows 0 - 15 of the table that belong to column subset D are fetched from the table, rows 16 - 19 of the table are being filled.
- rows 20 - 23, of the cluster are stored in rows 0 - 3 of the table; then the bytes in rows 8 - 19, 0 - 3 of the table that belong to column subset B are transferred to the memory buffer.
- These groups comprise exactly 16 bytes, and are effectively put in one entry of the buffer memory.
- rows 24 - 27, of the cluster are stored in rows 4 - 7 of the table; then the bytes in rows 12 - 19, 0 - 7 of the table that belong to column subset C are transferred to the memory buffer.
- These groups comprise exactly 16 bytes, and are effectively put in one entry of the buffer memory.
- the 4 EDC bytes of the 16 even dataframes can be transferred to the buffer or alternatively to some intermediate memory. This may give rise to holes of 12 dummy bytes at the end of a dataframe in the buffer, which can anyway be used for status information of the dataframe.
- This process is repeated until the row 215, when the bytes of column subset B, corresponding to rows 200 to 215 of the ECC cluster, are transferred to the buffer memory. This operation can easily be extended to the 32 rows of the parity bytes for syndrome calculation or any other reason.
- All the remaining bytes of the ECC cluster are at this point in the table and can be transferred to the buffer memory: first the groups of 12 bytes in columns of the group C, then the groups of 8 bytes in columns of the group D, last the groups of 4 bytes in columns of the group A.
- the method presented hereinabove achieves that byte 0 of the odd dataframes is the first in a group of N bytes transferred, and is nicely aligned with the entries, so that no dummy bytes or wholes at the beginning of a dataframe in the buffer are generated.
- the extension table can contain 5 rows instead of 4 to facilitate the synchronization of storing bytes in the table and fetching bytes from the table.
- This additional row can be used for storing some incoming bytes when the locations where the incoming bytes should be stored have not been freed yet.
- a possible way to use this additional row is that the whole table is indeed used as a circular buffer as far as rows are concerned.
- the invention can be summarized as follows. Interleaving improves noise rejection in digital communication and storage systems. According a known scheme, the interleaving/deinterleaving is achieved by storing symbols in a temporary memory table of R rows x C columns in a row by row order, and reading them in a column by column order, or vice versa, so obtaining a rearranged order. Methods and devices for interleaving and deinterleaving are proposed which accomplish the same interleaving/deinterleaving operation with a reduced size of the temporary memory table.
- the rearrangement of the symbols according to the rearranged order is accomplished by using a table with a reduced memory size, in combination with the order with which the symbols are fetched from or stored in a further memory.
- the invention further relates to ICs and apparatuses for interleaving and/or deinterleaving.
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Abstract
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Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP06710822A EP1851861A2 (en) | 2005-02-14 | 2006-02-03 | Block interleaving with memory table of reduced size |
| JP2007554700A JP4891927B2 (en) | 2005-02-14 | 2006-02-03 | Block interleaving with reduced size memory tables |
| US11/815,883 US7840859B2 (en) | 2005-02-14 | 2006-02-03 | Block interleaving with memory table of reduced size |
| CN2006800049007A CN101120508B (en) | 2005-02-14 | 2006-02-03 | Method and apparatus for interleaving or deinterleaving |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP05101058 | 2005-02-14 | ||
| EP05101058.5 | 2005-02-14 |
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| Publication Number | Publication Date |
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| WO2006085251A2 true WO2006085251A2 (en) | 2006-08-17 |
| WO2006085251A3 WO2006085251A3 (en) | 2006-10-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/IB2006/050365 Ceased WO2006085251A2 (en) | 2005-02-14 | 2006-02-03 | Block interleaving with memory table of reduced size |
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|---|---|
| US (1) | US7840859B2 (en) |
| EP (1) | EP1851861A2 (en) |
| JP (1) | JP4891927B2 (en) |
| KR (1) | KR20070102753A (en) |
| CN (1) | CN101120508B (en) |
| TW (1) | TW200705828A (en) |
| WO (1) | WO2006085251A2 (en) |
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| WO2009014403A3 (en) * | 2007-07-26 | 2009-03-19 | Samsung Electronics Co Ltd | Device for processing streams and method thereof |
| FR2955001A1 (en) * | 2010-01-06 | 2011-07-08 | St Microelectronics Grenoble 2 | METHOD AND DEVICE FOR LINE AND COLUMN INTERLACING FOR BLOCKS OF VARIABLE SIZE |
| KR101185868B1 (en) | 2008-03-28 | 2012-09-25 | 콸콤 인코포레이티드 | De-interleaving mechanism involving a multi-banked llr buffer |
| WO2023046533A1 (en) | 2021-09-22 | 2023-03-30 | Airbus Defence And Space Sas | Device and method for interleaving data blocks for an optical communications system between a satellite and an earth station |
| EP4325726A1 (en) * | 2022-08-19 | 2024-02-21 | Kabushiki Kaisha Toshiba | Interleave circuit and communication device |
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|---|---|---|---|---|
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| CN101681282A (en) | 2006-12-06 | 2010-03-24 | 弗森多系统公司(dba弗森-艾奥) | Apparatus, system and method for shared, front-end, distributed RAID |
| US9116823B2 (en) * | 2006-12-06 | 2015-08-25 | Intelligent Intellectual Property Holdings 2 Llc | Systems and methods for adaptive error-correction coding |
| US9519540B2 (en) | 2007-12-06 | 2016-12-13 | Sandisk Technologies Llc | Apparatus, system, and method for destaging cached data |
| US7836226B2 (en) | 2007-12-06 | 2010-11-16 | Fusion-Io, Inc. | Apparatus, system, and method for coordinating storage requests in a multi-processor/multi-thread environment |
| CA3015223C (en) * | 2009-07-30 | 2020-09-15 | Ibiquity Digital Corporation | Systems, methods, and computer readable media for digital radio broadcast receiver memory and power reduction |
| WO2013089749A1 (en) | 2011-12-15 | 2013-06-20 | Intel Corporation | Methods to optimize a program loop via vector instructions using a shuffle table and a mask store table |
| CN105377114A (en) * | 2013-10-03 | 2016-03-02 | 王康怀 | Robust storage and transmission of capsule images |
| US10201026B1 (en) | 2016-06-30 | 2019-02-05 | Acacia Communications, Inc. | Forward error correction systems and methods |
| US10802907B2 (en) * | 2018-03-20 | 2020-10-13 | Micron Technology, Inc. | Hierarchical buffering scheme to normalize non-volatile media raw bit error rate transients |
| US10381073B1 (en) | 2018-03-20 | 2019-08-13 | Micron Technology, Inc. | Converged structure supporting buffering of recent writes and overwrite disturb remediation |
| US10505676B1 (en) | 2018-08-10 | 2019-12-10 | Acacia Communications, Inc. | System, method, and apparatus for interleaving data |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3335409A (en) * | 1964-06-25 | 1967-08-08 | Westinghouse Electric Corp | Permutation apparatus |
| US4394642A (en) * | 1981-09-21 | 1983-07-19 | Sperry Corporation | Apparatus for interleaving and de-interleaving data |
| US5530934A (en) * | 1991-02-02 | 1996-06-25 | Vlsi Technology, Inc. | Dynamic memory address line decoding |
| JP2940196B2 (en) | 1991-02-08 | 1999-08-25 | ソニー株式会社 | Recording and playback device |
| US5537420A (en) * | 1994-05-04 | 1996-07-16 | General Instrument Corporation Of Delaware | Convolutional interleaver with reduced memory requirements and address generator therefor |
| US5559506A (en) * | 1994-05-04 | 1996-09-24 | Motorola, Inc. | Method and apparatus for encoding and decoding a digital radio signal |
| US5946357A (en) * | 1997-01-17 | 1999-08-31 | Telefonaktiebolaget L M Ericsson | Apparatus, and associated method, for transmitting and receiving a multi-stage, encoded and interleaved digital communication signal |
| US6088760A (en) | 1997-03-07 | 2000-07-11 | Mitsubishi Semiconductor America, Inc. | Addressing system in a multi-port RAM having main and cache memories |
| TW334533B (en) | 1997-06-28 | 1998-06-21 | United Microelectronics Corp | The control circuit apparatus for CD-ROM optical disk driver |
| KR100306282B1 (en) * | 1998-12-10 | 2001-11-02 | 윤종용 | Apparatus and for interleaving and deinterleaving frame date in communication system |
| US6678843B2 (en) * | 1999-02-18 | 2004-01-13 | Interuniversitair Microelektronics Centrum (Imec) | Method and apparatus for interleaving, deinterleaving and combined interleaving-deinterleaving |
| EP1039646A1 (en) * | 1999-03-05 | 2000-09-27 | Mitsubishi Electric France | Interleaver device and method for interleaving a data set |
| EP1089439A1 (en) * | 1999-09-28 | 2001-04-04 | TELEFONAKTIEBOLAGET L M ERICSSON (publ) | Interleaver and method for interleaving an input data bit sequence using a coded storing of symbol and additional information |
| KR100416057B1 (en) * | 2000-08-23 | 2004-01-31 | 주식회사 대우일렉트로닉스 | Interleaving method for short burst error correction control in the high density DVD |
| JP3752995B2 (en) * | 2000-09-27 | 2006-03-08 | 日本ビクター株式会社 | Information recording / reproducing device |
| KR100370239B1 (en) * | 2000-10-25 | 2003-01-29 | 삼성전자 주식회사 | Memory device for applying to high speed block pipelined reed-solomon decoder and method of memory access and reed-solomon decoder having the memory device |
| EP1537672A1 (en) * | 2002-09-09 | 2005-06-08 | Telefonaktiebolaget LM Ericsson (publ) | Speed and memory optimised interleaving |
| US7386766B2 (en) * | 2004-03-05 | 2008-06-10 | Thomson Licensing | Address generation apparatus for turbo interleaver and deinterleaver in W-CDMA systems |
-
2006
- 2006-02-03 EP EP06710822A patent/EP1851861A2/en not_active Ceased
- 2006-02-03 KR KR1020077020918A patent/KR20070102753A/en not_active Ceased
- 2006-02-03 US US11/815,883 patent/US7840859B2/en not_active Expired - Fee Related
- 2006-02-03 CN CN2006800049007A patent/CN101120508B/en not_active Expired - Fee Related
- 2006-02-03 WO PCT/IB2006/050365 patent/WO2006085251A2/en not_active Ceased
- 2006-02-03 JP JP2007554700A patent/JP4891927B2/en not_active Expired - Fee Related
- 2006-02-10 TW TW095104483A patent/TW200705828A/en unknown
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|---|---|---|---|---|
| US8458554B2 (en) | 2007-07-26 | 2013-06-04 | Samsung Electronics Co., Ltd. | Device for processing streams and method thereof |
| WO2009014403A3 (en) * | 2007-07-26 | 2009-03-19 | Samsung Electronics Co Ltd | Device for processing streams and method thereof |
| US8489963B2 (en) | 2007-07-26 | 2013-07-16 | Samsung Electronics Co., Ltd. | Device for processing streams and method thereof |
| KR101185868B1 (en) | 2008-03-28 | 2012-09-25 | 콸콤 인코포레이티드 | De-interleaving mechanism involving a multi-banked llr buffer |
| US8812917B2 (en) | 2010-01-06 | 2014-08-19 | Stmicroelectronics (Grenoble 2) Sas | Method and device for row and column interleaving of blocks of variable size |
| EP2343811A1 (en) * | 2010-01-06 | 2011-07-13 | STMicroelectronics (Grenoble 2) SAS | Method and apparatus for variable size block row-column interleaving |
| FR2955001A1 (en) * | 2010-01-06 | 2011-07-08 | St Microelectronics Grenoble 2 | METHOD AND DEVICE FOR LINE AND COLUMN INTERLACING FOR BLOCKS OF VARIABLE SIZE |
| WO2023046533A1 (en) | 2021-09-22 | 2023-03-30 | Airbus Defence And Space Sas | Device and method for interleaving data blocks for an optical communications system between a satellite and an earth station |
| EP4325726A1 (en) * | 2022-08-19 | 2024-02-21 | Kabushiki Kaisha Toshiba | Interleave circuit and communication device |
| CN117595965A (en) * | 2022-08-19 | 2024-02-23 | 株式会社东芝 | Interleaving circuits and communication devices |
| JP2024027962A (en) * | 2022-08-19 | 2024-03-01 | 株式会社東芝 | Interleaving circuits and communication devices |
| JP7739238B2 (en) | 2022-08-19 | 2025-09-16 | 株式会社東芝 | Interleave circuit and communication device |
| US12517826B2 (en) | 2022-08-19 | 2026-01-06 | Kabushiki Kaisha Toshiba | Interleave circuit and communication device |
Also Published As
| Publication number | Publication date |
|---|---|
| US20080270714A1 (en) | 2008-10-30 |
| JP4891927B2 (en) | 2012-03-07 |
| EP1851861A2 (en) | 2007-11-07 |
| CN101120508A (en) | 2008-02-06 |
| TW200705828A (en) | 2007-02-01 |
| CN101120508B (en) | 2012-10-10 |
| US7840859B2 (en) | 2010-11-23 |
| JP2008530885A (en) | 2008-08-07 |
| KR20070102753A (en) | 2007-10-19 |
| WO2006085251A3 (en) | 2006-10-19 |
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