WO2006122084A2 - Sepic synchronous rectification - Google Patents

Sepic synchronous rectification Download PDF

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Publication number
WO2006122084A2
WO2006122084A2 PCT/US2006/017844 US2006017844W WO2006122084A2 WO 2006122084 A2 WO2006122084 A2 WO 2006122084A2 US 2006017844 W US2006017844 W US 2006017844W WO 2006122084 A2 WO2006122084 A2 WO 2006122084A2
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WO
WIPO (PCT)
Prior art keywords
power converter
converter
output
transistor
sepic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/017844
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French (fr)
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WO2006122084A3 (en
Inventor
Joseph D. Remson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Igo Inc
Original Assignee
Mobility Electronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mobility Electronics Inc filed Critical Mobility Electronics Inc
Publication of WO2006122084A2 publication Critical patent/WO2006122084A2/en
Publication of WO2006122084A3 publication Critical patent/WO2006122084A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1588—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load comprising at least one synchronous rectifier element
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/1557—Single ended primary inductor converters [SEPIC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention is generally related to power converters, and more particularly to SEPIC converters.
  • the present invention achieves technical advantages as a SEPIC converter having synchronous rectification.
  • the converter accommodates changes in the converter duty cycle, and the ringing conditions when the converter changes operation from a continuous mode to a discontinuous mode, and back. Conductive losses are significantly reduced.
  • Figure 1 is an electrical schematic of one embodiment of the invention
  • Figure 2 is a waveform diagram showing voltages at various nodes of the schematic of Figure 1 with a light load.
  • Figure 3 is a waveform diagram showing voltages at various nodes of the schematic of Figure 1 with a heavy load.
  • FIG. 1 there is shown a SEPIC converter 10 according to one embodiment of the invention.
  • Inductor Ll, indicator L2, capacitor Cl, transistor Ql, transistor Q3 and associated body diode, and capacitor C5 form a classic SEPIC converter shown at 12.
  • the voltage at the junction Jl of capacitor Cl, inductor Ll and the drain of transistor Q3 tend to ring, as shown in the waveform diagram at 20 in Figure 2 for a light load.
  • the first positive going pulse contains almost all of the transferable energy. The remaining pulses are low energy ringing.
  • amplifier Ul, diode Dl, resistor Rl, diode D2, resistor R2, resistor R6, resistor RlO, resistor RIl, capacitor C4 and transistor Q4 form a dual slope integrator shown at 14.
  • the integrator 14 captures the gate on-time at control line 16, and then uses this gate on-time to capture the energy in the inductance of inductor Ll. If transistor Q3 is turned on when the voltage at its drain is less than the voltage at its source, capacitor C5 discharges through inductor Ll. When the gate drive to transistors Ql transitions high, the output voltage at pin 1 of amplifier Ul moves in a positive direction.
  • the gate drive voltage for transistor Ql is also applied to the inverting input, pin 6, of amplifier U2.
  • This gate drive voltage is always higher than the output of amplifier Ul due to the bias network formed by resistors R7, R8 , R9 and diode D3, which forces the output of amplifier U2 to remain low while the non- inverting input to amplifier U2 is going in a positive direction, thus, insuring the transistor Q2 does not force transistor Q3 into an on condition.
  • the rising slope constant of integrator 14 is the product of capacitor C4, resistor R2 and diode D2.
  • the descending slope constant at the amplifier Ul output is the product of capacitor C4, resistor Rl and diode Dl. It is at this time that the voltage at the non-inverting input to amplifier U2, pin 7, is higher than the voltage at the inverting input, pin 6, of amplifier U2. This causes the output of amplifier U2, at pin 1, to move to a positive level that consequently causes transistor Q2 to conduct, thereby causing transistor Q3 to conduct, thereby transferring the energy at inductor Ll to the output capacitor C5.
  • the integrator 14 output descends below the voltage level at the inverting input of amplifier U2 the output of amplifier U2 returns to a low level, thereby causing transistor Q2, and subsequently transistor Q3, to stop conducting.
  • Resistors R6, RlO and RIl form a voltage divider such that integration of integrator 14 follows the gate drive voltage at 16.
  • the alternate paths for integrating "up” verses integrating "down” allow different timing for each direction of the integrator 14 to accommodate duty cycle, or timing, differences.
  • Capacitor C ⁇ and resistor R14 form a differentiation circuit, where the positive pulse created when the gate transitions high briefly turns on transistor Q4 to eliminate integration wind up. Diode D5 clips the negative going portion of the differentiated pulse.
  • circuit 10 When circuit 10 operates at high load conditions, where the duty cycle at gate drive 16 is such that capacitor C4 would never completely discharge and, as such, would eventually reach positive saturation keeping transistors Q2 and Q3 in a state of constant conduction, the non-inverting input to amplifiers U2 is biased by transistor Q4 to keep the output of circuit 10 low when the gate drive voltage is high.
  • the non-inverting input to amplifier U2 is also biased when the output of the integrator 14 has descended below the voltage level at the non-inverting input of amplifier U2 when the gate drive voltage is low.
  • transistor Q3 is advantageously- controlled to conduct for a period equal to, or slightly less than, the "on" period required to transfer the output energy stored in inductor Ll and eliminate reverse conduction through transistor Q3 when the voltage at the junction of inductor Ll, capacitor Cl, and transistor Q3's drain is less then the voltage across capacitor C5.
  • the arrangement of the forward biased body diode of transistor Q3 provides a means of charging capacitor C5 before the voltage across capacitor C5 is sufficient to support the drive circuitry for transistors Q2 and Q3, and advantageously avoids contending with the ripple voltage at the source of transistor Q3.
  • good Vgs across transistor Q3 is maintained.
  • any small amount of energy remaining in inductor Ll during the ringing is captured.
  • the output current at an output voltage equal to 15 volts, is about 6.66 amps.
  • the losses are:
  • circuit 10 realizes a 21 times reduction in conductive losses. In addition, switching losses are minimized with the body diode oriented in the direction shown. The maximum voltage across the body diode is 1.0 volts so the transistor Q3 switches when the Vds is at a minimum.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

A SEPIC converter having synchronous rectification, accommodating changes in the converter duty cycle, and the ringing conditions when the converter changes operation from a continuous mode to a discontinuous mode, and back. Conductive losses are significantly reduced.

Description

SEPIC SYNCHRONOUS RECTIFICATION
FIELD OF THE INVENTION
The present invention is generally related to power converters, and more particularly to SEPIC converters.
BACKGROUND OF THE INVENTION
Technical issues in applying synchronous rectification to a SEPIC converter include accommodating a changing duty cycle and the ringing conditions when the converter changes operation from continuous mode to discontinuous mode and back. In particular, the frequency of the ring decreases as the load decreases, and there is a decrease in the duty cycle that affects the synchronous rectification.
SUMMARY OF THE INVENTION
The present invention achieves technical advantages as a SEPIC converter having synchronous rectification. The converter accommodates changes in the converter duty cycle, and the ringing conditions when the converter changes operation from a continuous mode to a discontinuous mode, and back. Conductive losses are significantly reduced.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is an electrical schematic of one embodiment of the invention;
Figure 2 is a waveform diagram showing voltages at various nodes of the schematic of Figure 1 with a light load; and
Figure 3 is a waveform diagram showing voltages at various nodes of the schematic of Figure 1 with a heavy load.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to Figure 1, there is shown a SEPIC converter 10 according to one embodiment of the invention. Inductor Ll, indicator L2, capacitor Cl, transistor Ql, transistor Q3 and associated body diode, and capacitor C5 form a classic SEPIC converter shown at 12. As the load on the converter 10 decreases, the voltage at the junction Jl of capacitor Cl, inductor Ll and the drain of transistor Q3 tend to ring, as shown in the waveform diagram at 20 in Figure 2 for a light load. Under a light load condition at output Vout, the first positive going pulse contains almost all of the transferable energy. The remaining pulses are low energy ringing.
According to this embodiment of the present invention, amplifier Ul, diode Dl, resistor Rl, diode D2, resistor R2, resistor R6, resistor RlO, resistor RIl, capacitor C4 and transistor Q4 form a dual slope integrator shown at 14. The integrator 14 captures the gate on-time at control line 16, and then uses this gate on-time to capture the energy in the inductance of inductor Ll. If transistor Q3 is turned on when the voltage at its drain is less than the voltage at its source, capacitor C5 discharges through inductor Ll. When the gate drive to transistors Ql transitions high, the output voltage at pin 1 of amplifier Ul moves in a positive direction. The gate drive voltage for transistor Ql is also applied to the inverting input, pin 6, of amplifier U2. This gate drive voltage is always higher than the output of amplifier Ul due to the bias network formed by resistors R7, R8 , R9 and diode D3, which forces the output of amplifier U2 to remain low while the non- inverting input to amplifier U2 is going in a positive direction, thus, insuring the transistor Q2 does not force transistor Q3 into an on condition.
The rising slope constant of integrator 14 is the product of capacitor C4, resistor R2 and diode D2. When the gate drive voltage at control line 16 transitions low, the descending slope constant at the amplifier Ul output is the product of capacitor C4, resistor Rl and diode Dl. It is at this time that the voltage at the non-inverting input to amplifier U2, pin 7, is higher than the voltage at the inverting input, pin 6, of amplifier U2. This causes the output of amplifier U2, at pin 1, to move to a positive level that consequently causes transistor Q2 to conduct, thereby causing transistor Q3 to conduct, thereby transferring the energy at inductor Ll to the output capacitor C5. When the integrator 14 output, the output of amplifier Ul, descends below the voltage level at the inverting input of amplifier U2 the output of amplifier U2 returns to a low level, thereby causing transistor Q2, and subsequently transistor Q3, to stop conducting.
Resistors R6, RlO and RIl form a voltage divider such that integration of integrator 14 follows the gate drive voltage at 16. The alternate paths for integrating "up" verses integrating "down" allow different timing for each direction of the integrator 14 to accommodate duty cycle, or timing, differences.
Capacitor Cβ and resistor R14 form a differentiation circuit, where the positive pulse created when the gate transitions high briefly turns on transistor Q4 to eliminate integration wind up. Diode D5 clips the negative going portion of the differentiated pulse.
When circuit 10 operates at high load conditions, where the duty cycle at gate drive 16 is such that capacitor C4 would never completely discharge and, as such, would eventually reach positive saturation keeping transistors Q2 and Q3 in a state of constant conduction, the non-inverting input to amplifiers U2 is biased by transistor Q4 to keep the output of circuit 10 low when the gate drive voltage is high. The non-inverting input to amplifier U2 is also biased when the output of the integrator 14 has descended below the voltage level at the non-inverting input of amplifier U2 when the gate drive voltage is low.
In this manner, transistor Q3 is advantageously- controlled to conduct for a period equal to, or slightly less than, the "on" period required to transfer the output energy stored in inductor Ll and eliminate reverse conduction through transistor Q3 when the voltage at the junction of inductor Ll, capacitor Cl, and transistor Q3's drain is less then the voltage across capacitor C5. The arrangement of the forward biased body diode of transistor Q3 provides a means of charging capacitor C5 before the voltage across capacitor C5 is sufficient to support the drive circuitry for transistors Q2 and Q3, and advantageously avoids contending with the ripple voltage at the source of transistor Q3. Advantageously, in this manner, good Vgs across transistor Q3 is maintained. In addition, any small amount of energy remaining in inductor Ll during the ringing is captured.
Example
When using the circuit 10 in a typical application, such as a 100 Watt inverter, the output current, at an output voltage equal to 15 volts, is about 6.66 amps. Using 1.0 volt as a typical forward drop for power diodes, the losses are:
7 6.66 (amps) * 1.0 (volt) * 0.65 (Duty Cycle) = 4.33 watts.
Using a 75.0 volt Vdss, 0.0063 Ω Rdson MOSFET transistor, the power losses are:
(6.66)2 amps * 0.011 Ω (Rdson hot) * 0.65 (Duty cycle) = 0.317 watts.
Use of the circuit 10 realizes a 21 times reduction in conductive losses. In addition, switching losses are minimized with the body diode oriented in the direction shown. The maximum voltage across the body diode is 1.0 volts so the transistor Q3 switches when the Vds is at a minimum.
6.66 (amps) * 1.0 (volt) * 25 nsec * 50,000 Hz * 2= 0.02 watts.
Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.

Claims

WE CLAIM:
1. A power converter comprising: a SEPIC power converter circuit having an input adapted to receive an input signal and providing an output signal at an output, the circuit having a duty cycle, and further comprising a synchronous rectifier responsive to changes in the duty cycle.
2. The power converter of Claim 1, wherein the synchronous rectifier reduces ringing in the output signal when the converter changes from a continuous mode to a discontinuous mode, and back.
3. The power converter of Claim 2, wherein a frequency of the ringing decreases as a load applied to the output decreases.
4. The power converter of Claim 1, wherein the synchronous rectifier provides a reduction in conductive losses in the converter circuit.
5. The power converter of Claim 1, wherein the synchronous rectifier comprises a dual slope integrator .
6. The power converter of Claim 5, wherein the integrator includes an inductor capturing energy.
7. The power converter of Claim 6, wherein the integrator is controlled by a gate, and captures an on-time of the gate.
10
PCT/US2006/017844 2005-05-06 2006-05-08 Sepic synchronous rectification Ceased WO2006122084A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/123,745 US7352158B2 (en) 2005-05-06 2005-05-06 SEPIC synchronous rectification
US11/123,745 2005-05-06

Publications (2)

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WO2006122084A2 true WO2006122084A2 (en) 2006-11-16
WO2006122084A3 WO2006122084A3 (en) 2007-08-30

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WO (1) WO2006122084A2 (en)

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EP2709257A2 (en) 2012-09-18 2014-03-19 Bombardier Transportation GmbH Power converter circuit and method for controlling the power converter circuit

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CN114982112A (en) * 2020-12-21 2022-08-30 三垦电气株式会社 Power supply for driving synchronous rectification element of SEPIC converter

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EP2709257A2 (en) 2012-09-18 2014-03-19 Bombardier Transportation GmbH Power converter circuit and method for controlling the power converter circuit
DE102012216691A1 (en) 2012-09-18 2014-03-20 Bombardier Transportation Gmbh Converter circuit and method for controlling the converter circuit

Also Published As

Publication number Publication date
US20060250826A1 (en) 2006-11-09
WO2006122084A3 (en) 2007-08-30
US7352158B2 (en) 2008-04-01

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