WO2006127586A3 - Methods for forming arrays of small, closely spaced features - Google Patents

Methods for forming arrays of small, closely spaced features Download PDF

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Publication number
WO2006127586A3
WO2006127586A3 PCT/US2006/019710 US2006019710W WO2006127586A3 WO 2006127586 A3 WO2006127586 A3 WO 2006127586A3 US 2006019710 W US2006019710 W US 2006019710W WO 2006127586 A3 WO2006127586 A3 WO 2006127586A3
Authority
WO
WIPO (PCT)
Prior art keywords
methods
small
pitch
forming arrays
closely spaced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2006/019710
Other languages
French (fr)
Other versions
WO2006127586A2 (en
Inventor
Mirzafer Abatchev
Gurtej Sandhu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to JP2008513582A priority Critical patent/JP5239854B2/en
Priority to EP06770823A priority patent/EP1886340B1/en
Priority to KR1020077030224A priority patent/KR101284410B1/en
Publication of WO2006127586A2 publication Critical patent/WO2006127586A2/en
Publication of WO2006127586A3 publication Critical patent/WO2006127586A3/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4088—Processes for improving the resolution of the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Non-Volatile Memory (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.
PCT/US2006/019710 2005-05-23 2006-05-22 Methods for forming arrays of small, closely spaced features Ceased WO2006127586A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008513582A JP5239854B2 (en) 2005-05-23 2006-05-22 Method for forming an array of small, narrow space components
EP06770823A EP1886340B1 (en) 2005-05-23 2006-05-22 Methods for forming arrays of small, closely spaced features
KR1020077030224A KR101284410B1 (en) 2005-05-23 2006-05-22 Methods for forming arrays of small, closely spaced features

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/134,982 US7429536B2 (en) 2005-05-23 2005-05-23 Methods for forming arrays of small, closely spaced features
US11/134,982 2005-05-23

Publications (2)

Publication Number Publication Date
WO2006127586A2 WO2006127586A2 (en) 2006-11-30
WO2006127586A3 true WO2006127586A3 (en) 2007-04-19

Family

ID=37056521

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/019710 Ceased WO2006127586A2 (en) 2005-05-23 2006-05-22 Methods for forming arrays of small, closely spaced features

Country Status (7)

Country Link
US (3) US7429536B2 (en)
EP (1) EP1886340B1 (en)
JP (1) JP5239854B2 (en)
KR (1) KR101284410B1 (en)
CN (1) CN100547731C (en)
TW (1) TWI299526B (en)
WO (1) WO2006127586A2 (en)

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US9412591B2 (en) 2007-07-31 2016-08-09 Micron Technology, Inc. Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures

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WO2006127586A2 (en) 2006-11-30
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