WO2006138055A2 - Method of curing hydrogen silses quioxane and densification in nano-scale trenches - Google Patents
Method of curing hydrogen silses quioxane and densification in nano-scale trenches Download PDFInfo
- Publication number
- WO2006138055A2 WO2006138055A2 PCT/US2006/020851 US2006020851W WO2006138055A2 WO 2006138055 A2 WO2006138055 A2 WO 2006138055A2 US 2006020851 W US2006020851 W US 2006020851W WO 2006138055 A2 WO2006138055 A2 WO 2006138055A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- trenches
- semiconductor substrate
- film forming
- forming material
- oxidant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H10P14/6925—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
- H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6342—Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/69—Inorganic materials
- H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
- H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
- H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
Definitions
- the invention relates to a method of curing hydrogen silsesquioxane (HSQ) films in nano-scale trenches of high aspect ratios.
- a high aspect ratio in general means a narrow and deep trench. The narrower the width of the trench relative to the depth of the trench, the higher is the aspect ratio.
- the curing technique involves a three stage procedure that is carried out at three temperature ranges, in the presence of an oxidant such as moisture steam and/or nitrous oxide, and the like.
- Integrated circuit technology uses narrow trenches in semiconductor substrates to isolate circuits such as pre-metal dielectrics (PMD) and shallow trench isolations (STI). Insulating material is deposited into the trenches to form insulation layers, and to planarize the topography.
- Chemical vapor deposition (CVD) and spin-on glass deposition (SOD) are techniques typically used to fill trenches on semiconductor substrates, to form dielectric layers such as silicon dioxide (Si ⁇ 2) and silicon dioxide based layers.
- a typical CVD method involves placing a substrate in a reactor chamber where process gases are introduced and heated. This induces a series of chemical reactions that result in the deposition of a desired layer on the substrate.
- CVD methods can be used to prepare a silicon dioxide film made from silane (S1H4) or tetraethoxysilane Si(OC2H5).
- CVD processes such as atmospheric pressure CVD, low pressure CVD, or plasma enhanced CVD.
- CVD methods can suffer from the drawback that when trench dimensions approach deep submicron scale, sufficient trench filling becomes difficult. The CVD technique therefore, is not suitable for the nano-scale trench filling with high aspect ratio according to the invention.
- a solution containing a film forming material such as an HSQ resin
- a film forming material such as an HSQ resin
- spin spread to form a uniform thin film, using certain spin parameters.
- the spinnability of the solution directly influences the quality and performance of the thin film.
- the film forming material is cured.
- SOD is the technique according to the method of the present invention.
- the invention is directed to a method of filling trenches in a semiconductor substrate.
- the trenches are filled by: dispensing a film forming material on the semiconductor substrate and into the trenches; curing the dispensed film forming material in the presence of an oxidant at a first low temperature for a first predetermined period of time; curing the dispensed film forming material in the presence of an oxidant at a second low temperature for a second predetermined period of time; curing the dispensed film forming material in the presence of an oxidant at a third high temperature for a third predetermined period of time; and forming filled oxide trenches in the semiconductor substrate.
- the film forming material is a solution of hydrogen silsesquioxane, and the oxidant can be nitrous oxide, nitric oxide, moisture steam, and the like.
- the hydrogen silsesquioxane film forming material is deposited on the semiconductor substrate and into the trenches by the spin-on coating method.
- the first low temperature is from 20-25 °C to 100 °C
- the second low temperature is from 100-400 °C
- the third high temperature is from 800-900 °C.
- the filled oxide trenches in the semiconductor substrate can be densif ⁇ ed in the presence of nitrous oxide at a temperature of 400-800 0 C.
- the first, second, and third predetermined periods of time, and the time for the densification, are each 30-60 minutes.
- Figure 1 is a cross section of a Scanning Electron Microscopy (SEM) image of a film made on a patterned wafer after the film was cured and wet etched.
- SEM Scanning Electron Microscopy
- the hydrogen silsesquioxane used herein is a preceramic silicon-containing resin, more particularly, a hydridosiloxane resin containing units of the formula HSi(OH) x (OR)yOz/2- R * s independently an organic group, which when bonded to silicon through the oxygen atom, forms a hydrolyzable substituent.
- Suitable R groups include alkyl groups such as methyl, ethyl, propyl, and butyl; aryl groups such as phenyl; and alkenyl groups such as allyl or vinyl.
- the value of x is 0-2; y is 0-2; z is 1-3; and the sum of x + y + z is 3.
- These resins may be (i) fully condensed hydrogen silsesquioxane resins (HSi ⁇ 3/2) n ; (ii) resins which are only partially hydrolyzed, i.e., containing some ⁇ SiOR; and/or (iii) resins which are partially condensed, i.e., containing some ⁇ SiOH.
- the resin may contain less than about 10 percent of silicon atoms having either no hydrogen atoms or two hydrogen atoms, or oxygen vacancies, as well as ⁇ Si-Si ⁇ bonds, which can occur during their formation or handling.
- Hydrogen silsesquioxane resins are ladder or cage polymers which generally conform to the structure depicted below.
- n has a value of four or more.
- n has a bond arrangement for a silsesquioxane cubical octamer is depicted below.
- n being five or more, double-stranded polysiloxanes of indefinitely higher molecular weight are formed, which contain regular and repeated cross links in their extended structure.
- US Patent 5,010,159 (April 23, 1991), which is also incorporated herein by reference, teaches another method of hydrolyzing hydridosilanes that are dissolved in a hydrocarbon solvent, with an aryl sulfonic acid hydrate medium to form the resin.
- a solid resinous polymer in powder form can be recovered by removing the solvent.
- the solvent can be removed by distilling off the solvent at atmospheric pressure to form a concentrate containing 40-80 percent of the resin, and removing the remaining solvent under vacuum and mild heat.
- solvents which can be employed by way of example are aromatic hydrocarbons such as benzene, toluene, and xylene; alkanes such as n-heptane, hexane, octane, and dodecane; ketones such as methyl ethyl ketone and methyl isobutyl ketone (MIBK); linear polydimethylsiloxanes such as hexamethyldisiloxane, octamethyltrisiloxane, decamethyltetrasiloxane, and mixtures thereof; cyclic polydimethylsiloxanes such as octamethylcyclotetrasiloxane, decamethylcyclopentasiloxane, dodecamethylcyclohexasiloxane, and mixtures thereof; esters such as butyl acetate and isoamyl acetate; or ethers such as diethyl ether and hexyl ether
- the present invention is based on the discovery that oxidants such as nitrous oxide (N2O), nitric oxide (NO), oxygen (O2), moisture steam, and the like, when used in curing film forming materials at high temperatures, often cause the film forming material in the top portion of a nano-scale trench to become more densified than the film forming material in the bottom portion of the nano-scale trench.
- oxidants such as nitrous oxide (N2O), nitric oxide (NO), oxygen (O2), moisture steam, and the like
- N2O nitrous oxide
- NO nitric oxide
- O2 oxygen
- moisture steam and the like
- the result is that oxidation occurs in the film forming material in the top portion of the trench before the film forming material in the bottom portion of the nano-scale trench is sufficiently oxidized. This prevents the formation of a fully densified and fully filled nano-scale trench.
- the cured film forming material in the top portion of the nano-scale trench forms a dense skin layer that prevents any further penetration of the oxidant and the film forming material into the nano- scale trench.
- the film forming material in the bottom portion of the nano- scale trench cannot be fully cured to the same extent as the film forming material in the top portion of the nano-scale trench.
- Moisture steam can therefore penetrate and/or diffuse fully into the bottom portion of the nano-scale trench.
- the moisture steam oxidant can then reacts with the SiH groups in the HSQ film forming material as noted above forming silanol groups.
- the moisture steam temperature should be maintained in a sufficiently low range so that the dense skin layer does not form, yet be maintained at a range sufficient to allow the moisture steam and the film forming material to penetrate into the depth of the nano-scale trench.
- the two low temperature curing steps are followed by a third high temperature annealing step in an oxidation environment.
- third step causes the silanol groups in the film forming material to condense, and silicon oxide is formed in the nano-scale trench.
- the temperature range for the three step cure are (i) from room and/or ambient temperature of 20-25 0 C to 100 0 C for the first low temperature cure; (ii) from 100-400 °C for the second and/or soaking low temperature cure; and (iii) from 800-900 °C for the third high temperature and/or annealing cure.
- the first low temperature cure and the second and/or soaking low temperature cure are carried out in the presence of moisture steam as the preferred oxidant.
- the third high temperature and/or annealing cure is carried out in the presence of moisture steam or nitrous oxide as preferred oxidants. Other common oxidants can be used provided their use has no detrimental effect upon the resulting wafer surface.
- the filled oxide trenches in the semiconductor substrate can be further densified in the presence of nitrous oxide at a temperature of 400-800 °C.
- the time period allowed during each of the three step cures and the densification should be between 30-60 minutes.
- the substrate is a semiconductor substrate having trenches thereon.
- the semiconductor substrate is not specifically restricted, and can be any semiconductor substrate used in the manufacture of an integrated circuit.
- the substrate may be a silicon wafer.
- the film forming material is applied by spin-on deposition (SOD).
- the conditions will depend on various factors including the desired thickness of the film formed by the method, and the specific film forming material selected.
- the semiconductor substrate onto which the film forming material is deposited is spun at a speed of at least about 500 revolutions per minute (rpm) to about 6,000 rpm.
- the time for deposition is at least about 5 seconds to about 3 minutes.
- the film forming material is deposited in an amount of about 0.4 milliliters/square centimeter.
- the spin speed, spin time, and the amount of the film forming material used can be adjusted to produce a film having a desired thickness.
- the desired thickness can adjusted to about 800 nanometers.
- the method can include an optional step of removing all or a portion of the solvent after SOD and before cure.
- the solvent may be removed by any convenient means such as heating under ambient or reduced pressure.
- the solvent may be removed by heating to a temperature of at least about 250 0 C to about 400 0 C.
- the method can produce substantially crack free films of at least about 800 nanometers in thickness.
- the method can produce films having good mechanical strength.
- the method can produce films having a dielectric constant of up to about 4.
- the method can produce films comprising silicon and oxygen in amounts such that a molar ratio of silicon to oxygen is about 1 to about 2.
- the method produces films having good resistance against invasive wet etching techniques during processes to make electronic devices. For example, films can be prepared having etch resistance expressed as film loss, in the trenches of 70-100 angstroms per minute, when exposed for one minute to an aqueous solution of 200:1 hydrofluoric acid at room temperature.
- the method described above can be used to form films used as a dielectric layer in a wide variety of applications.
- the method can be used to form a pre-metal dielectric (PMD) layer, shallow trench isolation (STI), an inter-layer dielectric (ILD) layer, and a planarizing layer in an electronic device.
- PMD pre-metal dielectric
- STI shallow trench isolation
- ILD inter-layer dielectric
- planarizing layer in an electronic device.
- the method herein is illustrated in the formation of a STI layer in a dynamic random access memory (DRAM) device.
- DRAM dynamic random access memory
- a silicon wafer is provided with a plurality of ceramic gates thereon. These gates have trenches therebetween. Aspect ratios (W:D) can be 1:10, preferably 1 :8. These trenches can have widths that vary from 10-100 nanometers.
- the method herein can be used in other devices in addition to DRAM devices. For example, the method can be used to form dielectric layer in a LOGIC device or a memory device such as a DRAM, or a static random access memory (SRAM).
- SRAM static random access memory
- the method can be used to form dielectric layers in a central processing unit (CPU) device.
- a CPU can have from 10-12 dielectric layers.
- the method can also be used for trench isolation such as shallow trench isolation (STI) in LOGIC and memory devices.
- the method can be used to fill a trench or hole on a semiconductor substrate to isolate p- and n- junctions, and prevent migration of dopants.
- STI shallow trench isolation
- Example 1 was repeated using a normal oxidation cure without moisture steam at 800 0 C. No etch resistance of the film was observed. The filled material in the trenches was completely removed.
- Example 3
- Example 1 was repeated, and the cured HSQ films in the nano-scale trenches of the silicon wafer were further densified under a nitrous oxide (N2O) environment.
- N2O nitrous oxide
- the curing of the thin film of HSQ resin coated on the silicon wafer in a nitrous oxide ambient was determined using different temperatures.
- the wet etch resistance in the nano-scale trenches was determined using the same HF etch procedure in Example 1. The process time for each determination was one hour.
- Table 1 the film loss of HSQ films cured in nitrous oxide in diluted HF solutions was decreased, compared to HSQ films cured under an oxygen or nitrogen environment.
- HSQ films cured under nitrous oxide at 800 0 C had film loss comparable to that of a thermal oxide film.
- the values for thermal oxide film in Table 1 are published data in the literature. Table 1 also shows that the mechanical properties (i.e., hardness and modulus) of HSQ films cured under nitrous oxide were increased as evidences by the high values of hardness and modulus.
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- Formation Of Insulating Films (AREA)
- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP06760541A EP1891669A2 (en) | 2005-06-15 | 2006-06-12 | Method of curing hydrogen silses quioxane and densification in nano-scale trenches |
| JP2008516898A JP2008547194A (en) | 2005-06-15 | 2006-06-12 | Method to harden hydrogen silsesquioxane and make it dense in nanoscale trench |
| US11/919,109 US20090032901A1 (en) | 2005-06-15 | 2006-06-12 | Method of curing hydrogen silsesquioxane and densification in nano-scale trenches |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US69082505P | 2005-06-15 | 2005-06-15 | |
| US60/690,825 | 2005-06-15 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2006138055A2 true WO2006138055A2 (en) | 2006-12-28 |
| WO2006138055A3 WO2006138055A3 (en) | 2007-08-02 |
Family
ID=37570951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2006/020851 Ceased WO2006138055A2 (en) | 2005-06-15 | 2006-06-12 | Method of curing hydrogen silses quioxane and densification in nano-scale trenches |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20090032901A1 (en) |
| EP (1) | EP1891669A2 (en) |
| JP (1) | JP2008547194A (en) |
| KR (1) | KR20080017368A (en) |
| CN (1) | CN101185160A (en) |
| TW (1) | TW200707583A (en) |
| WO (1) | WO2006138055A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2009096603A1 (en) * | 2008-02-01 | 2011-05-26 | Jsr株式会社 | Method for forming trench isolation |
| US8349985B2 (en) | 2009-07-28 | 2013-01-08 | Cheil Industries, Inc. | Boron-containing hydrogen silsesquioxane polymer, integrated circuit device formed using the same, and associated methods |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100822604B1 (en) * | 2006-02-23 | 2008-04-16 | 주식회사 하이닉스반도체 | Device Separating Method of Semiconductor Device |
| EP2493963A1 (en) | 2009-10-28 | 2012-09-05 | Dow Corning Corporation | Polysilane - polysilazane copolymers and methods for their preparation and use |
| US10189712B2 (en) * | 2013-03-15 | 2019-01-29 | International Business Machines Corporation | Oxidation of porous, carbon-containing materials using fuel and oxidizing agent |
| KR102406977B1 (en) * | 2015-07-16 | 2022-06-10 | 삼성전자주식회사 | Methods of manufacturing semiconductor devices including isolation layers |
| TWI785070B (en) | 2017-07-31 | 2022-12-01 | 美商陶氏有機矽公司 | Silicone resin, related methods, and film formed therewith |
| CN107393864A (en) * | 2017-08-29 | 2017-11-24 | 睿力集成电路有限公司 | A kind of isolation structure and its manufacture method |
| JP7372043B2 (en) * | 2019-03-29 | 2023-10-31 | 旭化成株式会社 | Modified porous body, method for producing modified porous body, reflective material, porous sheet |
| US20230295446A1 (en) * | 2020-07-01 | 2023-09-21 | SiOx ApS | An anti-fouling treated heat exchanger and method for producing an anti-fouling treated heat exchanger |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3615272A (en) * | 1968-11-04 | 1971-10-26 | Dow Corning | Condensed soluble hydrogensilsesquioxane resin |
| US4756977A (en) * | 1986-12-03 | 1988-07-12 | Dow Corning Corporation | Multilayer ceramics from hydrogen silsesquioxane |
| US4999397A (en) * | 1989-07-28 | 1991-03-12 | Dow Corning Corporation | Metastable silane hydrolyzates and process for their preparation |
| US5010159A (en) * | 1989-09-01 | 1991-04-23 | Dow Corning Corporation | Process for the synthesis of soluble, condensed hydridosilicon resins containing low levels of silanol |
| US5145723A (en) * | 1991-06-05 | 1992-09-08 | Dow Corning Corporation | Process for coating a substrate with silica |
| US5436029A (en) * | 1992-07-13 | 1995-07-25 | Dow Corning Corporation | Curing silicon hydride containing materials by exposure to nitrous oxide |
| US5656555A (en) * | 1995-02-17 | 1997-08-12 | Texas Instruments Incorporated | Modified hydrogen silsesquioxane spin-on glass |
| US6020410A (en) * | 1996-10-29 | 2000-02-01 | Alliedsignal Inc. | Stable solution of a silsesquioxane or siloxane resin and a silicone solvent |
| JP4030625B2 (en) * | 1997-08-08 | 2008-01-09 | Azエレクトロニックマテリアルズ株式会社 | Amine residue-containing polysilazane and method for producing the same |
| KR100280106B1 (en) * | 1998-04-16 | 2001-03-02 | 윤종용 | How to form trench isolation |
| US6699799B2 (en) * | 2001-05-09 | 2004-03-02 | Samsung Electronics Co., Ltd. | Method of forming a semiconductor device |
| US6693050B1 (en) * | 2003-05-06 | 2004-02-17 | Applied Materials Inc. | Gapfill process using a combination of spin-on-glass deposition and chemical vapor deposition techniques |
| KR100673884B1 (en) * | 2003-09-22 | 2007-01-25 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device capable of protecting attack by wet cleaning |
| KR100583957B1 (en) * | 2003-12-03 | 2006-05-26 | 삼성전자주식회사 | Method of forming double damascene metal wiring by adopting sacrificial metal oxide film |
-
2006
- 2006-06-12 EP EP06760541A patent/EP1891669A2/en not_active Withdrawn
- 2006-06-12 US US11/919,109 patent/US20090032901A1/en not_active Abandoned
- 2006-06-12 CN CNA2006800185478A patent/CN101185160A/en active Pending
- 2006-06-12 KR KR1020077029377A patent/KR20080017368A/en not_active Withdrawn
- 2006-06-12 JP JP2008516898A patent/JP2008547194A/en not_active Withdrawn
- 2006-06-12 WO PCT/US2006/020851 patent/WO2006138055A2/en not_active Ceased
- 2006-06-15 TW TW095121470A patent/TW200707583A/en unknown
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2009096603A1 (en) * | 2008-02-01 | 2011-05-26 | Jsr株式会社 | Method for forming trench isolation |
| US8349985B2 (en) | 2009-07-28 | 2013-01-08 | Cheil Industries, Inc. | Boron-containing hydrogen silsesquioxane polymer, integrated circuit device formed using the same, and associated methods |
| US8613979B2 (en) | 2009-07-28 | 2013-12-24 | Cheil Industries, Inc. | Boron-containing hydrogen silsesquioxane polymer, integrated circuit device formed using the same, and associated methods |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2008547194A (en) | 2008-12-25 |
| CN101185160A (en) | 2008-05-21 |
| KR20080017368A (en) | 2008-02-26 |
| WO2006138055A3 (en) | 2007-08-02 |
| TW200707583A (en) | 2007-02-16 |
| EP1891669A2 (en) | 2008-02-27 |
| US20090032901A1 (en) | 2009-02-05 |
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