WO2007013226A1 - 受信装置およびそれを用いた電子機器 - Google Patents
受信装置およびそれを用いた電子機器 Download PDFInfo
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- WO2007013226A1 WO2007013226A1 PCT/JP2006/311505 JP2006311505W WO2007013226A1 WO 2007013226 A1 WO2007013226 A1 WO 2007013226A1 JP 2006311505 W JP2006311505 W JP 2006311505W WO 2007013226 A1 WO2007013226 A1 WO 2007013226A1
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- signal
- frequency
- frequency error
- filter
- pll
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/26—Circuits for superheterodyne receivers
- H04B1/28—Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
- H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J2200/00—Indexing scheme relating to tuning resonant circuits and selecting resonant circuits
- H03J2200/02—Algorithm used as input for AFC action alignment receiver
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J2200/00—Indexing scheme relating to tuning resonant circuits and selecting resonant circuits
- H03J2200/07—Calibration of receivers, using quartz crystal oscillators as reference
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/0028—Correction of carrier offset at passband only
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0053—Closed loops
- H04L2027/0055—Closed loops single phase
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0063—Elements of loops
- H04L2027/0065—Frequency error detectors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2657—Carrier synchronisation
Definitions
- the present invention relates to a receiving device for receiving a signal and an electronic apparatus using the receiving device.
- FIG. 8 is a circuit block diagram of a conventional receiving device.
- the receiving device includes an input terminal 1004, a receiving unit 1001 connected to the input terminal 1004, a demodulating unit 1002 connected to the output side of the receiving unit 1001, and an output side of the demodulating unit 1002. And an output terminal 1040 connected to the.
- the receiving unit 1001 includes a phase-locked loop (hereinafter abbreviated as “PLL”) 1010, a mixer 1006 that mixes the local oscillation signal from the PLL 1010 and the signal from the input terminal 1004, and the output of the mixer 1006 And a filter 1008 connected to the side.
- PLL phase-locked loop
- the PLL 1010 includes a local oscillator 1007 that supplies a local oscillation signal to the mixer 1006, a variable frequency divider 1102 that divides a local oscillation signal from the local oscillator 1007, a crystal oscillator 1012, and an input of the local oscillator 1007. And a phase comparator 1104 that compares the signal from the variable frequency divider 1102 and the signal from the crystal oscillator 1012. The output of the phase comparator 1104 is connected to the input of the local oscillator 1007 via the loop filter 1003.
- the frequency error of the signal of the crystal unit 1011 is approximately 100 ppm or less. If the reference frequency of the signal of the crystal unit 1011 is 18 MHz, for example, the range of the frequency error is as small as ⁇ 1.8 kHz.
- crystal oscillation with errors The output frequency of the local oscillation signal from the local oscillator 1007 generated based on the signal of the moving element 1011 is obtained by multiplying this error by the ratio of the output frequency of the local oscillation signal and the reference frequency of the crystal oscillator 1011 signal. Have a frequency error. Therefore, a large frequency error occurs in the output frequency of the local oscillation signal.
- the receiving device includes an input terminal, a receiving unit connected to the input terminal, a demodulating unit connected to the output side of the receiving unit, and an output terminal connected to the output side of the demodulating unit.
- the receiving unit includes a PLL, a mixer for mixing the local oscillation signal from the PLL and the signal from the input terminal, and a filter connected to the output side of the mixer.
- the demodulator has a frequency error detector that detects the frequency error of the signal from the filter.
- the PLL is a local oscillator that supplies a local oscillation signal to the mixer, and a variable frequency divider that divides the local oscillation signal from the local oscillator by a division ratio determined based on the signal from the frequency error detector.
- an oscillator, and a phase comparator connected to the input side of the local oscillator and comparing the signal of the variable frequency divider force and the signal from the oscillator.
- the receiving apparatus can reduce the frequency error of the local oscillation signal by operating the variable frequency divider based on the signal from the frequency error detector.
- the frequency error in the IF signal output from the mixer can be reduced, and the pass bandwidth of the filter for passing only the desired signal can be reduced. Therefore, the attenuation characteristic of the filter becomes steep, and the amount of attenuation of unnecessary undesired signals existing in the vicinity of the desired signal can be increased.
- the electronic device includes an input terminal, a receiving unit connected to the input terminal, and an output of the receiving unit.
- a demodulation unit connected to the output side, an output terminal connected to the output side of the demodulation unit, a signal processing unit connected to the output terminal, and a display unit connected to the signal processing unit.
- the receiving unit includes a PLL, a mixer that mixes the local oscillation signal from the PLL and the signal from the input terminal, and a filter connected to the output side of the mixer.
- the demodulator has a frequency error detector that detects the frequency error of the signal from the filter.
- the PLL also has a local oscillator that supplies the local oscillation signal to the mixer and a variable frequency divider that divides the local oscillation signal from the local oscillator by a division ratio determined based on the signal from the frequency error detector. And a phase comparator that is connected to the input side of the local oscillator and compares the signal of the variable frequency divider force and the signal of the oscillator force.
- the electronic apparatus can reduce the frequency error of the local oscillation signal by operating the variable frequency divider based on the signal from the frequency error detector.
- the frequency error in the IF signal output from the mixer can be reduced, and the pass bandwidth of the filter for passing only the desired signal can be reduced. Therefore, the attenuation characteristic of the filter becomes steep, and the amount of attenuation of unnecessary undesired signals existing in the vicinity of the desired signal can be increased.
- FIG. 1 is a block diagram of a receiving apparatus and an electronic apparatus using the receiving apparatus according to Embodiment 1 of the present invention.
- FIG. 2 is a detailed block diagram of a receiving apparatus according to Embodiment 1 of the present invention.
- FIG. 3 is a block diagram of a receiving apparatus according to Embodiment 2 of the present invention.
- FIG. 4A is a characteristic diagram of a filter whose pass bandwidth is controlled in the second embodiment of the present invention.
- FIG. 4B is a characteristic diagram of a filter in which the pass bandwidth and the slope of the attenuation characteristic are controlled in the second embodiment of the present invention.
- FIG. 5 is a block diagram of a receiving apparatus according to Embodiment 3 of the present invention.
- FIG. 6 is a block diagram of a receiving apparatus according to Embodiment 3 of the present invention.
- FIG. 7 is a block diagram of a receiving apparatus according to Embodiment 4 of the present invention.
- FIG. 8 is a block diagram of a receiving apparatus in a conventional example. Explanation of symbols
- PLL Phase-locked loop
- FIG. 1 is a block diagram of a receiving device and an electronic apparatus using the receiving device in the present embodiment
- FIG. 2 is a detailed block diagram of the receiving device.
- the present embodiment an example in which the receiving device receives a terrestrial digital broadcast signal will be described.
- the receiving device includes an input terminal 4, a receiving unit 1 connected to the input terminal 4, a demodulating unit 2 connected to the output side of the receiving unit 1, and a demodulating unit 2. And an output terminal 40 connected to the output side.
- an input terminal for inputting data of the CPU 30 for controlling them is provided.
- the electronic apparatus including the receiving device includes a signal processing unit 200 connected to the output terminal 40 and a display unit 201 connected to the signal processing unit.
- the receiving unit 1 includes an input filter (not shown), a high-frequency amplifier 5, a PLL 10, a mixer 6 that mixes a local oscillation signal from the PLL 10 and a signal from the input terminal 4, A band limiting filter 8 as a filter connected to limit the frequency band is provided on the output side of the mixer 6.
- the input filter suppresses unnecessary general frequency bands other than the television broadcast signal from a wideband received radio wave, and selects a reception signal for television.
- the high frequency amplifier 5 amplifies the signal from the input filter and then supplies it to one input of the mixer 6.
- the mixer 6 Based on the local oscillation signal from the PLL 10, the mixer 6 converts the frequency of the signal input from the input terminal 4 via the input filter and the high frequency amplifier, and outputs the IF signal to the band limiting filter 8 Output.
- the band limiting filter 8 receives the IF signal and suppresses unnecessary disturbing signals existing in the vicinity of the IF signal. Further, the output signal of the band limiting filter 8 is gain-controlled to a desired output level by a low frequency amplifier (not shown).
- the PLL 10 includes a crystal oscillator 12 to which a crystal resonator 11 is connected, and a local oscillator 7 that supplies a local oscillation signal to the mixer 6.
- the PLL 10 includes a prescaler 101 that divides the local oscillation signal from the local oscillator 7 and a band limit filter 8.
- a variable frequency divider 102 that divides the signal from the prescaler 101 based on the signal from the frequency controller 25 connected to the frequency error detector 24 of the demodulator 2 that detects the frequency error of the signal.
- the PLL 10 includes a reference divider 105 that divides the signal from the crystal oscillator 12 as an oscillator, and a phase comparator 104 that compares the signal from the reference divider 105 and the signal from the variable divider 102. And have.
- the output of the phase comparator 104 is connected to the input of the local oscillator 7 via the loop filter 13.
- the PLL 10 receives the signal from the reference frequency divider 105 and the signal from the frequency controller 25 and outputs an overflow signal (hereinafter abbreviated as “OVF signal”) to the variable frequency divider 102. It has a counter 103.
- the demodulator 2 is connected to the AD conversion (referred to as “ADJ” in the drawing) 20 connected to the output side of the band limiting filter 8 and to the output side of the AD conversion 20
- a digital filter (not shown), a multiplier 21 connected to the output side of the digital filter, a Fourier transform 22 and a demodulator 23 connected between the multiplier 21 and the output terminal 40 are provided.
- the terminal 40 outputs data such as digitally demodulated video and audio, and the demodulator 2 performs a Fourier transform on the signal from the multiplier 21 before the Fourier transform by the Fourier transform 22 and the Fourier transform.
- NCOJ numerically controlled oscillator
- the AD converter 20 converts an input analog signal into a digital signal.
- the digital filter removes interference signals.
- the multiplier 21 converts the input desired signal into a complex signal obtained by quadrature demodulation and frequency-converts it to a baseband OFDM signal from which the carrier wave component has been removed, and outputs it.
- the Fourier transformer 22 converts the time-domain data string of the input baseband OFDM signal into a frequency-domain data string.
- the demodulator 23 demodulates the frequency domain data string, that is, the digital signal data transmitted by modulating each carrier of the OFDM signal. Demodulated data is error corrected After the normal processing is performed, information such as audio and video is output via the output terminal 40.
- the correction of the carrier frequency offset is realized by the circuit of the frequency error detector 24, NC026, and multiplier 21.
- the frequency error detector 24 includes a narrowband frequency error detector 27, a wideband frequency error detector 28, and an adder 29.
- the narrowband frequency error detector 27 receives a signal from the multiplier and detects a fine frequency error within the carrier interval of the OFDM signal. That is, since the guard period signal in the OFDM signal is a copy of the rear part of the effective symbol period signal, the frequency error within the carrier interval is calculated using the correlation of these signals.
- the broadband frequency error detector 28 receives the signal from the Fourier transform 22 and detects a frequency error in a carrier interval unit.
- the frequency error in the unit of the carrier interval is calculated using the reference symbol for frequency synchronization inserted at a predetermined cycle on the transmission side.
- the adder 29 adds the detection error of the narrowband frequency error detector 27 and the detection error of the wideband frequency error detector 28, and the added frequency error data is not shown in the figure with the frequency controller 25. Output to the controller. Based on the frequency error amount detected by the frequency error detector 24, the NCO controller supplies the frequency error data corresponding to the frequency offset so that there is no frequency error, and controls the output frequency of NC026. To do. The output signal of NC026 is supplied to the other input of the multiplier 21.
- the frequency error detector 24 detects the frequency error using the signal in the guard interval period characterized by the OFDM modulation signal by the narrowband frequency error detector 27, and further detects the wideband frequency.
- the error detector 28 uses a reference symbol called pilot signal V to detect the frequency error.
- the correction of the carrier frequency offset by the frequency error detector 24, NC026, and multiplier 21 of the demodulator 2 described above is particularly important for demodulation of a desired signal that has been subjected to OFDM modulation.
- Each carrier that is orthogonal to each other like an OFDM signal is frequency multiplexed.
- the orthogonality between the carriers is lost and a large error occurs in the demodulation result. For this reason, the correction of the carrier frequency offset does not cause a large error in the demodulated output.
- the frequency controller 25 receives preset PLL tuning data from the CPU 30. Then, the frequency controller 25 supplies the result of numerical calculation using the frequency error data and the data for PLL tuning to the variable frequency divider 102 of the PLL 10 as new data for PLL tuning.
- tuning variable data “M, K” representing a frequency division ratio preset in the variable frequency divider 102 is input to the variable frequency divider 102 of the PLL 10.
- “ ⁇ , ⁇ ” are an integer frequency division ratio and a fractional frequency division ratio which are channel selection data input from the CPU 30.
- Fvco which is the local frequency of the local oscillation signal output from the local oscillator 7, is divided by N by the prescaler 101, and a signal having a frequency of FvcoZN is input to the variable frequency divider 102.
- the reference frequency signal Fxtal excited by the crystal oscillator 11 and the crystal oscillator 12 is frequency-divided by the reference frequency divider 105 whose frequency division ratio is set to NR.
- the signal having the frequency of the divided FxtalZNR is input, and the cumulative adder 103 calculates NRZFxtal which is one cycle time. Then, the fractional division ratio K set by the CPU 30 is continuously added every cycle.
- the cumulative addition result reaches a predetermined addition upper limit value of 2 m or more (m is the number of bits of the cumulative adder 103)
- the cumulative adder 103 outputs the OVF signal to the variable frequency divider 102, and Subtract 2 m for a certain cumulative added force and continue the same cumulative addition again.
- variable frequency divider 102 and the cumulative adder 103 will be described in detail.
- the cumulative adder 103 outputs the OVF signal (Expression 1) times in an arbitrary predetermined period (NRZFxtal) Xa determined for convenience.
- the frequency division ratio of the variable frequency divider 102 is set to M + l. Further, in the remaining period (Equation 2) in which the cumulative adder 103 does not output the OVF signal, the frequency division ratio of the variable frequency divider 102 is set to M.
- the phase comparator 104 supplies a signal according to the phase difference between these input signals to the local oscillator 7 as a voltage value via the loop filter 13.
- the frequency controller 25 in the present embodiment operates to correct an error.
- the operation of the frequency controller 25 will be described with reference to FIG.
- the frequency controller 25 is a new fractional frequency division ratio of the PLL 10 that outputs the local frequency Fvco of the correct local oscillator 7 at the reference frequency Fxtal * having the frequency error in order to remove the frequency error A fc of the IF signal. * Is derived by calculation. In this way, the correct IF signal frequency is obtained.
- the frequency error A fc output from the frequency error detector 24 is input to the multiplier 25a.
- the multiplier 25a multiplies the addition upper limit value “2 m ” (m is the number of bits of the cumulative adder 103) of the cumulative adder 103 of the PLL 10 and the frequency error amount “A fc”, and outputs 2 m XA fc. .
- the divider 25b uses the frequency “Fxtal” of the reference frequency signal of the PLL 10, the frequency division ratio “NR” of the reference frequency divider 105, and the frequency division ratio “N” of the prescaler 101 “( FxtalZ NR) XN ”is divided from 2 m XA fc. Then, the result is output as a correction value ⁇ for the fractional frequency division ratio K of PLL10. Therefore, the correction value ⁇ is expressed as (Equation 9).
- the output signal ⁇ of the divider 25b is input to one of the adder / subtractor 25c.
- the preset data for PLL tuning output from the CPU 30 is input to the other input of the adder / subtracter.
- the preset data is PLL10 integer division ratio “M” and fractional division ratio “K”.
- the adder / subtractor 25c inputs the integer division ratio "M" out of these input signals without performing any operation.
- IF frequency high frequency signal frequency is one local frequency.
- the direction of deviation between the IF frequency and the local frequency Fvco is opposite. For example, if the IF frequency is 550 kHz and the frequency shifts 50 kHz higher than the expected value of 500 kHz! / Speaks, the local frequency Fvco * is shifted 50 kHz lower than the expected value Fvco.
- the frequency controller 25 receives the frequency error input from the frequency error detector 24.
- a Derivation value “ ⁇ ” of PLL tuning data is derived from fc, and PLL tuning preset data ( ⁇ , ⁇ ) input from CPU30 is supplied to PLL10 of receiver 1 as ( ⁇ , ⁇ ⁇ ⁇ )
- the reception signal of the digital terrestrial broadcasting input to the input terminal 4 of the reception unit 1 is output from the output terminal 9 as the IF signal frequency.
- the input terminal 4 receives fRF (767.143 MHz) which is the channel frequency of the digital broadcast signal.
- the local frequency Fvco output from the local oscillator 7 is a frequency that is selected and controlled by the PLL 10.
- the AD converter converts the input IF signal into a digital signal also with an analog signal power.
- the multiplier 21 converts the input digital signal into a complex signal and converts it into a baseband frequency signal.
- the Fourier transform 22 converts the input time domain data string into a frequency domain data string. Both the output of the multiplier 21 and the output of the Fourier transformer 22 are input to the frequency error detector 24, and the frequency error A fc of the IF signal detected by the frequency error detector 24 is obtained as —76.664 kHz, It is output to the frequency controller 25 as frequency error data.
- the new channel selection data (M, K *) is supplied to the variable frequency divider 102 and the cumulative adder 103 via the data output terminal 15 and the data input terminal 14 of the receiving unit 1.
- the PLL 10 of the receiving unit 1 updates the tuning data of the PLL.
- the receiving apparatus in the present embodiment can reduce the frequency error of the local oscillation signal.
- the frequency error in the IF signal output from the mixer 6 is reduced. Therefore, the pass bandwidth for allowing the desired signal to pass through the filter 8 can be designed to have a smaller bandwidth than in the past.
- the attenuation characteristic of the filter 8 becomes steep, and the effect of increasing the amount of attenuation of unnecessary undesired signals existing in the vicinity of the desired signal can be obtained.
- the filter order can be reduced, the circuit becomes smaller, and the active filter configured with active elements consumes less current. Reduced. Further, as described above, since a large frequency error can be allowed for the reference frequency signal in the receiver 1, the signal source of the reference frequency is If a temperature-compensated crystal oscillator (Temperature Compensated Crystal Oscillator) and V, and an inexpensive oscillator, can be configured with an inexpensive and small crystal unit 11, the effect can be obtained.
- a temperature-compensated crystal oscillator Tempoture Compensated Crystal Oscillator
- V Tempoture Compensated Crystal Oscillator
- an inexpensive oscillator can be configured with an inexpensive and small crystal unit 11, the effect can be obtained.
- the receiving unit 1, the demodulating unit 2 and the CPU 30 are each composed of individual semiconductor components, it is not necessary to provide a dedicated terminal for updating the tuning data of the PLL 10 for the purpose of correcting the frequency error. Absent.
- the data input terminal 14 of the receiver 1, the data output terminal 15 of the demodulator 2, and the CPU connection terminal 50 exchange data between the respective semiconductor components, but these terminals are generally controlled between the semiconductor components. There is no problem as a general-purpose terminal. Therefore, frequency error correction can be achieved without using a dedicated terminal that causes the chip size of the semiconductor component to increase.
- the power integer division method may be used in which PLL 10 is a generally known fractional division method.
- the fractional frequency division method when used, the local frequency of the local oscillator 7 can be selected and controlled at a minute interval, so that the frequency error can be corrected with higher accuracy.
- the received signal is an OFDM modulation method adopted in terrestrial digital broadcasting.
- the frequency error detector 24 detects the frequency error using the signal in the guard interval period characterized by the OFDM modulation signal by the narrowband frequency error detector 27, and further detects the frequency error by the broadband frequency error detector 28.
- the frequency error is detected using a reference symbol called a pilot signal, but the frequency error may be corrected using only the wideband frequency error detector 28. That is, the frequency error detector 24 may detect the frequency error of the signal from the Fourier transform 22.
- the carrier interval unit is about 1 kHz, which is sufficiently small against the error of the output frequency generated by the local oscillator 7, so there is no problem even if it is used for error correction. It doesn't happen.
- the OFD M modulation method is adopted in which the received signal is adopted in digital terrestrial broadcasting.
- the frequency error is detected even in other broadcasting methods and communication methods.
- the frequency error of the IF frequency shown in the present embodiment can be corrected using the demodulating unit 2 that can be used.
- the receiving unit 1 and the demodulating unit 2 may be integrated in the same semiconductor component. Even in this case, the correction of the frequency error of the IF frequency described in the present embodiment can be similarly performed.
- Embodiment 2 of the present invention will be described with reference to FIGS. 3, 4A, and 4B. Note that, unless otherwise specified, the same as in the first embodiment.
- the second embodiment is characterized in that the band-limiting filter 8 in the first embodiment is a variable band-limiting filter 208 whose passband range can be controlled variably.
- FIG. 3 is a block diagram of a receiving apparatus according to Embodiment 2 of the present invention.
- the receiving unit 1 of the receiving apparatus according to the present embodiment includes a high-frequency amplifier 5, a mixer 6, and a variable band through which an IF signal passes from the input terminal 4 side to the demodulating unit 2 side.
- the limiting filter 208 is connected in this order.
- a control signal for controlling the range of the pass band is input to the variable band limiting filter 208 from the data input terminal 14.
- the data input terminal 14 is connected to the CPU 30 via the data output terminal 15 and the frequency controller 25.
- the frequency controller 25 receives the frequency error data from the frequency detector 24.
- the variable band limiting filter 208 capable of variably controlling the range of the pass band as a filter connected to limit the frequency band is supplied from the mixer 6 based on the signal from the frequency detector 24.
- the signal passband range can be changed.
- variable band limiting filter 208 passes the desired signal among the IF signals selected by the mixer 6 and suppresses unnecessary undesired signals existing in the vicinity of the desired signal. Therefore, it is preferable to have a steeper attenuation characteristic.
- the pass band width of variable band limiting filter 208 is widened, and the band of the desired signal is set.
- the CPU 30 performs control so that an IF signal in a range in which the bandwidth corresponding to the frequency error is added to the width is passed.
- the receiving device narrows the pass bandwidth of the variable band limiting filter 208, and the range of only the desired signal bandwidth.
- FIG. 4A is a characteristic diagram of a filter in which the pass bandwidth is controlled in Embodiment 2 of the present invention
- FIG. 4B is a filter in which the slope of the pass bandwidth and the attenuation characteristic is controlled in Embodiment 2 of the present invention.
- the frequency error of the IF signal is assumed to be ⁇ 80 kHz at maximum, and it is assumed that the interference signal (undesired signal to be suppressed) exists at 1.5 MHz.
- the broken line indicates the desired signal and the filter characteristics in the operating state before the IF signal frequency error is corrected, and the solid line indicates the IF signal frequency error is corrected.
- the desired signal and the filter characteristic in the operation state after being performed are shown.
- the filter characteristic example of the variable band limiting filter 208 shown in FIG. 4B shows an example in which the passband width and the slope of the attenuation characteristic are controlled before and after the frequency error of the IF signal is corrected. ing.
- the passband width is controlled to be narrow.
- the cutoff frequency approaches the IF frequency, and interference signals are present. Since 1.5 MHz is controlled so that the attenuation does not change, the slope of the attenuation characteristic becomes gentle. Therefore, particularly in a filter using an active element, the effect of reducing current consumption can be obtained by lowering the filter order.
- the power of the filter type bandpass filter is low. The same effect can be obtained even if a band-pass filter is used. If the pass band is variably controlled, the reception characteristics can be improved and the current consumption can be reduced.
- the same effect can be obtained even when the filter for limiting the frequency band is configured by a SAW filter.
- a SAW filter having a steep attenuation characteristic is used as a filter for limiting the frequency band in the intermediate frequency band. As a result, the reception characteristics can be improved.
- the third embodiment is different from the first embodiment in the configuration of the frequency error detector 24 and the frequency controller 25 that are configured by the demodulator 2.
- the feature is that the detection of the frequency error A fc of the IF signal and the calculation processing of the frequency correction value ⁇ for deriving the frequency error force are not always performed.
- FIG. 5 is a block diagram of a receiving apparatus according to Embodiment 3 of the present invention.
- the demodulator 2 of the receiving device includes a memory 60 for primary storage of data between the divider 25b and the adder / subtractor 25c, and the frequency controller 25 has a frequency error power of the IF signal of the PLL 10.
- the correction value ⁇ is derived, and the correction value ⁇ is temporarily stored in the memory 60.
- the receiving apparatus in the present embodiment detects a frequency error ⁇ fc of the IF signal by frequency error detector 24 of demodulator 2. Then, the multiplier 25a and the divider 25b of the frequency controller 25 output the corrected correction value ⁇ of the PLL 10 to the memory 60, and the memory 60 primarily stores the correction value ⁇ . Also, the adder / subtracter 25c reads the correction value ⁇ from the memory 60, performs addition / subtraction processing using the preset data for PLL10 tuning and correction value ⁇ ⁇ output from the CCU30, and outputs the calculation result to the PLL10. To do.
- the receiving apparatus in the present embodiment can turn off the multiplier 25a and the divider 25b to stop their operations. Even after turning off the multiplier 25a and the divider 25b under the control of the CPU 30, the adder / subtractor 25c reads the correction value ⁇ that is primarily stored from the memory 60, and outputs the PLL10 channel selection output from the CPU 30. Addition / subtraction processing using the preset data and correction value ⁇ can be performed, and the calculation result can be output to PLL10.
- the demodulator 2 of the receiving apparatus in the present embodiment has a switch 39 on the input side of the multiplier 21 and on the output side of the frequency error detector 24. Also good. With this configuration, when the switch 39 is on, the multiplier 21 and the frequency error detector 24 are connected in a loop. When the switch 39 is off, the multiplier 21 does not remove the frequency error, so the frequency error detector 24 detects the frequency error caused by the crystal unit 11 as it is.
- the correction value ⁇ that is primarily stored in the memory 60 is derived in a state where the switch 39 is turned off, so that the frequency error is not temporarily removed by the multiplier 21 and is primarily stored in the memory 60.
- the adder / subtractor 25c performs addition / subtraction processing using the preset data for PLL 10 channel selection output from the CPU 30 and the correction value ⁇ read from the memory 60, and the calculation result is output to the PLL 10.
- the PLL 10 is a fractional frequency division method, and selects and controls the output frequency of the local oscillator 7 at minute intervals. Therefore, the frequency error of the local oscillation signal and IF signal is corrected with high accuracy. Therefore, it is not necessary to correct the frequency error in the multiplier 21, and the frequency error detector 24, the multiplier 25a, and the divider 25b may be turned off.
- the receiving apparatus of the present embodiment always performs detection of the frequency error of the IF signal, calculation processing of the frequency correction value ⁇ derived from the frequency error, and frequency correction in the demodulation unit 2. However, it is possible to obtain the effect of reducing the current consumption by turning off the corresponding circuit.
- the receiving apparatus determines the number and timing of primary storage in the force memory 60, which is limited to the case where the timing at which the frequency correction value ⁇ is primarily stored in the memory 60 is derived once. Even if it changes, the same effect can be acquired.
- the CPU 30 issues an instruction to temporarily store the correction value ⁇ ⁇ in the memory 60, and the CPU 30 issues an instruction to perform the primary storage. You may make it implement regularly, managing with a timer.
- the correction value ⁇ temporarily stored in the memory 60 is not instantaneously appropriate.
- BER Bit Error Rate
- Embodiment 4 of the present invention will be described with reference to FIG. Unless otherwise explained, it is the same as the first embodiment.
- This embodiment is characterized in that the arithmetic processing (the above (Equation 9)) performed by the frequency controller 25 (FIG. 2) of the demodulation unit 2 in Embodiment 1 is performed by software on the CPU 30 or the like. It is.
- FIG. 7 is a block diagram of a receiving apparatus according to Embodiment 4 of the present invention.
- the frequency error A fc of the IF signal detected by the frequency error detector 24 is read into the CPU 30 via the CPU connection terminal 50.
- the CPU 30 is determined by the read frequency error A fc and the circuit configuration of the PLL 10, and the reference signal frequency “Fxtal” preset by the CPU 30, the division ratio “NR” of the reference divider 105, and the prescaler 101 Using the frequency division ratio “N” and the number of bits “m” of the cumulative adder 103, the correction value ⁇ (the above (Equation 9)) is calculated.
- the CPU 30 calculates the channel selection preset data ( ⁇ , ⁇ ) of PLL10 and the new channel selection data ( ⁇ , ⁇ ⁇ ⁇ ) from the correction value ⁇ , and the new channel selection data is obtained. Output to PLL10 via data input terminal 14 of receiver 1.
- the PLL 10 can remove the local oscillation signal power frequency error output from the local oscillator 7 and can also remove the frequency error of the IF signal frequency power.
- the receiving apparatus uses the force CPU30 to perform the calculation shown in (Equation 9) performed by the frequency controller 25 and the correction value ⁇ calculated by the CPU30. Since K does not easily change instantaneously and is determined by the accuracy of the reference signal frequency, it is easy to realize K at a low calculation speed that can be handled by the CPU 30 software. Also, (Equation 9) calculated by CPU30 is the same as PLL10 except for A fc calculated by demodulator 2. The setting value that sets the conditions of each circuit that constitutes the CPU power is also used. For this reason, if the calculation is realized by software, for example, it becomes easy to change the circuit of the PLL 10 of the receiving unit 1.
- the receiving apparatus of the present invention can reduce the frequency error of the local oscillation signal by the above configuration. As a result, the attenuation characteristic of the filter becomes steep, the amount of attenuation of unnecessary undesired signals existing in the vicinity of the desired signal can be increased, and the filter can be used for a television set or a portable terminal mounted in an automobile.
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Superheterodyne Receivers (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
Description
Claims
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP06766480A EP1777831A4 (en) | 2005-07-29 | 2006-06-08 | RECEIVER DEVICE AND THE SAME ELECTRONIC DEVICE USED THEREOF |
| JP2006536954A JP4245049B2 (ja) | 2005-07-29 | 2006-06-08 | 受信装置およびそれを用いた電子機器 |
| US11/572,942 US7733986B2 (en) | 2005-07-29 | 2006-06-08 | Receiver and electronic apparatus |
| CN2006800009207A CN101032088B (zh) | 2005-07-29 | 2006-06-08 | 接收装置及采用该接收装置的电子设备 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005-219960 | 2005-07-29 | ||
| JP2005219960 | 2005-07-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2007013226A1 true WO2007013226A1 (ja) | 2007-02-01 |
Family
ID=37683130
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2006/311505 Ceased WO2007013226A1 (ja) | 2005-07-29 | 2006-06-08 | 受信装置およびそれを用いた電子機器 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US7733986B2 (ja) |
| EP (1) | EP1777831A4 (ja) |
| JP (1) | JP4245049B2 (ja) |
| CN (1) | CN101032088B (ja) |
| WO (1) | WO2007013226A1 (ja) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009116262A1 (ja) * | 2008-03-18 | 2009-09-24 | パナソニック株式会社 | シンセサイザと受信装置 |
| JP2010016723A (ja) * | 2008-07-04 | 2010-01-21 | Toyota Industries Corp | 周波数補正システム及び受信機 |
| JP5310728B2 (ja) * | 2008-08-28 | 2013-10-09 | パナソニック株式会社 | シンセサイザ及びこれを用いた受信装置及び電子機器 |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4849329B2 (ja) * | 2006-10-06 | 2012-01-11 | ソニー株式会社 | 受信装置および受信方法、並びに、プログラム |
| JP2010093625A (ja) * | 2008-10-09 | 2010-04-22 | Toshiba Corp | ビデオ信号復調回路 |
| US9071493B2 (en) | 2009-06-29 | 2015-06-30 | Qualcomm Incorporated | Dual frequency tracking loop for OFDMA systems |
| US9137069B2 (en) * | 2012-08-07 | 2015-09-15 | Intel Deutschland Gmbh | Systems and methods to frequency shift unwanted signal components |
| EP2975772B1 (en) * | 2013-03-15 | 2018-03-07 | Sony Corporation | Receiver and electronic appliance |
| CN104682978B (zh) | 2013-12-02 | 2017-08-29 | 上海东软载波微电子有限公司 | 载波频偏处理方法和装置及接收机 |
| CN204068947U (zh) * | 2014-07-12 | 2014-12-31 | 无锡中星微电子有限公司 | 可调中频无线接收机及蓝牙模块 |
| KR101811221B1 (ko) * | 2016-02-17 | 2017-12-21 | 주식회사 이노와이어리스 | 신호 분석기의 wcdma 신호 타이밍 오프셋 처리 방법 |
| EP3376666A1 (fr) * | 2017-03-14 | 2018-09-19 | STMicroelectronics (ALPS) SAS | Dispositif d'oscillateur local à faible consommation |
| CN112485520B (zh) * | 2020-12-03 | 2024-03-22 | 成都市精准时空科技有限公司 | 基于电压采样的绝对频差测量方法及系统及装置及介质 |
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| US5970105A (en) * | 1998-05-11 | 1999-10-19 | Cleveland Medical Devices Inc. | Apparatus and method for efficient wireless communications in the presence of frequency error |
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- 2006-06-08 JP JP2006536954A patent/JP4245049B2/ja not_active Expired - Fee Related
- 2006-06-08 WO PCT/JP2006/311505 patent/WO2007013226A1/ja not_active Ceased
- 2006-06-08 EP EP06766480A patent/EP1777831A4/en not_active Withdrawn
- 2006-06-08 US US11/572,942 patent/US7733986B2/en not_active Expired - Fee Related
- 2006-06-08 CN CN2006800009207A patent/CN101032088B/zh not_active Expired - Fee Related
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| JPH0249223U (ja) * | 1988-09-30 | 1990-04-05 | ||
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| WO2009116262A1 (ja) * | 2008-03-18 | 2009-09-24 | パナソニック株式会社 | シンセサイザと受信装置 |
| JP2009225234A (ja) * | 2008-03-18 | 2009-10-01 | Panasonic Corp | シンセサイザと、これを用いた受信装置、及び電子機器 |
| US8594608B2 (en) | 2008-03-18 | 2013-11-26 | Panasonic Corporation | Synthesizer and reception device |
| JP2010016723A (ja) * | 2008-07-04 | 2010-01-21 | Toyota Industries Corp | 周波数補正システム及び受信機 |
| JP5310728B2 (ja) * | 2008-08-28 | 2013-10-09 | パナソニック株式会社 | シンセサイザ及びこれを用いた受信装置及び電子機器 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4245049B2 (ja) | 2009-03-25 |
| CN101032088B (zh) | 2012-06-27 |
| US20090232259A1 (en) | 2009-09-17 |
| US7733986B2 (en) | 2010-06-08 |
| JPWO2007013226A1 (ja) | 2009-02-05 |
| EP1777831A1 (en) | 2007-04-25 |
| CN101032088A (zh) | 2007-09-05 |
| EP1777831A4 (en) | 2013-01-16 |
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